CYPRESS CY62167DV30LL

CY62167DV30 MoBL®
16-Mbit (1 M × 16) Static RAM
Features
■
Thin small outline package (TSOP-I) configurable as
1 M × 16 or as 2 M × 8 SRAM
■
Wide voltage range: 2.2 V – 3.6 V
■
Ultra-low active power: Typical active current:
2 mA at f = 1 MHz
■
Ultra-low standby power
■
Easy memory expansion with CE1, CE2 and OE features
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed / power
■
Available in Pb-free and non Pb-free 48-ball very fine-pitch
ball grid array (VFBGA) and 48-pin TSOP I package
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE1 HIGH or
CE2 LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a Write operation (CE1 LOW, CE2 HIGH and WE
LOW).
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A19). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A19).
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory appear on
I/O8 to I/O15. See the truth table at the back of this data sheet
for a complete description of Read and Write modes.
Functional Description
The CY62167DV30 is a high-performance CMOS static RAM
organized as 1M words by 16-bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
Logic Block Diagram
1M × 16 / 2M x 8
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
A11
A12
A13
A14
A15
A16
A17
A18
A19
BHE
WE
CE2
CE1
OE
BLE
Power-Down
Circuit
Cypress Semiconductor Corporation
Document Number : 38-05328 Rev. *J
•
198 Champion Court
BHE
BLE
•
CE2
CE1
San Jose, CA 95134-1709
•
408-943-2600
Revised July 27, 2011
CY62167DV30 MoBL®
Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics
(Over the Operating Range) ............................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics
(Over the Operating Range) ............................................... 5
Data Retention Waveform ................................................ 6
Switching Characteristics
Over the Operating Range ................................................. 6
Document Number : 38-05328 Rev. *J
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 11
Ordering Code Definitions ........................................ 12
Ordering Information ...................................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ...................................................... 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
Page 2 of 17
CY62167DV30 MoBL®
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62167DV30LL
Operating ICC(mA)
Speed
(ns)
Min
Typ[1]
Max
2.2
3.0
3.6
f = 1 MHz
f = fMax
Standby ISB2(μA)
Typ[1]
Max
Typ[1]
Max
Typ[1]
Max
2
4
15
30
2.5
22
12
25
55
70
Pin Configuration
Figure 1. 48-ball VFBGA Top View[2, 3, 4]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12 DNU
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
A19
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
DNU
H
48-Pin TSOP-I (Forward)(1 M × 16 / 2M × 8)
Top View
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
[5]
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
2. NC pins are not connected on the die.
3. DNU pins have to be left floating.
4. Ball H6 for the FBGA package can be used to upgrade to a 32M density.
5. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8
SRAM by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used (DNU).
Document Number : 38-05328 Rev. *J
Page 3 of 17
CY62167DV30 MoBL®
Maximum Ratings
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Latch-up current ..................................................... > 200 mA
Storage temperature ................................ –65 °C to +150 °C
Operating Range
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Device
Supply voltage to ground potential ...... –0.2 V to VCC + 0.3 V
DC voltage applied to outputs
in High-Z state[6, 7] ................................ –0.2 V to VCC + 0.3 V
Ambient
Temperature
VCC[8]
–40 °C to +85 °C
2.20 V to
3.60 V
Range
CY62167DV30LL Industrial
DC input voltage[6, 7] ............................. –0.2 V to VCC + 0.3 V
Electrical Characteristics (Over the Operating Range)
CY62167DV30-55
Parameter
VOH
VOL
VIH
VIL
Description
CY62167DV30-70
Test Conditions
Unit
Min
Typ[9]
Max
Min
Typ[9]
Max
–
–
2.0
–
–
V
–
0.4
V
–
VCC
+0.3
V
V
–
0.6
V
Output HIGH voltage IOH = –0.1 mA
VCC = 2.20 V
2.0
IOH = –1.0 mA
VCC = 2.70 V
2.4
Output LOW voltage IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
IOL = 2.1 mA
VCC = 2.70 V
VCC = 2.2 V to 2.7 V
1.8
–
1.8
VCC = 2.7 V to 3.6 V
2.2
VCC
+0.3 V
VCC = 2.2 V to 2.7 V
–0.3
0.6
–0.3
Input HIGH voltage
Input LOW voltage
2.4
–
VCC= 2.7 V to 3.6 V
IIX
Input leakage current GND ≤ VI ≤ VCC
IOZ
Output leakage
current
ICC
VCC operating supply VCC = VCC(max)
IOUT = 0 mA
current
CMOS levels
2.2
0.8
GND ≤ VO ≤ VCC, output disabled
f = fMax = 1/tRC
0.8
–1
–
+1
–1
–
+1
μA
–1
–
+1
–1
–
+1
μA
–
15
30
–
12
25
mA
2
4
2
4
f = 1 MHz
ISB1
Automatic
power-down
current —
CMOS inputs
CE1 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V,
VIN ≥ VCC – 0.2 V, VIN ≤ 0.2 V,
f = fMax (address and data only),
f = 0 (OE, WE), VCC = 3.60 V
–
2.5
22
–
2.5
22
μA
ISB2
Automatic
power-down
current —
CMOS Inputs
CE1 ≥ VCC – 0.2 V or CE2 ≤ 0.2 V
VIN ≥ VCC – 0.2 V or VIN ≤ 0.2V,
f = 0, VCC = 3.60 V
–
2.5
22
–
2.5
22
μA
Notes
6. VIL(min.) = –2.0 V for pulse durations less than 20 ns.
7. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
8. Full Device AC operation requires linear VCC ramp from 0 to VCC(min.) and VCC must be stable at VCC(min) for 500 μs.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
Document Number : 38-05328 Rev. *J
Page 4 of 17
CY62167DV30 MoBL®
Capacitance
Parameter[10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
8
pF
10
pF
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter[10]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
VFBGA
TSOP I
Unit
55
60
°C / W
16
4.3
°C / W
Still air, soldered on a 3 × 4.5 inch,
2-layer printed circuit board
AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
VCC
90%
10%
50 pF[12]
GND
Rise Time = 1 V/ns
R2
90%
10%
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.5 V
3.0 V
Unit
R1
16667
1103
Ω
R2
15385
1554
Ω
RTH
8000
645
Ω
VTH
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for data retention
ICCDR
Data retention current
tCDR[10]
Chip deselect to data retention time
tR[12]
Operation recovery time
Min
Typ[11]
Max
Unit
1.5
–
–
V
–
–
10
μA
0
–
–
ns
CY62167DV30LL-55
55
–
–
ns
CY62167DV30LL-70
70
Conditions
VCC= 1.5 V,
CE1 ≥ VCC – 0.2 V or CE2 ≤ 0.2 V,
VIN ≥ VCC – 0.2 V or VIN ≤ 0.2 V
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
12. Full device operation requires linear VCC ramp from VDR to VCC(min.) ≥ 100 μs or stable at VCC(min.) ≥ 100 μs.
Document Number : 38-05328 Rev. *J
Page 5 of 17
CY62167DV30 MoBL®
Data Retention Waveform[13]
VCC
DATA RETENTION MODE
VDR ≥ 1.5 V
VCC, min.
tCDR
CE1 or
VCC, min.
tR
BHE,BLE
or
CE2
Switching Characteristics Over the Operating Range
Parameter[14]
Description
55 ns
Min
70 ns
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
70
–
ns
tAA
Address to data valid
–
55
–
70
ns
tOHA
Data hold from address change
10
–
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
55
–
70
ns
tDOE
OE LOW to data valid
–
25
–
35
ns
tLZOE
OE LOW to low Z[15]
5
–
5
–
ns
[15, 16]
tHZOE
OE HIGH to high Z
–
20
–
25
ns
tLZCE
CE1 LOW and CE2 HIGH to low Z[15]
10
–
10
–
ns
[15, 16]
tHZCE
CE1 HIGH and CE2 LOW to high Z
–
20
–
25
ns
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down
–
55
–
70
ns
tDBE
BLE/BHE LOW to data valid
–
55
–
70
ns
[15]
tLZBE
BLE/BHE LOW to low Z
10
–
10
–
ns
tHZBE
BLE/BHE HIGH to high Z[15, 16]
–
20
–
25
ns
tWC
Write cycle time
55
–
70
–
ns
Write Cycle[17]
tSCE
CE1 LOW and CE2 HIGH to write end
40
–
60
–
ns
tAW
Address setup to write end
40
–
60
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
40
–
45
–
ns
tBW
BLE/BHE LOW to write end
40
–
60
–
ns
tSD
Data setup to write end
25
–
30
–
ns
tHD
Data hold from write end
0
–
0
–
ns
[15, 16]
tHZWE
WE LOW to high-Z
–
20
–
25
ns
tLZWE
WE HIGH to low-Z[15]
10
–
10
–
ns
Notes
13. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
14. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0
to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
17. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the Write.
Document Number : 38-05328 Rev. *J
Page 6 of 17
CY62167DV30 MoBL®
Switching Waveforms
Figure 2. Read Cycle 1 (Address Transition Controlled)[18, 19]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 3. Read Cycle 2 (OE Controlled)[19, 20]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tLZBE
OE
tDBE
tHZBE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
18. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
19. WE is HIGH for read cycle.
20. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number : 38-05328 Rev. *J
Page 7 of 17
CY62167DV30 MoBL®
Switching Waveforms (continued)
Figure 4. Write Cycle 1 (WE Controlled)[21, 22, 23]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
See Note 24
tHZOE
Notes
21. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal
that terminates the Write.
22. Data I/O is high-impedance if OE = VIH.
23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
24. During this period, the I/Os are in output state and input signals should not be applied.
Document Number : 38-05328 Rev. *J
Page 8 of 17
CY62167DV30 MoBL®
Switching Waveforms (continued)
Figure 5. Write Cycle 2 (CE1 or CE2 Controlled)[25, 26, 27]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
Note 28
tHZOE
Figure 6. Write Cycle 3 (WE Controlled, OE LOW)[27]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
WE
tSA
tHA
tPWE
tSD
DATA I/O
Note 28
tHD
VALID DATA
tHZWE
tLZWE
Notes
25. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal
that terminates the Write.
26. Data I/O is high-impedance if OE = VIH.
27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
28. During this period, the I/Os are in output state and input signals should not be applied.
Document Number : 38-05328 Rev. *J
Page 9 of 17
CY62167DV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[29]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
Note 30
tHD
VALID DATA
Notes
29. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
30. During this period, the I/Os are in output state and input signals should not be applied.
Document Number : 38-05328 Rev. *J
Page 10 of 17
CY62167DV30 MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
L
H
L
Mode
Power
High Z
Deselect/Power-down
Standby (ISB)
X
High Z
Deselect/Power-down
Standby (ISB)
H
H
High Z
Deselect/Power-down
Standby (ISB)
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
H
L
H
L
High Z (I/O8–I/O15);
Data out (I/O0–I/O7)
Read
Active (ICC)
H
H
L
L
H
Data out (I/O8–I/O15);
High Z (I/O0–I/O7)
Read
Active (ICC)
L
H
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
High Z (I/O8–I/O15);
Data in (I/O0–I/O7)
Write
Active (ICC)
L
H
L
X
L
H
Data in (I/O8–I/O15);
High Z (I/O0–I/O7)
Write
Active (ICC)
L
H
H
H
L
H
High Z
Output disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output disabled
Active (ICC)
Document Number : 38-05328 Rev. *J
Inputs/Outputs
Page 11 of 17
CY62167DV30 MoBL®
Ordering Information
Speed
(ns)
55
70
Ordering Code
CY62167DV30LL-55BVI
CY62167DV30LL-55BVXI
CY62167DV30LL-55ZXI
CY62167DV30LL-70BVI
Package
Package Type
Diagram
51-85178 48-ball FBGA (8 × 9.5 × 1 mm)
48-ball FBGA (8 × 9.5 × 1 mm) (Pb-free)
51-85183 48-pin TSOP-I (12 × 18.4 × 1 mm) (Pb-free)
51-85178 48-ball FBGA (8 × 9.5 × 1 mm)
Operating
Range
Industrial
Please contact your local Cypress sales representative for availability of these parts
Ordering Code Definitions
CY
621
6
7D
V30 LL
XX
XXX I
Tem perature Grades
I = Industrial
Package Type = ZX : TSOP I (Pb-free)
BVX : VFBGA (Pb-free)
BV : VFBGA
Speed Grade
Low Power
Voltage = 3.0
Bus W idth = X16
D = 130nm Technology
Density = 16 M bit
M oBL SRAM Fam ily
Com pany ID: CY = Cypress
Document Number : 38-05328 Rev. *J
Page 12 of 17
CY62167DV30 MoBL®
Package Diagram
Figure 8. 48-ball VFBGA (8 × 9.5 × 1 mm) (51-85178)
51-85178 *A
Document Number : 38-05328 Rev. *J
Page 13 of 17
CY62167DV30 MoBL®
Figure 9. 48-pin TSOP-I (12 × 18.4 × 1 mm) (51-85183)
51-85183 *C
Document Number : 38-05328 Rev. *J
Page 14 of 17
CY62167DV30 MoBL®
Acronyms
Document Conventions
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
Symbol
I/O
input/output
°C
degrees Celsius
SRAM
static random access memory
μA
microampere
VFBGA
very fine ball grid array
mA
milliampere
TSOP
thin small outline package
MHz
megahertz
ns
nanosecond
pF
picofarad
V
volt
Ω
ohm
W
watts
Acronym
Document Number : 38-05328 Rev. *J
Unit of Measure
Page 15 of 17
CY62167DV30 MoBL®
Document History Page
Document Title: CY62167DV30 MoBL®, 16-Mbit (1 M × 16) Static RAM
Document Number: 38-05328
ECN
Orig. of
Change
Submission
Date
**
118408
GUG
09/30/02
New Datasheet
*A
123692
DPM
02/11/03
Changed Advanced to Preliminary
Added package diagram
Revision
Description of Change
*B
126555
DPM
04/25/03
Minor change: Changed Sunset Owner from DPM to HRT
*C
127841
XRJ
09/10/03
Added 48 TSOP I package
*D
205701
AJU
*E
238050
KKV/AJU
See ECN
Replaced 48-ball VFBGA package diagram; Modified Package Name in
Ordering Information table from BV48A to BV48B
*F
304054
PCI
See ECN
Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #12 on page #4
Added Pb-free packages on page # 10
*G
492895
VKN
See ECN
Modified datasheet to explain x8 configurability.
Removed L power bin from the product offering
Updated Ordering Information Table
*H
2896036
AJU
03/19/10
Removed 45-ns. Removed inactive parts from Ordering Information.
Updated Packaging Information
Updated links in Sales, Solutions, and Legal Information.
*I
3067267
RAME
11/08/10
Updated datasheet as per new template
Added Ordering Code Definitions, Acronyms and Units of Measure.
Updated all table notes to footnote.
Package diagram updated 51-85178 from ** to *A
*J
3329789
RAME
07/27/11
Removed references to AN1064 SRAM system guidelines.
Updated template according to current CY standards.
Document Number : 38-05328 Rev. *J
Changed BYTE pin usage description for 48 TSOPI package
Page 16 of 17
CY62167DV30 MoBL®
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number : 38-05328 Rev. *J
Revised July 27, 2011
Page 17 of 17
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their respective holders.