CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09099V CY7C09179V 3.3 V 32K/128K × 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features ❐ ■ True Dual-Ported memory cells which enable simultaneous access of the same memory location ■ ❐ Active = 115 mA (typical) Standby = 10 A (typical) ■ Fully synchronous interface for easier operation Flow-through and Pipelined devices ■ Burst counters increment addresses internally ■ 32K × 9 organizations (CY7C09179V) ■ Shorten cycle times ■ 128K × 8 organizations (CY7C09099V) ■ Minimize bus noise ■ Three Modes ❐ Flow-through ❐ Pipelined ❐ Burst ■ Supported in Flow-through and Pipelined modes ■ Dual Chip Enables for easy depth expansion ■ Automatic power down ■ Commercial and Industrial temperature ranges ■ Available in 100-pin TQFP ■ Pb-free packages available ■ ■ Pipelined output mode on both ports enables fast 100-MHz operation 0.35-micron CMOS for optimum speed and power ■ High-speed clock to data access ■ 3.3-V low operating power 7.5[1]/12 ns (max.) For a complete list of related documentation, click here. Note 1. See page 9 and page 10 for Load Conditions. Cypress Semiconductor Corporation Document Number: 38-06043 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 26, 2014 CY7C09099V CY7C09179V Logic Block Diagram R/WL R/WR OEL OER CE0L CE1L 1 0 0 0/1 1 0/1 FT/PipeL [3] A0–A14/15/16L CLKL ADSL CNTENL CNTRSTL 0/1 0 0 1 0/1 8/9 [2] I/O0L–I/O7/8L CE0R CE1R 1 FT/PipeR 8/9 I/O Control [2] I/O0R–I/O7/8R I/O Control 15/16/17 15/16/17 Counter/ Address Register Decode True Dual-Ported RAM Array Counter/ Address Register Decode [3] A0–A14/15/16R CLKR ADSR CNTENR CNTRSTR Notes 2. I/O0–I/O7 for ×8 devices, I/O0–I/O8 for ×9 devices 3. A0–A14 for 32K and A0–A16 for 128K devices Document Number: 38-06043 Rev. *I Page 2 of 28 CY7C09099V CY7C09179V Functional Description The CY7C09099V and CY7C09179V are high speed synchronous CMOS 128K × 8 and 32K × 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines enable minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 7.5 ns[5] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode, data is available tCD1 = 22 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to enable the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables enables easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter increments on each LOW-to-HIGH transition of that port’s clock signal. This reads/writes one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and loops back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. Notes 4. When writing simultaneously to the same location, the final value cannot be guaranteed. 5. See page 9 and page 10 for Load Conditions. Document Number: 38-06043 Rev. *I Page 3 of 28 CY7C09099V CY7C09179V Contents Pin Configurations ........................................................... 5 Selection Guide ................................................................ 7 Pin Definitions .................................................................. 7 Maximum Ratings ............................................................. 8 Operating Range ............................................................... 8 Electrical Characteristics ................................................. 8 Capacitance ...................................................................... 9 Switching Characteristics .............................................. 11 Switching Waveforms .................................................... 12 Read/Write and Enable Operation.................................. 23 Address Counter Control Operation............................. 23 Document Number: 38-06043 Rev. *I Ordering Information ...................................................... 24 128 K × 8 3.3 V Synchronous Dual-Port SRAM ........ 24 32 K × 9 3.3 V Synchronous Dual-Port SRAM.......... 24 Ordering Code Definitions ......................................... 24 Package Diagram ............................................................ 25 Acronyms ........................................................................ 26 Document Conventions ................................................. 26 Units of Measure ....................................................... 26 Document History Page ................................................. 27 Sales, Solutions, and Legal Information ...................... 28 Worldwide Sales and Design Support ....................... 28 Products .................................................................... 28 PSoC Solutions ......................................................... 28 Page 4 of 28 CY7C09099V CY7C09179V Pin Configurations NC NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC Figure 1. 100-pin TQFP (Top View) - CY7C09099V (128K × 8) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R A15L 11 65 A15R A16L 12 64 A16R VCC 13 63 GND NC 14 62 NC NC 15 61 NC NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R CNTRSTL 20 56 CNTRSTR R/WL 21 55 R/WR OEL 22 54 OER FT/PIPEL 23 53 FT/PIPER NC 24 52 GND NC 25 51 NC CY7C09099V Document Number: 38-06043 Rev. *I NC NC NC I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L NC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 5 of 28 CY7C09099V CY7C09179V NC A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR GND GND ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L NC NC Figure 2. 100-pin TQFP (Top View) - CY7C09179V (32K × 9) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R [6] A15L 11 65 A15R [6] 64 A16R [7] 63 GND [7] CY7C09179V A16L 12 VCC 13 NC 14 62 NC NC 15 61 NC NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R CNTRSTL 20 56 CNTRSTR R/WL 21 55 R/WR OEL 22 54 OER FT/PIPEL 23 53 FT/PIPER NC 24 52 GND NC 25 51 NC NC NC I/O8R I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O8L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes 6. This pin is NC for CY7C09179V 7. This pin is NC for CY7C09179V Document Number: 38-06043 Rev. *I Page 6 of 28 CY7C09099V CY7C09179V Selection Guide CY7C09099V -7[8] CY7C09099V CY7C09179V -12 fMAX2 (MHz) (Pipelined) 83 50 Max. Access Time (ns) (Clock to Data, Pipelined) 7.5 12 Description Typical Operating Current ICC (mA) 155 115 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) 25 20 Typical Standby Current for ISB3 (A) (Both Ports CMOS Level) 10 10 Pin Definitions Left Port Right Port Description A0L–A16L A0R–A16R Address Inputs (A0–A14 for 32K and A0–A16 for 128K devices). ADSL ADSR Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CE0L, CE1L CE0R, CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). CLKL CLKR Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. CNTENL CNTENR Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRSTL CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. I/O0L–I/O8L I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for ×8 devices; I/O0–I/O8 for ×9 devices). OEL OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. R/WL R/WR Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPEL FT/PIPER Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NC No Connect. VCC Power Input. Note 8. See page 9 and page 10 for Load Conditions. Document Number: 38-06043 Rev. *I Page 7 of 28 CY7C09099V CY7C09179V Maximum Ratings Output Current into Outputs (LOW) ............................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[9] Storage Temperature .............................. –65 °C to +150 °C Ambient Temperature with Power Applied .................................. –55 °C to +125 °C Static Discharge Voltage ......................................... > 2001 V Latch-Up Current ................................................... > 200 mA Operating Range Range Supply Voltage to Ground Potential .............–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State ...................... –0.5 V to VCC + 0.5 V Commercial [10] Industrial Ambient Temperature VCC 0 °C to +70 °C 3.3 V 300 mV –40 °C to +85 °C 3.3 V 300 mV DC Input Voltage ................................ –0.5 V to VCC + 0.5 V Electrical Characteristics Over the Operating Range VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Max Min Typ Max Unit Output HIGH Voltage (VCC = Min., IOH = –4.0 mA) Output LOW Voltage (VCC = Min., IOH = +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Standby Current (Both Ports TTL Level)[12] CEL & CER VIH, f = fMAX Standby Current (One Port TTL Level)[12] CEL | CER VIH, f = fMAX Standby Current (Both Ports CMOS Level)[12] CEL & CER VCC – 0.2 V, f=0 Standby Current (One Port CMOS Level)[12] CEL | CER VIH, f = fMAX Typ VOH Description Min Parameter CY7C09099V/ CY7C09179V -7[11] -12 2.4 – – 2.4 – – V – 0.4 – 0.4 V 2.0 – –10 – 155 275 – 0.8 10 275 390 2.0 – –10 – 115 – – 0.8 10 205 – V V A mA mA Commercial Industrial[10] 25 85 85 120 20 – 50 – mA mA Commercial Industrial[10] 105 165 165 210 85 – 140 – mA mA Commercial Industrial[10] 10 10 250 250 10 – 250 – A A Commercial Industrial[10] 95 125 125 170 75 – 100 – mA mA Commercial Industrial[10] Notes 9. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 10. Industrial parts are available in CY7C09099V 11. See page 9 and page 10 for Load Conditions. 12. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). Document Number: 38-06043 Rev. *I Page 8 of 28 CY7C09099V CY7C09179V Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Max Unit 10 pF 10 pF Figure 3. AC Test Loads 3.3 V 3.3 V R1 = 590 OUTPUT C = 30 pF OUTPUT RTH = 250 R1 = 590 OUTPUT C = 30 pF R2 = 435 C = 5 pF R2 = 435 VTH = 1.4 V (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) Figure 4. AC Test Loads (Applicable to -6 and -7 only)[13] ALL INPUT PULSES Z0 = 50 R = 50 OUTPUT 3.0 V C GND VTH = 1.4 V 10% 3 ns 90% 90% 10% 3 ns (a) Load 1 (-6 and -7 only) Note 13. Test Conditions: C = 10 pF. Document Number: 38-06043 Rev. *I Page 9 of 28 CY7C09099V CY7C09179V Figure 5. Load Derating Curve 0. 60 (ns) for all -7 access times 0. 50 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 30 35 Capacitance (pF) Document Number: 38-06043 Rev. *I Page 10 of 28 CY7C09099V CY7C09179V Switching Characteristics Over the Operating Range CY7C09099V CY7C09179V Parameter Description -7[14] Unit -12 Min Max Min Max – 45 – 33 MHz fMAX1 fMax Flow-through fMAX2 fMax Pipelined – 83 – 50 MHz tCYC1 Clock Cycle Time - Flow-through 22 – 30 – ns tCYC2 Clock Cycle Time - Pipelined 12 – 20 – ns tCH1 Clock HIGH Time - Flow-through 7.5 – 12 – ns tCL1 Clock LOW Time - Flow-through 7.5 – 12 – ns tCH2 Clock HIGH Time - Pipelined 5 – 8 – ns tCL2 Clock LOW Time - Pipelined 5 – 8 – ns tR Clock Rise Time – 3 – 3 ns tF Clock Fall Time – 3 – 3 ns tSA Address Set-Up Time 4 – 4 – ns tHA Address Hold Time 0 – 1 – ns tSC Chip Enable Set-Up Time 4 – 4 – ns tHC Chip Enable Hold Time 0 – 1 – ns tSW R/W Set-Up Time 4 – 4 – ns tHW R/W Hold Time 0 – 1 – ns tSD Input Data Set-Up Time 4 – 4 – ns tHD Input Data Hold Time 0 – 1 – ns tSAD ADS Set-Up Time 4 – 4 – ns tHAD ADS Hold Time 0 – 1 – ns tSCN CNTEN Set-Up Time 4.5 – 5 – ns tHCN CNTEN Hold Time 0 – 1 – ns tSRST CNTRST Set-Up Time 4 – 4 – ns tHRST CNTRST Hold Time 0 – 1 – ns tOE Output Enable to Data Valid – 9 – 12 ns [15, 16] OE to Low Z 2 – 2 – ns tOHZ[15, 16] OE to High Z 1 7 1 7 ns tCD1 Clock to Data Valid - Flow-through – 18 – 25 ns tCD2 Clock to Data Valid - Pipelined – 7.5 – 12 ns tDC Data Output Hold After Clock HIGH 2 – 2 – ns tCKHZ[15, 16] Clock HIGH to Output High Z 2 9 2 9 ns tCKLZ[15, 16] Clock HIGH to Output Low Z 2 – 2 – ns tOLZ Notes 14. See page 9 and page 10 for Load Conditions. 15. Test conditions used are Load 2. 16. This parameter is guaranteed by design, but it is not production tested. Document Number: 38-06043 Rev. *I Page 11 of 28 CY7C09099V CY7C09179V Switching Characteristics (continued) Over the Operating Range CY7C09099V CY7C09179V Parameter Description -7[14] Unit -12 Min Max Min Max Port to Port Delays tCWDD Write Port Clock HIGH to Read Data Delay – 35 – 40 ns tCCS Clock to Clock Set-Up Time – 10 – 15 ns Switching Waveforms Figure 6. Read Cycle for Flow-through Output (FT/PIPE = VIL)[17, 18, 19, 20] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS An An+1 tCD1 DATAOUT An+2 tCKHZ tDC Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tDC tOLZ OE tOE Notes 17. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 18. ADS = VIL, CNTEN and CNTRST = VIH. 19. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. 20. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document Number: 38-06043 Rev. *I Page 12 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[21, 22, 23, 24] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSW tSA tHW tHA tSC tHC CE1 R/W ADDRESS DATAOUT An An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes 21. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 22. ADS = VIL, CNTEN and CNTRST = VIH. 23. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. 24. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document Number: 38-06043 Rev. *I Page 13 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 8. Bank Select Pipelined Read[25, 26] - tCH2 tCYC2 tCL2 CLKL tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE0(B1) tCD2 tHC tSC tCD2 tHA tSA A0 ADDRESS(B2) tDC A1 tDC tSC tCKLZ A3 A2 tCKHZ D3 D1 D0 DATAOUT(B1) tCD2 tCKHZ A4 A5 tHC CE0(B2) tSC tHC tCD2 DATAOUT(B2) tCKHZ tCD2 D4 D2 tCKLZ tCKLZ Notes 25. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 26. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. Document Number: 38-06043 Rev. *I Page 14 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 9. Left Port Write to Flow-through Right Port Read[27, 28, 29, 30] CLKL tSW tHW tSA tHA R/WL ADDRESSL NO MATCH MATCH tHD tSD DATAINL VALID tCCS CLKR R/WR ADDRESSR tCD1 tSW tSA tHW tHA NO MATCH MATCH tCWDD DATAOUTR tCD1 VALID tDC VALID tDC Notes 27. The same waveforms apply for a right port write to flow-through left port read. 28. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 29. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to. 30. It tCCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case. Document Number: 38-06043 Rev. *I Page 15 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[31, 32, 33, 34] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS tSA An+1 An+2 tHA DATAIN An+2 An+3 An+4 tSD tHD tCD2 tCKHZ Dn+2 tCD2 tCKLZ Qn DATAOUT READ Qn+3 NO OPERATION WRITE READ Notes 31. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 32. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 33. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 34. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document Number: 38-06043 Rev. *I Page 16 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[35, 36, 37, 38] tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 R/W ADDRESS tSW tHW tSW tHW An tSA An+1 An+2 tHA An+3 An+4 An+5 tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCKLZ tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Notes 35. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 36. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 37. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 38. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document Number: 38-06043 Rev. *I Page 17 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 12. Flow-through Read-to-Write-to-Read (OE = VIL)[39, 40, 41, 42, 43] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS An+1 tSA DATAIN DATAOUT An+2 An+2 tSD tHA An+3 An+4 tHD Dn+2 tCD1 tCD1 Qn tCD1 Qn+1 tDC tCKHZ READ tCD1 Qn+3 NO OPERATION tCKLZ WRITE tDC READ Notes 39. ADS = VIL, CNTEN and CNTRST = VIH. 40. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 41. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 42. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 43. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document Number: 38-06043 Rev. *I Page 18 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 13. Flow-through Read-to-Write-to-Read (OE Controlled)[44, 45, 46, 47, 48] tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW An ADDRESS tSA DATAIN An+1 tSD tHA An+3 An+4 An+5 tHD Dn+2 tDC tCD1 DATAOUT An+2 Dn+3 tOE tCD1 Qn tCD1 Qn+4 tOHZ tCKLZ tDC OE READ WRITE READ Notes 44. ADS = VIL, CNTEN and CNTRST = VIH. 45. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 46. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 47. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 48. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document Number: 38-06043 Rev. *I Page 19 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 14. Pipelined Read with Address Counter Advance[49] tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx-1 tCD2 Qx READ EXTERNAL ADDRESS Qn tDC Qn+1 READ WITH COUNTER Qn+2 COUNTER HOLD Qn+3 READ WITH COUNTER Figure 15. Flow-through Read with Address Counter Advance[49] tCH1 tCYC1 tCL1 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN tCD1 Qx Qn Qn+1 tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn+3 Qn+2 COUNTER HOLD READ WITH COUNTER Note 49. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. Document Number: 38-06043 Rev. *I Page 20 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 16. Write with Address Counter Advance (Flow-through or Pipelined Outputs)[50, 51] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 Dn+4 WRITE WITH COUNTER Notes 50. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 51. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH. Document Number: 38-06043 Rev. *I Page 21 of 28 CY7C09099V CY7C09179V Switching Waveforms (continued) Figure 17. Counter Reset (Pipelined Outputs)[52, 53, 54, 55] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS AX 0 tSW tHW tSD tHD 1 An+1 An An+1 R/W tSAD tHAD tSCN tHCN tSRST tHRST ADS CNTEN CNTRST DATAIN D0 DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 Q1 Qn READ ADDRESS n Notes 52. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only. 53. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 54. CE0 = VIL; CE1 = VIH. 55. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document Number: 38-06043 Rev. *I Page 22 of 28 CY7C09099V CY7C09179V Read/Write and Enable Operation [56, 57, 58] Inputs OE CE0 CE1 R/W X H X X High Z Deselected[59] X X L X High Z Deselected[59] X L H L DIN Write L L H H DOUT Read[59] L H X High Z Outputs Disabled H CLK Outputs X I/O0–I/O9 Operation Address Counter Control Operation [56, 60, 61, 62] Address Previous Address X CLK ADS CNTEN X X X An X L X An X An CNTRST I/O Mode Operation L Dout(0) Reset Counter Reset to Address 0 X H Dout(n) Load Address Load into Counter H H H Dout(n) Hold External Address Blocked—Counter Disabled H L H Dout(n+1) Increment Counter Enabled—Internal Address Generation Notes 56. “X” = “Don’t Care”, “H” = VIH, “L” = VIL. 57. ADS, CNTEN, CNTRST = “Don’t Care.” 58. OE is an asynchronous input signal. 59. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 60. CE0 and OE = VIL; CE1 and R/W = VIH. 61. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 62. Counter operation is independent of CE0 and CE1. Document Number: 38-06043 Rev. *I Page 23 of 28 CY7C09099V CY7C09179V Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. 128 K × 8 3.3 V Synchronous Dual-Port SRAM Speed (ns) [63] 7.5 12 Ordering Code Package Name Package Type Operating Range CY7C09099V-7AXI A100 100-pin Thin Quad Flat Pack (Pb-free) Industrial CY7C09099V-12AXC A100 100-pin Thin Quad Flat Pack (Pb-free) Commercial 32 K × 9 3.3 V Synchronous Dual-Port SRAM Speed (ns) 12 Ordering Code Package Name CY7C09179V-12AXC A100 Package Type 100-pin Thin Quad Flat Pack (Pb-free) Operating Range Commercial Ordering Code Definitions CY 7C 09 X X9 V - XX A X X Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: A = 100-pin TQFP Speed Grade: 12 ns or 7.5 ns V = 3.3 V X9 = Depth: X = 7 or 9 7 = 32K; 9 = 128K X = Width: X = 0 or 1 0 = × 8; 1 = × 9 09 = Sync 7C = Dual Port SRAM Company ID: CY = Cypress Device Note 63. See page 9 and page 10 for Load Conditions. Document Number: 38-06043 Rev. *I Page 24 of 28 CY7C09099V CY7C09179V Package Diagram Figure 18. 100-pin TQFP 14 × 14 × 1.4 mm A100SA, 51-85048 51-85048 *I Document Number: 38-06043 Rev. *I Page 25 of 28 CY7C09099V CY7C09179V Acronyms Document Conventions Acronym Description Units of Measure CMOS complementary metal oxide semiconductor I/O input/output °C degree Celsius Symbol Unit of Measure OE output enable MHz megahertz SRAM static random access memory µA microamperes TQFP thin quad flat pack mA milliamperes TTL transistor-transistor logic mm millimeter WE write enable ms milliseconds mV millivolts Document Number: 38-06043 Rev. *I ns nanoseconds ohm % percent pF picofarads V volts W watts Page 26 of 28 CY7C09099V CY7C09179V Document History Page Document Title: CY7C09099V, CY7C09179V, 3.3 V 32K/128K × 8/9 Synchronous Dual-Port Static RAM Document Number: 38-06043 Rev. ECN No. Orig. of Change Orig. of Change Description of Change ** 110191 SZV 09/29/01 Change from Spec number: 38-00667 to 38-06043 *A 122293 RBI 12/27/02 Power up requirements added to Operating Conditions Information *B 365034 PCN See ECN Added Pb-Free Logo Added Pb-Free Part Ordering Information: CY7C09089V-6AXC, CY7C09089V-12AXC, CY7C09099V-6AXC, CY7C09099V-7AI, CY7C09099V-7AXI, CY7C09099V-12AXC, CY7C09179V-6AXC, CY7C09179V-12AXC, CY7C09189V-6AXC, CY7C09189V-12AXC, CY7C09199V-6AXC, CY7C09199V-7AXC, CY7C09199V-9AXC, CY7C09199V-9AXI, CY7C09199V-12AXC *C 2623658 VKN/PYRS 12/17/08 Added CY7C09089V-12AXI part in the Ordering information table *D 2897159 RAME 03/22/10 Removed inactive parts from ordering information table. Updated package diagram. Added Note in ordering information section. *E 3110406 ADMU 12/14/2010 Updated Ordering Information. Added Ordering Code Definitions. *F 3264673 ADMU 05/24/2011 Updated Document Title to read “CY7C09099V, CY7C09179V, 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM”. Updated Features. Updated Pin Configurations (Removed the Note “This pin is NC for CY7C09079V.” in page 5). Updated Selection Guide. Updated Package Diagram. Added Acronyms and Units of Measure. Updated in new template. *G 3849285 ADMU 12/21/2012 Updated Ordering Information (Updated part numbers). Updated Package Diagram: spec 51-85048 – Changed revision from *E to *G. *H 4411062 ADMU 06/17/2014 Information for MPNs CY7C09089V and CY7C09199V removed. Information for -6 and -9 speed bins also removed. Updated document title to “CY7C09099V, CY7C09179V, 3.3 V 32K/128K × 8/9 Synchronous Dual-Port Static RAM” *I 4580622 ADMU 11/26/2014 Added related documentation hyperlink in page 1. Document Number: 38-06043 Rev. *I Page 27 of 28 CY7C09099V CY7C09179V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06043 Rev. *I Revised November 26, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 28 of 28