ATMEL ATA6809

Features
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Digital Self-supervising Watchdog with Hysteresis
Three 250-mA Output Drivers
One Relay Driver, Two Lamp Drivers
Lamp Drivers With Auxiliary Ground
Short-circuit-protected Lamp Drivers
Lamp Drivers With Status Feedback
Enable Output
Overvoltage/Undervoltage Detection and Reset
All Power Outputs Protected Against Standard Transients
All Power Outputs Protected Against 40V Load Dump
Lamp Drivers Automatically Activated if VS is Disconnected
Lamp Drivers Automatically Activated Via AUX GND if Standard
Ground is Disconnected
1. Description
Fail-safe IC with
Relay Driver
and Lamp
Driver
ATA6809
The ATA6809 is designed to support the fail-safe function of safety-critical systems
such as ABS. It includes a relay driver, two independent short-circuit-protected lamp
drivers which are supplied by redundant ground lines, two monitoring circuits for the
lamp driver output voltage and output current, a watchdog controlled by an external
RC network, and a reset circuit initiated by an overvoltage or undervoltage condition
of the 5V supply providing a positive and a negative reset signal.
Rev. 4902A–AUTO–11/05
Figure 1-1.
Block Diagram
VS
LA1I
LA2I
RELI
WDI
Microcontroller
FBLA1
FBLA2
PRES
NRES
Digital input lamp 1
Open-collector
250 mA
lamp driver 1
Logic
Digital input lamp 2
Short-circuit
detection and
temperature
monitor
Digital input relay
LA1O
Temperature
Digital input wd
Watchdog
Open-collector
250 mA
lamp driver 2
Debouncing of
over- and undervoltage detection
Open-collector
250 mA
relay driver
Oscillator
monitoring
RC-oscillator
Open-collector
25 mA
enable driver
LA2O
Loads
Feedback lamp 1
Feedback lamp 2
p reset
n reset
OSC
GND
RELO
ENO
AUX GND
2. Pin Configuration
Figure 2-1.
2
Pinning SO20
REL1
1
20
LA1I
2
19 VS
LA2I
3
18 LA1O
RELO
4
17 GND
GND
5
16 GND
GND
6
FBLA1
7
14 LA2O
NRES
8
13 AUX
GND
PRES
9
12 ENO
FBLA2
10
11 OSC
ATA6809
WDI
15 GND
ATA6809
4902A–AUTO–11/05
ATA6809
Table 2-1.
Pin Description
Pin
Name
Type
Function
Logic
1
RELI
Digital input
Activation of relay driver
Driver on: L
Driver off: H
2
LA1I
Digital input
Activation of lamp driver 1
Driver off: L
Driver on: H
3
LA2I
Digital input
Activation of lamp driver 2
Driver off: L
Driver on: H
4
RELO
Open-collector driver output
Fail-safe relay driver
Driver off:--Driver on: L
5, 6
GND
Supply
Standard ground
7
FBLA1
Digital output
Feedback lamp 1
See Table 3-1 on page 5 and
Table 3-2 on page 5
8
NRES
Digital output
Negative reset signal
Reset: L
No reset: H
9
PRES
Digital output
Positive reset signal
Reset: H
No reset: L
10
FBLA2
Digital output
Feedback lamp 2
See Table 3-1 on page 5 and
Table 3-2 on page 5
11
OSC
Analog input
External RC for watchdog timer
12
ENO
Open-collector output
Watchdog disable output
13
AUX, GND
Supply
Auxiliary ground of lamp drivers
14
LA2O
Open-collector driver output
Warning lamp driver
15, 16, 17
GND
Supply
Standard ground
18
LA1O
Open-collector driver output
Warning lamp driver
19
VS
Supply
5V supply
20
WDI
Digital input
Watchdog trigger signal
Watchdog ok: --Watchdog not ok: L
Driver off: --Driver on: L
Driver off: --Driver on: L
Pulse sequence
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4902A–AUTO–11/05
3. Detailed Block Diagram with External Components
Figure 3-1.
Detailed Block Diagram
VS
Push pull
R+
Reset
debouncing
19
V Ref 4
+
-
Push pull
R-
Reset
delay
8
Temperature
shut down
1
RELO
Push pull
L1
+
-
7
VS
+
-
V Ref2
+
-
18
LA1O
V Ref 1
Failure
detection
lamp 2
+
C
B
14
LA2O
D
V Ref3
Ground backup
GND
AUX GND
+
-
E
Oscillator
OSC
D
Integrated
oscillator
Internal
timing
C
Push pull
L2
5 6 15 16 17
GND
E
10
FBLA2
Short-circuit
protection
B
4
E
D
A
11
V Batt
V Ref2
+
-
Watchdog
VS
VS
+
-
+
Debouncing
WDI
V Ref3
3
20
FBLA1
V Batt
Debouncing
Failure
detection
lamp 1
2
C
LA2I
- NRES
4
A
V Ref 5
LA1I
+ PRES
V Batt
+
-
RELI
9
12
ENO
13
AUX GND
ATA6809
4902A–AUTO–11/05
ATA6809
Table 3-1.
Truth Table for Lamp Drivers and Lamp Feedback
Inputs
Outputs
Lamp (I)
Lamp
Voltage
Lamp
Current
Lamp
Driver
Current
Lamp
Current
Feedback
Lamp
0
1
0
Off
Off
1
Output ok or open (internal pull-up) or shorted to
VBatt
0
1
1
On
Off
1
Output shorted to VBatt and faulty input level
0
0
1
On
On
0
Internal driver activated due to internal failure
0
0
0
Off
On
0
Output shorted to GND
1
0
1
On
On
0
Output ok
1
1
1
On
Off
1
Output shorted to VBatt
1
1
0
Off
Off
1
Internal driver deactivated due to internal failure or
thermal shutdown
0
0
Off
On/off
1
Output shorted to GND or open
1
Note:
Comment
Lamp voltage is logic 1 if output voltage > threshold voltage detection
Lamp voltage is logic 0 if output voltage < threshold voltage detection
Lamp current is logic 1 if output current > threshold current detection
Lamp current is logic 0 if output current < threshold current detection
Table 3-2.
Table of Fault Detection
Feedback Lamp
Condition
Lamp Input is 0 (Lamp Off)
Lamp Input is 1 (Lamp On)
Normal operation
1
0
Lamp output shorted to GND
0 (= detection)
1 (= detection)
Lamp output shorted to VBatt
1 (= no detection)
1 (= detection)
Lamp output open
1 (= no detection)
1 (= detection)
Feedback shorted to GND
0 (= detection)
0 (= no detection)
Feedback shorted to VS
1 (= no detection)
1 (= detection)
Lamp input shorted to GND
1 (= no detection)
1 (= detection)
Lamp input shorted to VS
0 (= detection)
0 (= no detection)
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4902A–AUTO–11/05
4. Fail-safe Functions
A fail-safe IC has to maintain its monitoring function even if there is a fault condition at one of the
pins (for example, a short circuit). This ensures that a microcontroller system is not brought into
a critical status. A critical status is reached if the system is not able to actuate a warning lamp
and switch off the relay. The following table shows fault conditions for different pins during which
the IC still works as a fail-safe device.
Table 4-1.
Table of Fault Condition
Pin
Function
Short to VS
Short to VBatt
Short to GND
Open Circuit
LA2O
Short-circuit proof driver for warning lamp
LA2O partly on
LA2O off
LA2O on
LA2O off
LA2I
Digital input to activate warning lamp
LA2O on
LA2O on
LA2O off
LA2O on
FBLA2 Digital feedback of warning lamp
Faulty feedback
Faulty feedback
Faulty feedback
Faulty feedback
LA1O
Short-circuit proof driver for warning lamp
LA1O partly on
LA1O off
LA1O on
LA1O off
LA1I
Digital input to activate warning lamp
LA1O on
LA1O on
LA1O off
LA1O on
FBLA1 Digital feedback of warning lamp
Faulty feedback
Faulty feedback
Faulty feedback
Faulty feedback
RELI
Digital input to activate the fail safe relay
Relay off
Relay off
Relay on
Relay off
WDI
Watchdog trigger input
Watchdog reset
Watchdog reset
Watchdog reset
Watchdog reset
OSC
Capacitor and resistor of watchdog
Watchdog reset
Watchdog reset
Watchdog reset
Watchdog reset
5. Description of the Watchdog
5.1
Abstract
The microcontroller is monitored by a digital window watchdog which accepts an incoming trigger signal of a constant frequency for correct operation. The frequency of the trigger signal can
be varied in a broad range as the watchdog's time window is determined by external RC
components.
The following description refers to Figure 1-1 on page 2.
Figure 5-1.
Watchdog Block Diagram
Binary counter
RCOSC
Dual MUX
WDI
Slope
detector
Up/down
counter
RS-FF
WD-OK
RESET
OSCERR
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ATA6809
4902A–AUTO–11/05
ATA6809
5.2
WDI Input (Pin 20)
The microcontroller has to provide a trigger signal with the frequency fWDI, which is fed to the
WDI input. A positive edge of fWDI detected by a slope detector resets the binary counter and
also clocks the up/down counter. The up/down counter only counts from 0 to 3 or reverse. Each
correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As
soon as the counter reaches the count of 3 the RS flip-flop is set (see Figure 5-2). A missing
incoming trigger signal is detected after 250 clocks of the internal watchdog frequency fRC (see
“WD-OK Output” ) and resets the up/down counter directly.
5.3
RCOSC Input
The IC generates a time base (frequency fRC) independent from the microcontroller via external
RC circuitry. The watchdog's time window refers to a frequency of
RC = 100 × fWDI
5.4
Reset Input
During power-on and undervoltage/overvoltage detection, a reset signal is fed to this pin. It
resets the watchdog timer and sets the initial state.
5.5
WD-OK Output
After the up/down counter has reached 3 (see the WD state diagram, Figure 5-2 on page 7), the
RS flip-flop is set and the WD-OK output becomes logic 1. This information is available for the
microcontroller at the open-collector output ENO. If, on the other hand, the up/down counter is
decremented to 0, the RS flip-flop is reset, and the WD-OK output and the ENO output are disabled. The WD-OK output also controls a dual MUX stage which shifts the time window by one
clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the
evaluation of the trigger signal "good” or “bad". The WD-OK signal is also reset if the watchdog
counter is not reset after 250 clocks (missing trigger signal).
5.6
Watchdog State Diagram
Figure 5-2.
Watchdog State Diagram
good
Initial status
2/NF
1/NF
bad
bad
bad
good
good
bad
O/F
3/NF
bad
good
bad
1/F
2/F
good
good
In each block, the number represents the state of the counter. “F” or “NF” indicates the fault status of the counter. Fault status is indicated by "F" and no-fault status is indicated by "NF". When
the watchdog is powered up initially, the counter starts at the 0/F block (initial state). "Good" indicates that a pulse has been received whose width resides within the timing window. "Bad"
indicates that a pulse has been received whose width is either too short or too long.
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4902A–AUTO–11/05
5.7
Watchdog Window Calculation
Example with recommended values
Cosc = 3.3 nF (should preferably be 10%, NPO)
Rosc = 39 kΩ (may be 5%, Rosc < 100 kΩ due to leakage current and humidity)
5.8
RC Oscillator
tWDC (s) = 10–3 × [Cosc (nF) × [(0.00078 × Rosc (kΩ)) + 0.0005]]
fWDC (Hz) = 1 / (tWDC)
5.9
Watchdog WDI
fWDI (Hz) = 0.01 × fWDC
tWDC = 100 µs -> fWDC = 10 kHz
fWDI = 100Hz -> tWDI = 10 ms
5.9.1
WDI Pulse Width for Fault Detection After 3 Pulses
Upper watchdog window
Minimum: 169 / fWDC = 16.9 ms -> fWDC / 169 = 59.1Hz
Maximum: 170 / fWDC = 17.0 ms -> fWDC / 170 = 58.8Hz
Lower watchdog window
Minimum: 79 / fWDC = 7.9 ms -> fWDC / 79 = 126.6Hz
Maximum: 80 / fWDC = 8.0 ms -> fWDC / 80 = 125.0Hz
5.9.2
WDI Dropouts for Immediate Fault Detection
Minimum: 250 / fWDC = 25 ms
Maximum: 251 / fWDC = 25.1 ms
Figure 5-3.
Watchdog Timing Diagram with Tolerances
79 / fWDC
Time/s
80 / fWDC
169 / fWDC
170 / fWDC
250 / fWDC
251 / fWDC
Watchdog
window update
rate is good
Update rate is
too fast
5.9.3
8
Update rate is
either too fast or
good
Update rate is
either too slow
or good
Update rate is
too slow
Update rate is
either too slow
or pulse has
dropped out
Pulse has
dropped out
Remark to Reset Delay
The duration of the overvoltage or undervoltage pulse determines the enable and reset output. A
pulse duration shorter than the debounce time has no effect on the outputs. A pulse longer than
the debounce time results in the first reset delay. If a pulse appears during this delay, a 2nd
delay time is triggered. Therefore, the total reset delay time can be longer than specified in the
datasheet.
ATA6809
4902A–AUTO–11/05
ATA6809
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
Unit
VS
–0.2 to +16
V
AUX GND offset voltage to GND
VAUX
±1.5
V
AUX GND offset current to GND
IAUX
–600
mA
Power dissipation VS = 5V;
Tamb = 125° C
Ptot
700
mW
Thermal resistance
Rthjc
25
K/W
Tj
150
°C
Ambient temperature range
Tamb
–40 to +125
°C
Storage temperature range
Tstg
–55 to +155
°C
Supply voltage range
Junction temperature
7. Electrical Characteristics
VS = 5V, Tamb = –40 to +125°C; reference pin is GND; fintern = 100 kHz + 50% – 45%, fWDC = 10 kHz ±10%; fWDI = 100Hz
Parameters
Test Conditions
Symbol
Min.
Operation range general
VS
Operation range reset
VS
Typ.
Max.
Unit
4.5
5.5
V
1.5
16.0
V
Supply Voltage
Supply Current
Lamp driver on, relay off
Tamb = –40° C
Tamb = 125° C
40
35
mA
mA
Lamp driver off, relay on
Tamb = –40° C
Tamb = 125° C
25
20
mA
mA
Lamp driver off, relay off
Tamb = –40° C
Tamb = 125° C
15
10
mA
mA
Auxiliary Ground (AUX GND)
AUX GND offset voltage operation
range
Tamb = –40° C
Tamb = 90° C
Tamb = 125° C
–1.2
–0.65
–0.5
1.2
1.0
0.8
V
V
V
AUX GND offset voltage to GND
IAUX = –600 mA
–1.7
3.0
V
–0.2
0.2 × VS
V
0.7 × VS
VS +
0.5V
V
10
40
kΩ
Digital Inputs (LA1I, LA2I, REL1 and WDI)
Detection low
Detection high
Resistance to VS
Input current low
Input voltage = 0V
100
550
µA
Input current high
Input voltage = VS
–5
5
µA
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4902A–AUTO–11/05
7. Electrical Characteristics (Continued)
VS = 5V, Tamb = –40 to +125°C; reference pin is GND; fintern = 100 kHz + 50% – 45%, fWDC = 10 kHz ±10%; fWDI = 100Hz
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Digital Outputs; Lamp Driver Feedbacks (FBLA1, FBLA2)
Voltage low
I ≤1.6 mA
0
0.5
V
0.8 × VS
0.7 ×
VS + 0.1
VS
V
Threshold voltage detection
0.4 × VS
0.5 × VS
V
Threshold current detection
10
50
mA
I ≤10A
Voltage high
10A ≤I ≤1.6 mA
Digital Outputs (PRES and NRES)
Voltage high
I ≤100A
0.7 ×
VS + 0.1
VS
V
Voltage low
I ≤1 mA
0
0.3
V
0
0.3
V
Clamping voltage
26
30
Current limit low
25
Digital Output (ENO) with Open Collector
Saturation voltage low
Leakage current
I ≤25 mA
VENO = 5V
VENO = 16V
VENO = 26V
V
mA
20
100
200
µA
µA
µA
Lamp Drivers (LA1O and LA2O) with Integrated Pull-up Resistor
Saturation voltage
I ≤125 mA; VS = 5V
I ≤125 mA; VS = 0V
0.5
1.5
V
V
Saturation voltage
250 mA requires enhanced heat sink
I ≤250 mA; VS = 5V
I ≤250 mA; VS = 0V
I ≤250 mA; no GND
1.0
2.0
3.0
V
V
V
Maximum load current
Tamb = 90° C
Tamb = 125° C
Clamping voltage
Leakage current
250
180
26
30
V
1
3
mA
mA
0.5
1.0
A
2
17
kΩ
VLA1O, LA2O = 16V
VLA1O, LA2O = 26V
Threshold current limitation
Pull-up resistor
mA
mA
Relay Driver (RELO)
Saturation voltage
I ≤250 mA
Maximum load current
Tamb = 90° C
Tamb = 125° C
Clamping voltage
Leakage current
10
0.5
250
200
26
VBatt = 16V
VBatt = 26V
V
mA
mA
30
V
20
200
µA
µA
ATA6809
4902A–AUTO–11/05
ATA6809
7. Electrical Characteristics (Continued)
VS = 5V, Tamb = –40 to +125°C; reference pin is GND; fintern = 100 kHz + 50% – 45%, fWDC = 10 kHz ±10%; fWDI = 100Hz
Parameters
Test Conditions
Symbol
Min.
Lower reset level
VS
Upper reset level
VS
Typ.
Max.
Unit
4.5
4.8
V
5.2
5.5
V
Reset and VS Control
Hysteresis
25
mV
Reset debounce time
120
500
µs
Reset delay
20
80
ms
12.8
ms
Watchdog Timing
Feedback reaction time
(FBLA1, FBLA2)
No fault, edge at LA1I, LA2I
tFB
2.56
Minimum lamp input toggle time for a
secure feedback reaction
No fault, pulse at LA1I, LA2I
tP,FB
10.24
tPOR
34.3
103.1
ms
Power-on-reset prolongation time
tRCerror
81.9
246
ms
Time interval for overvoltage/
undervoltage detection
tD,OUV
0.16
0.64
ms
Reaction time of NRES output on
overvoltage/undervoltage
tR,OUV
0.187
0.72
ms
Minimum toggle time for a secure
broken ground detection
tP,BGND
13.3
Maximum reaction time for broken
ground detection
tR,BGND
Detection time for RC-oscillator fault
VRC = constant
ms
µs
100
µs
Nominal frequency for WDI
fRC = 100 × fWDI
fWDI
10
130
Hz
Nominal frequency for RC
fWDI = 1 / 100 × fRC
fRC
1
13
kHz
Minimum pulse duration for a secure
WDI input pulse detection
tP,WDI
182
Frequency range for a correct
WDI signal
fWDI
64.7
Number of incorrect WDI trigger
counts for locking the outputs
nlock
3
nrelease
3
Number of correct WDI trigger counts
for releasing the outputs
Detection time for a stuck
WDI signal
VWDI = constant
tWDIerror
µs
24.5
112.5
Hz
25.5
ms
Watchdog Timing Relative to fRC
Minimum pulse duration for a securely
WDI input pulse detection
2
Frequency range for a correct
WDI signal
80
Hysteresis range at the
WDI ok margins
Detection time for a stuck
WDI signal
cycles
170
1
VWDI = constant
250
cycles
cycle
251
cycles
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4902A–AUTO–11/05
Table 7-1.
Protection Against Transient Voltages According to ISO TR 7637-3 Level 4 (Except Pulse 5)
Voltage
Source Resistance(1)
Rise Time
1
–110V
10Ω
100V/s
2 ms
15.000
2
+110V
10Ω
100V/s
0.05 ms
15.000
3a
–160V
50Ω
30V/ns
0.1s
1h
3b
+150V
50Ω
20V/ns
0.1s
1h
5
40V
2Ω
10V/ms
250 ms
20
Pulse
Note:
1. Lamp drivers: 1.2Ω lamps need to be added to the source resistance.
Relay driver: relay coil with Rmin = 70Ω need to be added to the source resistance.
7.1
Application Hints
Duration
Amount
a.)
The lamp output pins LA1O and LA2O may need to be protected by external
protection diodes (for example, BAV 202) against reversed battery, in order
to avoid a reset during negative pulses.
b.)
If pilot lamps with a wattage of P > 1.2W are connected, external Zener diodes
are mandatory.
8. Timing Diagrams
Figure 8-1.
Watchdog in Too Fast Condition
Normal operation
WDI too fast
Normal operation
5V
WDI
0V
VBatt
RELO
0V
5V
ENO
0V
VBatt
LAXO
0V
Don't care
12
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4902A–AUTO–11/05
ATA6809
Figure 8-2.
Watchdog in Too Slow Condition
Normal operation
WDI too low
Normal operation
5V
WDI
0V
VBatt
RELO
0V
5V
ENO
0V
VBatt
LAXO
0V
Don't care
Figure 8-3.
Overvoltage Condition
Overvoltage condition
> 120 µs
< 120 µs
≥ 5.5 V
5V
≥ 5.5 V
VS
0V
V Batt
RELO
0V
5V
ENO
0V
5V
NRES
0V
V Batt
LAXO
0V
Reset debounce time
3 good WDI pulses
Don't care
1st Reset delay
2nd Reset delay
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4902A–AUTO–11/05
Figure 8-4.
Undervoltage Condition
Undervoltage condition
> 120 µs
5V
≤ 4.5 V
VS
< 120 µs
≤ 4.5 V
0V
V Batt
RELO
0V
5V
ENO
0V
5V
NRES
0V
V Batt
LAXO
0V
Reset debounce time
3 good WDI pulses
Don't care
1st Reset delay
2nd Reset delay
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4902A–AUTO–11/05
ATA6809
9. Ordering Information
Extended Type Number
Package
ATA6809-TGQY
Remarks
SO20 special lead frame
Taped and reeled, Pb-free
10. Package Information
9.15
8.65
Package SO20
Dimensions in mm
12.95
12.70
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
11.43
20
11
technical drawings
according to DIN
specifications
1
10
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4902A–AUTO–11/05
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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Japan
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Atmel Operations
Memory
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Microcontrollers
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