Features • • • • • • • Watchdog Adjustable Over- and Undervoltage Detection of Vcc = 5V Standby Modes On/Off via Ignition Pin VKL15 Internal Time Delay for Output Signal Push-pull Output Driver Interference and Damage Protection According to ISO/CD 7637 ESD Protection Watchdog IC ATA6025 1. Description The ATA6025 is a monolithic circuit based on Atmel’s smart power BCD60-III technology. It is a universal IC for monitoring basic functions of an automotive application. It is possible to monitor the battery voltage (VKL15) and an external 5V voltage regulator. With the independent watchdog the correct function of a microcontroller can be observed. If a failure occurs, the output NOTL switches to high after a time delay. During standby mode the current consumption is reduced to a minimum. Figure 1-1. Block Diagram RREF VB VBG oscillator on chip trimming VCC standby mode Short circuit 2.5 mA protected BIAS current VDD 5V regulator OSC VCCH VCC over- & undervoltage detection POR & Bandgap Reference VBG IBias VB monitoring up &down counter 400ms VCCL NOTL POR VBOK NL High at counter end NL Low at counter zero VDD POR VKL15 failure watchdog fwd VDD NVKL15 standby mode Watchdog WD OSC Input Test mode 1 or 2 High at counter zero CLK OSC divided by 4 GND Rev. 4716C–AUTO–09/05 2. Pin Configuration Figure 2-1. Pinning SO8 NOTL VB GND RREF Table 2-1. 2 1 2 3 4 8 7 6 5 VCC CLK WD VKL15 Pin Description Pin Symbol 1 NOTL Function Push-pull output driver 2 VB 3 GND Voltage supply Ground 4 RREF Reference voltage to adjust oscillator frequency via resistor Rset 5 VKL15 Input for standby modes on/of via ignition KL15 6 WD Input for watchdog signal from microcontroller 7 CLK Clock output signal, open drain 8 VCC Input for monitoring 5V power supply ATA6025 4716C–AUTO–09/05 ATA6025 3. Functional Description 3.1 Voltage Supply The IC can be supplied directly from Vbattery. If the voltage at the VB pin is lower than the threshold of VVBlo = 5.76 V, the internal signal VBOK is set to low. If VBOK is low, the monitor function of the IC is completely disabled and the output NOTL is switched off in all cases (see Figure 8-3 on page 10). If the voltage at pin VKL15 is low, the IC is in standby mode and reduces the current consumption at pin VB < 100 µA. 3.2 Oscillator The frequency fCLK of the internal oscillator is defined by the external resistor RSET and the internal capacitor. Thus, it is possible to vary the oscillator frequency between 4 kHz and 24 kHz. 3.3 VKL15 Monitoring This input is used to monitor the battery voltage at ignition pin VKL15. If the voltage VKL15lo < 1.8V, the internal signal NVKL15 is set to high (see Figure 8-3 on page 10). The IC switches to standby mode. During standby mode the monitor function is disabled and the output NOTL is switched off after the time delay tDelay. If the output NOTL is switched on and the voltage at VKL15 switches suddenly to low, the internal timer starts and switches the NOTL off after a time delay of tDelay = 400 ms. 3.4 VCC Over-/Undervoltage Via the VCC input an external 5V voltage regulator is continuously monitored. If the voltage at pin VCC exceeds the voltage of VCChon > 6.3V, the failure bit VCCH is set high. If the voltage at pin VCC decreases to a value below VCClon < 4V, the internal failure bit VCCL will be set to high (see Figure 8-1 on page 9). This failure bit starts the internal counter and switches the output NOTL on after the time delay of typically tDelay= 400 ms. If the VCC voltage is inside the tolerance VCCloff < VVCC < VCChoff the failure signal will be reset and the internal counter counts back to zero. After a time delay of typically tDelay = 400 ms, the output NOTL is switched off again. 3.5 Watchdog A microcontroller can be monitored by a digital window watchdog which accepts an incoming trigger signal TWD of a constant frequency at pin WD for correct operation. If the pulse width TWD between two alternate edges exceeds the time window of ToWD > 8.9 ms or if there is no watchdog signal, the failure signal fwd (failure watchdog) is set. In case the pulse width TWD between two alternate edges falls below the time window of TuWD < 2.6 ms, the failure signal fwd (failure watchdog) is also set. With this fwd signal the internal up counter is activated and after a time delay of tDelay = 400 ms, the output NOTL is switched to high. If NOTL is high, 16 successive correct watchdog signals T WD within the pulse width of TuWD < TWD < ToWD are needed to create the internal signal nfwd (no failure watchdog) to start the down counter. After a time delay of tDelay= 400 ms, the output NOTL is switched to low (see Figure 8-2 on page 9). 3 4716C–AUTO–09/05 3.6 Time Delay The internal time delay is generated by an up/down counter. The clock for the counter is disabled if the voltage at the supply pin VB < 5.76V. In this case, the internal signal VBOK will be set to low and the output NOTL is directly switched to low. The direction of counting is set by the watchdog or VCC over- and undervoltage detection. If the VCC monitoring detects an undervoltage condition, the failure signal VCCL (VCC low voltage) is set and starts the up counter. If the VCC monitoring detects an overvoltage condition, the failure signal VCCH (VCC high voltage) is set and starts the up counter. A failure at the watchdog sets the internal fwd signal (failure watchdog) to high and starts the up counter. If the counter’s final value is reached, a Flip Flop is set and switches the output NOTL to high. If no failure signal is set and the window watchdog has counted successive 16 alternate WDI edges then the down counter is started. If the counter reaches the zero value the Flip Flop receives a reset command and switches the output NOTL off. The down counter is also started if the voltage at input VKL15 is low and switches the output NOTL after tDelay = 400 ms to low (see Figure 8-3 on page 10). 3.7 Output NOTL If the voltage at VKL15 is high and if a failure signal is set, the output NOTL switches to high after the internal time delay. The output is short circuit protected with a current limitation of ISCNOTL = 15 mA. The maximum output voltage is limited to VCNOTL = 22V (see Figure 8-4 on page 10). 3.8 Test Mode The pin CLK is normally open or connected to GND. If the internal clock frequency is to be checked, the CLK pin has to be connected with an external resistor Rex = 5 kΩ to a 5V supply. The measured value is the clock frequency divided by four. 4 ATA6025 4716C–AUTO–09/05 ATA6025 4. Truth Table VVB VVB < 5.76V VVCC WDI Do not care Do not care VVCC < 4V Do not care Do not care 7.26V < VVB < 17.5V 4.8V < VVCC < 5.2V Low Standby, NOTL low High NOTL low Low Standby, NOTL low High NOTL high Low Standby, NOTL low High NOTL low Watchdog failure High NOTL high Low Standby, NOTL low High NOTL high Do not care VVCC > 6.3V Low Standby, NOTL low High NOTL high (maximum 22 V) Do not care Low Standby, NOTL low No watchdog failure High NOTL low Watchdog failure High NOTL high (maximum 22 V) Low Standby, NOTL low High NOTL high VVCC < 4V 4.8V < VVCC < 5.2V Mode No watchdog failure VVCC > 6.3V 22V< VVB < 40V VKL15 Do not care VVCC > 6.3V VVCC > 6.3V Do not care 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit VVB –0.3 +40 V Voltage at pins VCC, WD VVCC, VWDI –0.3 +30 V Voltage at pins RREF, CLK Supply voltage VRREF, VCLK –0.5 +6 V Voltage at pin NOTL VNOTL –0.3 +22 V Voltage at pin KL15 (in series with external resistor of 50 kΩ 1%) VKL15 –0.1 +40 V Maximum current at pin VCC IVCC –100 +0.1 mA Maximum current at pin VB IVB –10 +10 mA –100 +100 mA IWD –1 +1 mA ESD classification HBM ESD S.5.1 all pins 2000 V ESD classification MM JEDEC A115A all pins 200 V Maximum current in pins CLK, RREF, VKL15, NOTL Maximum current at pin WD 300 mW –40 +150 °C Tamb –40 +125 °C TStg –55 +150 °C Power dissipation PV Chip temperature TJ Operating ambient temperature Storage temperature 5 4716C–AUTO–09/05 6. Thermal Resistance Parameters Symbol Value Unit RthJA 160 K/W Thermal resistance from junction to ambient 7. Electrical Characteristics VVB = 7.2V to 17.5V, RKL15 = 50 kΩ 1%, RSET = 22 kΩ 1%, Tamb = –40 to 125°C, unless otherwise specified No. Pin Symbol Max. Unit Type* 0.1 VVKL15 > 4.5V Current consumption in VVB =17.5V NOTL = high normal mode INOTL = –2.5 mA 2 IVB 10 mA A 0.2 Standby: Current consumption in VVKL15 < 1.8V VVB = 17.5V standby mode NOTL = low 2 IVBstby 100 µA A 0.3 Negative ESD clamping to GND, IVB = –10 mA pin VB 2 VNVB –1.4 –0.3 V A 0.4 Positive ESD clamping pin RREF to GND, IRREF = 5 mA 4 VPRREF 4 8 V A 0.5 Positive ESD clamping pin CLK to GND, ICLK = 20 mA 7 VPCLK 6 10 V A 0.6 Positive ESD clamping pin VB to GND, IVB = 5 mA 2 VPVB 41 65 V A 0.7 Positive ESD clamping pin VKL15 to GND, IVKL15 = 1.6 mA 5 VPVKL15 41 65 V A 0.8 Positive ESD clamping pin NOTL to GND, INOTL = 20 mA 1 VPNOTL 31 55 V A 0.9 Positive ESD clamping pin WD to GND, IWD = 0.7 mA 6 VPWD 35 55 V A 0.10 Positive ESD clamping pin VCC to GND, IVCC = 0.5 mA 8 VPVCC 35 55 V A 0 1 Parameters Test Conditions Min. Typ. Current Consumption and ESD Clamping Reference Voltage 1.1 Voltage at RREF 4 VRREF 1.14 1.22 1.3 V A 1.2 Possible values of resistor RREF 4 RRREF 10 22 50 kΩ A 10 11 kHz A 2 Oscillator 2.1 Oscillator frequency RSET = 22 kW ±1% at pin CLK with pull-up-resistor to +5 V 7 fCLK 9 2.2 Oscillator frequency is variable in a range RSE = 10 kΩ to 50 kΩ ±1% 7 fCLK 3.96 24.2 kHz A 4 VB Monitoring 4.1 High level threshold 2 VVBhi 5.94 7.26 V A 4.2 Low level threshold 2 VVBlo 5.76 7.04 V A 4.3 Hysteresis 2 VVBhys 0.2 V A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 6 ATA6025 4716C–AUTO–09/05 ATA6025 7. Electrical Characteristics (Continued) VVB = 7.2V to 17.5V, RKL15 = 50 kΩ 1%, RSET = 22 kΩ 1%, Tamb = –40 to 125°C, unless otherwise specified No. 5 5.1 Parameters Test Conditions Pin Symbol Min. 5 RiKL15 18 1.8 Typ. Max. Unit Type* 70 kΩ A V A 4.5 V A VKL15 Monitoring Input resistor at VKL15 5.2 Low voltage threshold RKL15 = 50 kΩ ±1% 5 VKL15lo 5.3 High voltage threshold RKL15 = 50 kΩ ±1% 5 VKL15hi 5.4 Hysteresis 5 VKL15hys 0.2 1 V A 8 RpdVCC 50 350 kΩ A 4 V A 6 VCC Monitoring VVB = 17.5V VVKL15 = 0V or VVKL15 = VVB VVCC = 5V 6.1 Pull-down resistor to GND at pin VCC 6.2 Undervoltage detection low level 8 VCCIon 6.3 Undervoltage detection high level 8 VCCIoff 4.8 V A 6.4 Overvoltage detection high level 8 VCCIoff 6.3 V A 6.5 Overvoltage detection low level 8 VCChoff 5.2 V A 6.6 Hysteresis of underand overvoltage detection 8 VCChys 0.2 V A 6 15 kΩ A 9 Oscillator Test 9.1 Pull-down-resistor CLK = high, VCLK = 0V to 4.5V 7 RpdCLK 9.2 Saturation voltage ICLK = 1.6 mA, CLK = low 7 VsCLK 0.4 V A 9.3 Short current VCLK = 5V, CLK = low 7 IscCLK 10 mA A 10 Push-pull Output NOTL 10.1 Saturation voltage NOTL switched off INOTL = 1.8 mA NOTL off 1 VsatNOTLoff 1 V A 10.2 Short current NOTL if switched off VNOTL = VVB NOTL off 1 IscNOTLoff 15 mA A 10.3 Maximum output voltage NOTL 17.5V < VVB < 30V INOTL = –2.5 mA NOTL on 1 VNOTLmax 22 V A 10.4 Saturation voltage NOTL switched on; guaranteed down to VB low level threshold VsatNOTLon = VVB – VNOTL VVKL15 = VVB INOTL = –2.5 mA NOTL on 1 VsatNOTLon 0.25 V A 10.5 Short current NOTL if switched off VNOTL = 0 V NOTL = on 1 IscNOTLon –50 mA A 10.7 Time delay of internal up and down counter 1 tDelay 360 ms A 17.5 400 450 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7 4716C–AUTO–09/05 7. Electrical Characteristics (Continued) VVB = 7.2V to 17.5V, RKL15 = 50 kΩ 1%, RSET = 22 kΩ 1%, Tamb = –40 to 125°C, unless otherwise specified No. Parameters Test Conditions 10.8 Rise time at pin NOTL switch on 10.9 Fall time at pin NOTL switch off 11 Pin Symbol CNOTL ≤ 200 pF VNOTL from low = 10% to high = 90% VVB 1 CNOTL ≤ 200 pF VNOTL from high = 90% to low = 10% V(VB) VVB = VKL15 = 17.5V Min. Typ. Max. Unit Type* trNOTL 5 µs A 1 tfNOTL 5 µs A 6 RpdWD 30 200 kΩ A 6 VlowWD 1 V A V A V A Watchdog 11.1 Pull-down-resistor 11.2 Voltage threshold low 11.3 Voltage threshold high 3.5 6 VhighWD 6 VhysWD 0.5 11.4 Hysteresis VhysWD = VhighWD – VlowWD 11.5 Acceptable low WD pulse width for failure Pulse = high or low RSET = 22 kΩ ±1% 6 TuWD 2.6 3 3.3 ms A 11.6 Acceptable high WD pulse width for failure Pulse = high or low RSET = 22 kΩ ±1% 6 ToWD 7.1 8 8.9 ms A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 8 ATA6025 4716C–AUTO–09/05 ATA6025 8. Diagrams Figure 8-1. VCC Monitoring Diagram V(VCC) VCChon VCChoff VCCloff VCClon t low high VCCH VCCL Figure 8-2. Watchdog Timing Diagram no WD or TWD >ToWD TuWD < TWD < ToWD 0 TWD <TuWD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WD fwd nfwd down up NOTL tDelay tDelay 9 4716C–AUTO–09/05 Figure 8-3. Time Delay Diagram VBOK NVKL15 high low VCCH VCCL fwd NOTL tDelay tDelay Figure 8-4. tDelay tDelay tDelay tDelay Push-pull Output NOTL V(NOTL) 22 V VNOTLmax VBlo 10 VBhi 17.5 to 22 V V(VB) ATA6025 4716C–AUTO–09/05 ATA6025 Figure 8-5. Application Circuit Rset CVB2 100 nF KL30 CVB1 DKL30 220 µF BYG10J VB RREF VBG oscillator on chip trimming VCC standby mode Short circuit 2.5 mA protected BIAS current VDD 5 V regulator OSC VCCH VCC over- & undervoltage detection POR & Bandgap Reference VBG IBias VB monitoring up & down counter 400 ms VCCL NOTL POR VBOK NL High at counter end NL Low at counter zero VDD POR VKL15 RKL15 50k CKL15 100 nF failure watchdog fwd VDD NVKL15 standby mode Watchdog WD OSC Input Test mode 1 or 2 High at counter zero CLK OSC divided by 4 GND 11 4716C–AUTO–09/05 9. Ordering Information Extended Type Number Package ATA6025-TAQY Remarks SO8 Taped and reeled, Pb-free 10. Package Information Package SO8 Dimensions in mm 5.2 4.8 5.00 4.85 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 3.81 8 0.2 3.8 5 technical drawings according to DIN specifications 1 4 11. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 12 Revision No. History 4716C-AUTO-09/05 • • • • Put datasheet in a new template Pb-free logo on page 1 added Heading rows on Table “Absolute Maximum Ratings” on page 5 added Ordering Information on page 12 changed ATA6025 4716C–AUTO–09/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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