FAIRCHILD FM34W02UL

FM34W02U
2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Designed with Permanent Write-Protection for First 128 Bytes for Serial Presence
Detect Application on Memory Modules (PC100/PC133 Compliant)
General Description
Features
The FM34W02U is 2048 bits of CMOS non-volatile electrically
erasable memory. This device is specifically designed to support
Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA)
lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).
■ PC100/PC133 Compliant
■ Extended Operating Voltage: 2.7V-5.5V
■ Software Write-Protection for first 128 bytes
■ Hardware Write-Protection for entire memory array
■ 200 µA active current typical
– 1.0 µA standby current typical (L)
– 0.1 µA standby current typical (LZ)
The contents of the non-volatile memory allows the CPU to
determine the capacity of the module and the electrical characteristics of the memory devices it contains. This will enable "plug and
play" capability as the module is read and PC main memory
resources utilized through the memory controller.
■ IIC compatible interface
– Provides bidirectional data transfer protocol
■ Sixteen byte page write mode
– Minimizes total write time per byte
The first 128 bytes of the memory of the FM34W02U can be
permanently Write Protected by writing to the "WRITE PROTECT"
Register. Write Protect implementation details are described
under the section titled Addressing the WP Register.
■ Self timed write cycle
- Typical write cycle time of 6ms
■ Endurance: 1,000,000 data changes
The FM34W02U is available in a JEDEC standard TSSOP package for low profile memory modules for systems requiring efficient
space utilization such as in a notebook computer. Two options are
available: L - Low Voltage and LZ - Low Power, allowing the part
to be used in systems where battery life is of primary importance.
■ Data retention greater than 40 years
■ Packages available: 8-pin TSSOP and 8-pin SO
■ Temperature Ranges: Commercial and Extended
Block Diagram
VCC
VSS
WP
H.V. GENERATION
TIMING &CONTROL
START CYCLE
START
STOP
LOGIC
SDA
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
SCL
16
XDEC
LOAD
A2
A1
A0
E2PROM
ARRAY
16 x 16 x 8
INC
WORD
ADDRESS
COUNTER
0/1/2/3
4
16
4
R/W
YDEC
Device Address Bits
Write Protect
Register
© 2001 Fairchild Semiconductor Corporation
FM34W02U Rev. A.1
8
CK
DATA REGISTER
DIN
1
DOUT
www.fairchildsemi.com
FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
May 2001
SO (M8) and TSSOP (MT8) Package
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
VSS
4
5
SDA
FM34W02U
Top View
See Package Number
M08A and MTC08
Pin Names
A0,A1,A2
Device Address Inputs
VSS
Ground
SDA
Data I/O
SCL
Clock Input
WP
Write Protect
VCC
Power Supply
Ordering Information
FM
34
W
02
U
LZ
E
XX
Letter Description
Package
M8
MT8
8-Pin SO8
8-Pin TSSOP
Temp. Range
None
E
0 to 70°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Process
U
Ultralite CS100UL
Density
02
2K
W
Full Array Write Protect
34
IIC
FM
Fairchild Non-Volatile
Memory
Interface
2
FM34W02U Rev. A.1
www.fairchildsemi.com
FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Connection Diagram
Operating Conditions
Absolute Maximum Ratings
Ambient Storage Temperature
Ambient Operating Temperature
FM34W02U
FM34W02UE
–65°C to +150°C
All Input or Output Voltages
with Respect to Ground
6.5V to –0.3V
Lead Temperature
(Soldering, 10 seconds)
Positive Power Supply
FM34W02U
FM34W02UL
FM34W02ULZ
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
2000V min.
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Limits
Typ
(Note 1)
Max
Units
ICCA
Active Power Supply Current
fSCL = 400 kHz
0.2
1.0
mA
ISB
Standby Current
VIN = GND or VCC
10
50
µA
ILI
Input Leakage Current
VIN = GND to VCC
0.1
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
0.1
1
µA
VIL
Input Low Voltage
–0.3
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
IOL = 3 mA
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Limits
Typ
(Note 1)
Max
Units
ICCA
Active Power Supply Current
fSCL = 400 kHz
0.2
1.0
mA
ISB
Standby Current
VIN = GND or VCC = 4.5V - 5.5V
VIN = GND or VCC = 2.7V - 5.5V (L)
VIN = GND or VCC = 2.7V - 5.5V (LV)
10
1
0.1
50
10
1
µA
µA
µA
ILI
Input Leakage Current
VIN = GND to VCC
0.1
1
µA
VOUT = GND to VCC
ILO
Output Leakage Current
1
µA
VIL
Input Low Voltage
–0.3
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
0.1
IOL = 3 mA
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
Test
Conditions
Max
Units
CI/O
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN
Input Capacitance (A0, A1, A2, SCL)
VIN = 0V
6
pF
Note 1: Typical values are TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.
3
FM34W02U Rev. A.1
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FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Product Specifications
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels
VCC x 0.5
Output Load
1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
fSCL
TI
Parameter
100 KHz
Min
Max
400 KHz
Min
Max
Units
SCL Clock Frequency
100
400
KHz
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
50
ns
0.9
µs
tAA
SCL Low to SDA Data Out Valid
0.3
tBUF
Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
µs
Start Condition Hold Time
4.0
0.6
µs
tLOW
Clock Low Period
4.7
1.5
µs
tHIGH
Clock High Period
4.0
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data in Hold Time
0
0
ns
tSU:DAT
Data in Setup Time
250
100
ns
tHD:STA
tR
SDA and SCL Rise Time
tF
SDA and SCL Fall Time
tSU:STO
tDH
tWR
(Note 3)
3.5
0.1
1
300
0.3
µs
300
ns
Stop Condition Setup Time
4.7
0.6
µs
Data Out Hold Time
300
50
ns
Write Cycle Time - FM34W02U
- FM34W02UL, FM34W02ULZ
10
15
10
15
ms
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM34W02U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
4
FM34W02U Rev. A.1
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FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
AC Conditions of Test
tR
tF
tHIGH
tLOW
tLOW
SCL
;;
tSU:STA
tHD:DAT
tHD:STA
SDA
tSU:DAT
tSU:STO
IN
tBUF
tAA
tDH
SDA
OUT
Background Information (IIC Bus)
DEFINITIONS
As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condition.
BYTE
8 bits of data
PAGE
16 sequential addresses (one byte
each) that may be programmed
during a 'Page Write' programming
cycle
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROMs, etc., a device type identifier string must
follow the START condition. For EEPROMs, this 4-bit string is
1010. Also refer the Addressing the WP Register section.
PAGE BLOCK
2,048 (2K) bits organized into 16
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) = 2,048
bits
MASTER
Any IIC device CONTROLLING the
transfer of data (such as a microprocessor)
SLAVE
Device being controlled (EEPROMs
are always considered Slaves)
TRANSMITTER
Device currently SENDING data on
the bus (may be either a Master or
Slave).
RECEIVER
Device currently receiving data on the
bus (Master or Slave)
As shown below, although the EEPROMs on the IIC bus may be
configured in any manner required, the total memory addressed
can not exceed 16K (16,384 bits) on the Standard IIC. EEPROM
memory address programming is controlled by 2 methods:
• Hardware configuring the A0, A1, and A2 pins (Device
Address pins) with pull-up or pull-down to VCC or VSS. All
unused pins must be grounded (tied to VSS).
• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]—[DEVICE ADDRESS]—[PAGE BLOCK
ADDRESS]—[BYTE ADDRESS]
Example of 16K of Memory on 2-Wire Bus
VCC
VCC
SDA
SCL
VCC
VCC
VCC
34C02L
24C02
24C04
24C08
A0 A1 A2 VSS
A0 A1 A2 VSS
A0 A1 A2 VSS
A0 A1 A2 VSS
To VCC or VSS
Note:
VCC
To VCC or VSS
To VCC or VSS
To VCC or VSS
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
5
FM34W02U Rev. A.1
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FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Bus Timing
FM34W02U
Address Pins
A0
A1
A2
ADR
ADR
ADR
Memory Size
Number of
Page Blocks
2048 Bits
1
Pin Descriptions
Start Condition
Serial Clock (SCL)
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
FM34W02U continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until this
condition has been met.
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
Stop Condition
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM34W02U to place the device in the
standby power mode.
Device Operation Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or VSS
to configure the EEPROM chip address. Table A shows the active
pins across the FM34W02U device family.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits.
Table 1.
Device
A0
A1
A2
FM34W02U ADR ADR ADR
Effects of Addresses
During the ninth clock cycle the receiver will pull the SDA line to
LOW to acknowledge that it received the eight bits of data. Refer
to Figure 3.
8 devices max.
Device Operation
The FM34W02U device will always respond with an acknowledge
after recognition of a start condition and its slave address. If both
the device and a write operation have been selected, the
FM34W02U will respond with an acknowledge after the receipt of
each subsequent eight bit byte.
The FM34W02U supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as
a transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the FM34W02U will be considered a slave
in all applications.
In the Read mode the FM34W02U slave will transmit eight bits of
data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to Figures 1 and 2.
6
FM34W02U Rev. A.1
www.fairchildsemi.com
FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Device
FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Write Cycle Timing
SCL
SDA
8th BIT
ACK
WORD n
tWR
STOP
CONDITION
START
CONDITION
SDA
DATA STABLE
DATA
CHANGE
SCL
Data Validity (Figure 1).
SDA
START
CONDITION
SCL
STOP
CONDITION
Start and Stop Definition (Figure 2).
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
Acknowledge Responses from Receiver (Figure 3).
Device Addressing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier (see Figure 4). This
is fixed as 1010 for all EEPROM devices.
All IIC EEPROMs use an internal protocol that defines a PAGE
BLOCK size of 2K bits (for Byte addresses 00 through FF).
7
FM34W02U Rev. A.1
www.fairchildsemi.com
Device Type
Identifier
and the previously written data will be overwritten. As with the byte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address, acknowledge, and data transfer sequence.
Device
Address
Acknowledge Polling
1
0
1
0
A2
A1
A0
R/W
(LSB)
Once the stop condition is issued to indicate the end of the host’s
write operation the FM34W02U initiates the internal write cycle.
ACK polling can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write operation.
If the FM34W02U is still busy with the write operation no ACK will
be returned. If the FM34W02U has completed the write operation
an ACK will be returned and the host can then proceed with the
next read or write operation.
34W02
Slave Addresses (Figure 4).
Refer to the following table for Slave Address string details:
Device
A0
A1
A2
Page
Blocks
Page Block
Addresses
FM34W02U
A
A
A
1 (2K)
(None)
Software Write Protect
Software write protection on the FM34W02U protects the first 128
bytes of the EEPROM memory. Software write protection is
implemented through a seperate register called the WRITE PROTECT (WP) Register and writing to this WP register permanently
WRITE protects the memory. This WP register is a "one-timeonly-write" register. Once this register is written, it cannot be
erased. After the first WRITE to this register, all future access'
to this register are ignored as if an invalid IIC cycle occured.
To write protect, the user must perform a byte write to the WP
register. This will permanently disable programming to the first
128 bytes of memory.
Write Operations
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
A simple review: After the FM34W02U recognizes the start
condition, the devices interfaced to the IIC bus wait for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the SDA line LOW with an acknowledge
signal and awaits further transmissions.
Addressing the WP Register
Byte Write
Addressing the WP register is very similar to accessing any
memory array with the following difference:
For a write operation a second address field is required which is
a byte address that is comprised of eight bits and provides access
to any one of the 256 bytes in the selected page block of memory.
Upon receipt of the byte address the FM34W02U responds with
an acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
FM34W02U begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the FM34W02U
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
Instead of the conventional "1010" IIC device address, the unused
IIC device address "0110" is used to access just the WP register.
Device address "1010" will be used for all the typical memory array
access. With this difference in place, accessing the WP register is
same as a typical IIC byte write cycle as described under "Write
Operations" section. All timing information and waveform details
remain the same. The "Byte Address" and the "Data" fields of the
Byte write cycle serve as place holders and can be of any value
(Don't Care). Refer to Figure 7.
Hardware Write Protect
Programming of the memory will not take place if the WP pin of the
FM34W02U is connected to VCC, regardless of whether the
software write protect register has been implemented or not. The
FM34W02U will accept slave and word addresses; but if the
memory accessed is write protected by the WP pin, the FM34W02U
will not generate an acknowledge after the first byte of data has
been received, and thus the program cycle will not be started when
the stop condition is asserted. (Note: if the WP pin is set to VCC,
it will prevent the software write protect register from being
written.)
Page Write
The FM34W02U is capable of a sixteen byte page write operation.
It is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data byte is
transferred, the master can transmit up to fifteen more bytes. After
the receipt of each byte, the FM34W02U will respond with an
acknowledge.
After the receipt of each byte, the internal address counter
increments to the next address and the next SDA data is accepted.
If the master should transmit more than sixteen bytes prior to
generating the stop condition, the address counter will 'roll over'
8
FM34W02U Rev. A.1
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FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Device Addressing (Continued)
Bus Activity:
Master
S
T
A
R
T
SLAVE
ADDRESS
WORD
ADDRESS
S
T
O
P
DATA
SDA Line
A
C
K
A
C
K
A
C
K
Byte Write (Figure 5).
Bus Activity:
Master
S
T
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS (n)
DATA n
DATA n + 1
S
T
O
P
DATA n + 15
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Page Write (Figure 6).
Bus Activity:
Master
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
SDA Line
Bus Activity:
DEVICE
ADDRESS
A
C
K
DON'T CARE
A
C
K
DON'T CARE
A
C
K
WP Register Write (Figure 7).
Read Operations
be read. After the slave word address acknowledge, the master
immediately reissues the start condition and the slave address
with the R/W bit set to one. This will be followed by an acknowledge from the FM34W02U and then by the eight bit word. The
master will not acknowledge the transfer but does generate the
stop condition, and therefore the FM34W02U discontinues transmission. Refer to Figure 9 for the address, acknowledge and data
transfer sequence.
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to a one. There are three basic read operations: current
address read, random read, and sequential read.
CURRENT ADDRESS READ
Internally the FM34W02U contains an address counter that maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address
n, the next read operation would access data from address n + 1.
Upon receipt of the slave address with R/W set to one, the
FM34W02U issues an acknowledge and transmits the data byte.
The master will not acknowledge the transfer but does generate
a stop condition, and therefore the FM34W02U discontinues
transmission. Refer to Figure 8 for the sequence of address,
acknowledge and data transfer.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The FM34W02U continues to output data for each acknowledge received. The read operation is terminated by the master not
responding with an acknowledge or by generating a stop condition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter 'rolls over' and the
FM34W02U continues to output data for each acknowledge
received. Refer to Figure 10 for the address, acknowledge, and
data transfer sequence.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address, R/W bit set to zero, and then the word address to
9
FM34W02U Rev. A.1
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FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Write Protect Scheme (Continued)
Bus Activity:
Master
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
SDA Line
A
C
K
DATA
Random Read (Figure 9)
Bus Activity:
Master
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS
S
T
O
P
SLAVE
ADDRESS
SDA Line
A
C
K
A
C
K
A
C
K
DATA n
Sequential Read (Figure 10)
A
C
K
Bus Activity:
SLAVE
Master ADDRESS
S
T
O
P
A
C
K
A
C
K
SDA Line
A
C
K
DATA n
DATA n +1
DATA n + 2
DATA n + x
Typical System Configuration (Figure 11)
VCC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
Note:
Due to open drain configuration of SDA, a bus-level resistor is called for
(Typical value = 4.7Ω)
10
FM34W02U Rev. A.1
www.fairchildsemi.com
FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Current Address Read (Figure 8)
FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45¡
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
8¡ Max, Typ.
All leads
0.004
(0.102)
All lead tips
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
8-Pin Molded Small Outline Package (M8)
Order Number FM34W02ULM8/LZM8
Package Number M08A
11
FM34W02U Rev. A.1
www.fairchildsemi.com
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0118
(0.19 - 0.30)
Gage
plane
0¡-8¡
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Order Number FM34W02ULMT8/LZMT8
Package Number MTC08
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
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Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
12
FM34W02U Rev. A.1
www.fairchildsemi.com
FM34W02U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
with Full Array Write Protect
Physical Dimensions inches (millimeters) unless otherwise noted