FM24CL04B 4Kb Serial 3V F-RAM Memory Features 4K bit Ferroelectric Nonvolatile RAM Organized as 512 x 8 bits High Endurance 1014 Read/Writes 38 Year Data Retention NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface Up to 1 MHz maximum bus frequency Direct hardware replacement for EEPROM Supports legacy timing for 100 kHz & 400 kHz Description Low Power Operation 2.7V to 3.65V operation 100 A Active Current (100 kHz) 3 A (typ.) Standby Current Industry Standard Configuration Industrial Temperature -40 C to +85 C 8-pin “Green”/RoHS SOIC (-G) Pin Configuration The FM24CL04B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM24CL04B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM24CL04B is capable of supporting 1014 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM24CL04B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. NC 1 8 VDD A1 2 7 WP A2 3 6 VSS 4 5 SCL SDA Pin Names A1-A2 SDA SCL WP VSS VDD Function Device Select Address 1 and 2 Serial Data/Address Serial Clock Write Protect Ground Supply Voltage Ordering Information FM24CL04B-G FM24CL04B-GTR “Green”/RoHS 8-pin SOIC “Green”/RoHS 8-pin SOIC, Tape & Reel The FM24CL04B provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24CL04B is available in an industry standard 8pin SOIC package and uses a familiar two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Cypress Semiconductor Corporation • Document Number: 001-84455 Rev. *A 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 07, 2013 FM24CL04B Address Latch Counter 64 x 64 FRAM Array 8 Serial to Parallel Converter SDA Data Latch SCL WP A1 A2 Control Logic Figure 1. Block Diagram Pin Description Pin Name A1-A2 I/O Input SDA I/O SCL Input WP Input NC VDD VSS Supply Supply Pin Description Address 1-2: The address pins set the device select address. The device address value in the 2-wire slave address must match the setting of these two pins. These pins are internally pulled down. Serial Data/Address: This is a bi-directional pin used to shift serial data and addresses for the two-wire interface. It employs an open-drain output and is intended to be wireOR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. A pull-up resistor is required. Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL input also incorporates a Schmitt trigger input for improved noise immunity. Write Protect: When WP is high, the entire array is write-protected. When WP is low, all addresses may be written. This pin is internally pulled down. No connect Supply Voltage Ground Document Number: 001-84455 Rev. *A Page 2 of 13 FM24CL04B Overview Two-wire Interface The FM24CL04B is a serial FRAM memory. The memory array is logically organized as 512 x 8 and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM24CL04B and a serial EEPROM with the same pinout relates to its superior write performance. The FM24CL04B employs a bi-directional two-wire bus protocol using few pins and little board space. Figure 2 illustrates a typical system configuration using the FM24CL04B in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. Memory Architecture When accessing the FM24CL04B, the user addresses 512 locations each with 8 data bits. These data bits are shifted serially. The 512 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish other devices), a page address, and a word address. The word address consists of 8bits that specify one of 256 addresses. The page address is 1-bit and so there are 2 pages of 256 locations. The complete address of 9-bits specifies each byte address uniquely. Most functions of the FM24CL04B either are controlled by the two-wire interface or are handled automatically by on-board circuitry. The memory is read or written at the speed of the two-wire bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24CL04B is always a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions: Start, Stop, Data bit, and Acknowledge. Figure 3 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications. VDD Rmin = 1.1 Kohm Rmax = tR/Cbus Microcontroller SDA SCL FM24CL04B Users can expect several obvious system benefits from the FM24CL04B due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. A1 A2 SDA SCL FM24CL04B A1 A2 Figure 2. Typical System Configuration Note that the FM24CL04B contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within data sheet tolerances to prevent incorrect operation. Document Number: 001-84455 Rev. *A Page 3 of 13 FM24CL04B Figure 3. Data Transfer Protocol error. Second and most common, the receiver does Stop Condition not acknowledge the data to deliberately end an A Stop condition is indicated when the bus master operation. For example, during a read operation, the drives SDA from low to high while the SCL signal is FM24CL04B will continue to place data onto the bus high. All operations must end with a Stop condition. If as long as the receiver sends acknowledges (and an operation is pending when a stop is asserted, the clocks). When a read operation is complete and no operation will be aborted. The master must have more data is needed, the receiver must not control of SDA (not a memory read) in order to assert acknowledge the last byte. If the receiver a Stop condition. acknowledges the last byte, this will cause the FM24CL04B to attempt to drive the bus on the next Start Condition clock while the master is sending a new command A Start condition is indicated when the bus master such as a Stop command. drives SDA from high to low while the SCL signal is high. All read and write transactions begin with a Start Slave Address condition. An operation in progress can be aborted by The first byte that the FM24CL04B expects after a asserting a Start condition at any time. Aborting an start condition is the slave address. As shown in operation using the Start condition will ready the Figure 4, the slave address contains the device type, FM24CL04B for a new operation. the device select, the page of memory to be accessed, and a bit that specifies if the transaction is If during operation the power supply drops below the a read or a write. specified VDD minimum, the system should issue a Start condition prior to performing another operation. Bits 7-4 are the device type and should be set to 1010b for the FM24CL04B. The device type allows Data/Address Transfer other types of functions to reside on the 2-wire bus All data transfers (including addresses) take place within an identical address range. Bits 3-2 are the while the SCL signal is high. Except under the two device address. If bit 3 matches the A2 pin and bit 2 conditions described above, the SDA signal should not matches the A1 pin the device will be selected. Bit 1 change while SCL is high. is the page select. It specifies the 256-byte block of memory that is targeted for the current operation. Bit Acknowledge th 0 is the read/write bit. A 0 indicates a write The Acknowledge takes place after the 8 data bit has operation. been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the Word Address receiver to drive it. The receiver drives the SDA signal After the FM24CL04B (as receiver) acknowledges low to acknowledge receipt of the byte. If the receiver the slave ID, the master will place the word address does not drive SDA low, the condition is a Noon the bus for a write operation. The word address is Acknowledge and the operation is aborted. the lower 8-bits of the address to be combined with The receiver could fail to acknowledge for two distinct the 1-bit page select to specify exactly the byte to be reasons. First, if a byte transfer fails, the Nowritten. The complete 9-bit address is latched Acknowledge ends the current operation so that the internally. device can be addressed again. This allows the last byte to be recovered in the event of a communication Document Number: 001-84455 Rev. *A Page 4 of 13 FM24CL04B Memory Operation Figure 4. Slave Address No word address occurs for a read operation. Reads always use the lower 8-bits that are held internally in the address latch and the 9th address bit is part of the slave address. Reads always begin at the address following the previous access. A random read address can be loaded by doing a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24CL04B increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (1FFh) is reached, the address latch will roll over to 000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Data Transfer After all address information has been transmitted, data transfer between the bus master and the FM24CL04B can begin. For a read operation the FM24CL04B will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded. For a write operation, the FM24CL04B will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. The FM24CL04B is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24CL04B and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a slave address then a word address. The bus master indicates a write operation by setting the LSB of the Slave address to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 1FFh to 000h. Unlike other nonvolatile memory technologies, there is no write delay with FRAM. The entire memory cycle occurs in less time than a single bus clock. Therefore any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a done condition. An actual memory array write occurs after the 8th data bit is transferred. It will be complete before the acknowledge is sent. Therefore if the user desires to abort a write without altering the memory contents, this should be done using a start or stop condition prior to the 8th data bit. The FM24CL04B needs no page buffering. The memory array can be write protected using the WP pin. Pulling WP high will disable writes to the entire array. The FM24CL04B will not acknowledge data bytes that are written when write protect is asserted. In addition, the address counter will not increment if writes are attempted. Pulling WP low (VSS) will deactivate this feature. Figure 5 below illustrates both a single- and multiple- byte write. Document Number: 001-84455 Rev. *A Page 5 of 13 FM24CL04B Start By Master S Address & Data Slave Address 0 A Word Address By FM24CL04B Stop A Data Byte A P Acknowledge Figure 5. Byte Write By Master Start S Address & Data Slave Address 0 A Word Address Stop A By FM24CL04B Data Byte A Data Byte A P Acknowledge Figure 6. Multiple Byte Write Read Operation There are two basic types of read operations. They are current address read and selective address read. In a current address read, the FM24CL04B uses the internal address latch to supply the lower 8 address bits. In a selective read, the user performs a procedure to set these lower address bits to a specific value. Current Address & Sequential Read The FM24CL04B uses an internal latch to supply the lower 8 address bits for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. This is the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to 1. This indicates that a read operation is requested. The page select bit in the slave address specifies the block of memory that is used for the read operation. After the acknowledge, the FM24CL04B will begin shifting out data from the current address. The current address is the bit from the slave address combined with the 8 bits that were in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Each time the bus master acknowledges a byte, this indicates that the FM24CL04B should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24CL04B Document Number: 001-84455 Rev. *A attempts to read out additional data onto the bus. The four valid methods are as follows. 1. 2. 3. 4. The bus master issues a no-acknowledge in the 9th clock cycle and a stop in the 10th clock cycle. This is illustrated in the diagrams below. This is the preferred method. The bus master issues a no-acknowledge in the 9th clock cycle and a start in the 10th. The bus master issues a stop in the 9th clock cycle. Bus contention may result. The bus master issues a start in the 9th clock cycle. Bus contention may result. If the internal address reaches 1FFh it will wrap around to 000h on the next read cycle. Figures 7 and 8 show the proper operation for current address reads. Selective (Random) Read A simple technique allows a user to select a random address location as the starting point for a read operation. This involves using the first two bytes of a write operation to set the internal address byte followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the word address byte that is loaded into the internal address latch. After the FM24CL04B acknowledges the word address, the bus master issues a start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a 1. The operation is now a current address read. See Figure 9. Page 6 of 13 FM24CL04B Start By Master No Acknowledge Address Stop S Slave Address By FM24CL04 1 A Data Byte Acknowledge 1 P Data Figure 7. Current Address Read By Master Start Address No Acknowledge Acknowledge Stop S Slave Address By FM24CL04 1 A Data Byte A Acknowledge Data Byte 1 P Data Figure 8. Sequential Read By Master Address Start Start Address No Acknowledge Acknowledge Stop S Slave Address 0 A Word Address By FM24CL04 A S Slave Address 1 A Data Byte Acknowledge A Data Byte 1 P Data Figure 9. Selective (Random) Read Document Number: 001-84455 Rev. *A Page 7 of 13 FM24CL04B Electrical Specifications Absolute Maximum Ratings Symbol VDD VIN TSTG TLEAD VESD Description Power Supply Voltage with respect to VSS Voltage on any signal pin with respect to VSS Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) Package Moisture Sensitivity Level Ratings -1.0V to +5.0V -1.0V to +5.0V and VIN < VDD+1.0V * -55 C to + 125 C 260 C 3.5kV 1.25kV 250V MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Typ Max Units VDD Main Power Supply 2.7 3.3 3.65 V IDD VDD Supply Current @ SCL = 100 kHz 100 A @ SCL = 400 kHz 170 A @ SCL = 1 MHz 300 A ISB Standby Current 3 6 A ILI Input Leakage Current ±1 A ILO Output Leakage Current ±1 A VIH Input High Voltage 0.7 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.3 VDD V VOL Output Low Voltage 0.4 V @ IOL = 3.0 mA RIN Input Resistance (WP, A2, A1) For VIN = VIL (max) 40 K For VIN = VIH (min) 1 M VHYS Input Hysteresis 0.05 VDD V Notes 1 2 3 3 5 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A1, A2 pins. 4. This parameter is periodically sampled and not 100% tested. 5. The input pull-down circuit is strong (40K ) when the input voltage is below VIL and much weaker (1M ) when the input voltage is above VIH. Document Number: 001-84455 Rev. *A Page 8 of 13 FM24CL04B AC Parameters (TA = -40 C to + 85 C, VDD = 2.7V to 3.65V, CL = 100 pF unless otherwise specified) Symbol fSCL tLOW tHIGH tAA Parameter SCL Clock Frequency Clock Low Period Clock High Period SCL Low to SDA Data Out Valid Min 0 4.7 4.0 tBUF Bus Free Before New Transmission Start Condition Hold Time Start Condition Setup for Repeated Start Data In Hold Data In Setup Input Rise Time Input Fall Time Stop Condition Setup Data Output Hold (from SCL @ VIL) Noise Suppression Time Constant on SCL, SDA 4.7 1.3 0.5 s 4.0 4.7 0.6 0.6 0.25 0.25 s s 0 250 0 100 0 100 300 100 ns ns ns ns s ns 50 ns tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tSP Max 100 Min 0 1.3 0.6 3 Min 0 0.6 0.4 0.9 1000 300 4.0 0 Max 400 0.55 300 300 0.6 0 50 Max 1000 0.25 0 50 Units kHz s s s Notes 1 1 Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3V) Symbol Parameter CI/O Input/Output Capacitance (SDA) CIN Input Capacitance Max 8 6 Units pF pF Notes 1 1 Notes 1 This parameter is periodically sampled and not 100% tested. Power Cycle Timing VDD VDD min. tVR tVF tPU tPD SDA,SCL Power Cycle Timing (TA = -40 C to +85 C, VDD = 2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Max tPU Power Up (VDD min) to First Access (Start condition) 1 tPD Last Access (Stop condition) to Power Down (VDD min) 0 tVR VDD Rise Time 30 tVF VDD Fall Time 30 Notes 1. Slope measured at any point on VDD waveform. Document Number: 001-84455 Rev. *A Units Notes ms s s/V s/V 1 1 Page 9 of 13 FM24CL04B AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Equivalent AC Load Circuit 0.1 VDD to 0.9 VDD 10 ns 0.5 VDD 3.6V 1100 Output Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. 100 pF Read Bus Timing tR ` tF tHIGH tSP tLOW tSP SCL tSU:SDA 1/fSCL tBUF tHD:DAT tSU:DAT SDA tDH tAA Stop Start Start Acknowledge Write Bus Timing tHD:DAT SCL tHD:STA tSU:STO tSU:DAT tAA SDA Start Stop Start Data Retention Symbol Parameter TDR @ +85ºC @ +80ºC @ +75ºC Document Number: 001-84455 Rev. *A Acknowledge Min 10 19 38 Max - Units Years Years Years Notes Page 10 of 13 FM24CL04B Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Recommended PCB Footprint 7.70 3.90 ±0.10 3.70 6.00 ±0.20 2.00 0.65 1.27 Pin 1 4.90 ±0.10 1.27 0.33 0.51 0.25 0.50 1.35 1.75 0.10 0.25 0.19 0.25 45 0.10 mm 0-8 0.40 1.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme XXXXXXXP RLLLLLLL RICYYWW Legend: XXXXXX= part number, P= package type (G=SOIC) R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24CL04B, “Green” SOIC package, Year 2010, Work Week 49 FM24CL04BG A00002G1 RIC1049 Document Number: 001-84455 Rev. *A Page 11 of 13 FM24CL04B Revision History Revision 1.0 1.1 1.2 1.3 3.0 Date 11/10/2010 12/20/2010 1/31/2011 2/15/2011 1/6/2012 Summary Initial Release Changed VIH (max) spec to VDD+0.3V. Added ESD ratings. Changed tPU and tVF spec limits. Changed to Production status. Changed tVF spec. Document History Document Title: FM24CL04B 4Kb Serial 3V F-RAM Memory Document Number: 001-84455 Revision ECN Orig. of Change Submission Date ** 3902082 GVCH 02/25/2013 New Spec *A 3924523 GVCH 03/07/2013 Changed tPU spec value from 10ms to 1ms Document Number: 001-84455 Rev. *A Description of Change Page 12 of 13 FM24CL04B Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/usb Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support RAMTRON is a registered trademark and NoDelay™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2011-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-84455 Rev. *A Page 13 of 13