www.fairchildsemi.com FMS7951 Zero Delay Clock Multiplier Features • • • • • • • • • It has four banks of configurable outputs. By externally connecting one of the outputs to FBIN, the internal PLL will lock in both phase and frequency to the incoming clock. Any changes to the input clock will be tracked by the outputs. Depending on the selected output for feedback connection, the output frequencies will be as 1X, 2X or 4X of the input. Low Voltage CMOS or PECL reference input Up to 175 MHz of output frequency Nine configurable outputs Output enable pin 250 pS of output to output skew 300 pS of Cycle to Cycle Jitter VDD Range of 3.3V ±0.2V Commercial temperature range Available in 32 pin TQFP Description FMS7951 is a high speed, zero delay, low skew clock driver. It uses phase locked loop technology to generate frequencies up to 175 MHz. REF_SEL allows selection between PECL input or TCLK a CMOS clock driven input. Connecting PLL_EN LOW and REF_SEL HIGH will by pass the Phase locked loop. In this mode, FMS7951 will be in clock buffer mode where any clock applied to TCLK will be divided down to the four output banks. This is ideal for system diagnostic test. When PLL_EN is HIGH, the PLL is enabled, and any clock applied to TCLK will be locked in both phase and frequency to FBIN. PECL_CLK is activated when REF_SEL is high. FMS7951 operates at 3.3 Volts and is available in 32 pin LQFP. Block Diagram REF_SEL PLL_EN OE TCLK QA MUX QB MUX PECL_CLK PECL_CLK PLL QC0 FBIN QC1 QD0 QD1 DIV_SEL A QD2 DIV_SEL B DIV_SEL C Control Logic QD3 DIV_SEL D QD4 REV. 1.0.0 1/9/01 PRODUCT SPECIFICATION FMS7951 VDDCOR FBIN 1 2 DIV_SEL A 3 4 DIV_SEL B GNDOUT QB GNDOUT QA VDDOUT TCLK PLL_EN REF_SEL Pin Assignments 32 31 30 29 28 27 26 25 24 23 QC0 22 QC1 21 GNDOUT QD0 32-PIN LQFP DIV_SEL C DIV_SEL D 5 6 20 19 GNDCOR PECL_CLK 7 8 18 17 VDDOUT VDDOUT QD1 GNDOUT QD2 QD3 VDDOUT GNDOUT QD4 VDDOUT PECL_CLK OE 9 10 11 12 13 14 15 16 Pin Description Pin Name Pin # Pin Type VDDCOR 1 PWR FBIN 2 IN Feedback In. PLL feedback input. The user connects it to one of the outputs. 3, 4, 5, 6 IN Divider Select: It divides the clock to a desirable value. See table 2. No internal pull up or pull down. 7 PWR Ground Connection. Ground for core logic and PLL circuitry. Connect to the common system ground plane. PECL_CLK/ PECL_CLK 8, 9 IN PECL Clock Input: These are differential PECL inputs when REF_SEL is Low, they are activated. OE 10 IN Output Enable. When high, all outputs are in high impedance. Normal operation when asserted low. 11, 15, 19, 23, 27 PWR Power Connection. Power supply for all the output buffers. Connect to 3.3 Volts nominal. QA; QB; QC(0:1); 12, 14, 16, 18, 20, 22, 24, 26, 28 QD(0:4) OUT Clock Outputs. These outputs are multiple of the input. GNDOUT 13, 17, 21, 25, 29 PWR Ground Connection. Ground for all the outputs. Connect to common system ground plane. TCLK 30 IN Test Clock. When PLL-EN is low, all outputs are buffer copy of TCLK. PLL_EN 31 IN PLL Enable. When low, PLL is by passed. REF_SEL 32 IN Reference Select. When low, PECL_CLK/PECL_CLK is used for input. When high, TCLK is used for input. DIV_SEL(A:D) GNDCOR VDDOUT 2 Description Power Connection. Power supply for core logic and PLL circuitry. Connect to 3.3 Volts nominal. REV. 1.0.0 1/9/01 FMS7951 PRODUCT SPECIFICATION Table 1. Functionality REF_SEL PLL_EN OE PLL All Outputs Input 0 0 1 By Pass Hi-Z PECL_CLK 0 0 0 By Pass Running PECL_CLK 0 1 0 Enabled Running PECL_CLK 1 0 1 By Pass Hi-Z TCLK 1 0 0 By Pass Running TCLK 1 1 0 Enabled Running TCLK Table 2. Input Versus Output Frequency DIV_SELA DIV_SELB DIV_SELC DIV_SELD QA QB QC QD 0 0 0 0 2XREF REF REF REF 0 0 0 1 4XREF 2XREF 2XREF REF 0 0 1 0 2XREF REF 1/2REF REF 0 0 1 1 4XREF 2XREF REF REF 0 1 0 0 2XREF 1/2REF REF REF 0 1 0 1 4XREF REF 2XREF REF 0 1 1 0 2XREF 1/2REF 1/2REF REF 0 1 1 1 4XREF REF REF REF 1 0 0 0 REF REF REF REF 1 0 0 1 2XREF 2XREF 2XREF REF 1 0 1 0 REF REF 1/2REF REF 1 0 1 1 2XREF 2XREF REF REF 1 1 0 0 REF 1/2REF REF REF 1 1 0 1 2XREF REF 2XREF REF 1 1 1 0 REF 1/2REF 1/2REF REF 1 1 1 1 2XREF REF REF REF Note: 1. Reference input could be either PECL_CLK or TCLK input. 2. FBIN is tied to QD output for table Table 3. Divide Select Functionality DIV_SEL A DIV_SEL B DIV_SEL D DIV_SEL D QA QB QC QD 0 0 0 0 ÷2 ÷4 ÷4 ÷4 1 1 1 1 ÷4 ÷8 ÷8 ÷8 REV. 1.0.0 1/9/01 3 PRODUCT SPECIFICATION FMS7951 Absolute Maximum Ratings Symbol Parameter Ratings Units VDD, VIN Voltage on any pin with respect to ground -0.5 to 7.0 V TSTG Storage Temperature -65 to 150 °C TB Ambient Temperature -55 to 125 °C TA Operating Temperature 0 to 70 °C Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability. DC Electrical Characteristics TA = 0 to 70°C; Supply Voltage 3.3 V ±0.2V (unless otherwise stated) Parameter Symbol Conditions Min. Typ. Max. Units 0.8 V Input Low Voltage VIL TCLK; control pins Input High Voltage VIH TCLK; control pins 2.0 3.6 V Input Low Current IIL VIN= 0 -10 10 µA Input High Current IIH VIN= VDD -30 30 µA Peak to Peak Input Voltage VPP PECL_CLK/PCL_CLK 0.3 1.0 V VDD-2.0 VDD-0.6 mV Common Mode Range VCMR Output Low Voltage VOL IOL= 40 mA Output High Voltage VOH IOH= –40mA Input Capacitance(1) CIN Supply Current IDD Clock Stabilization(1) 0.5 2.2 Outputs loaded TSTAB V V TBD From VDD = 3.3V to 1% Target 7.0 pF 150 mA 10 mS Max. Units MHz Note: 1. Guaranteed by design, not subject to 100% production testing. AC Electrical Characteristics TA = 0 to 70°C; Supply Voltage VDD = 3.3V ±0.2V, CL = 10 pF (unless otherwise stated) Parameter Symbol Input Frequency FIN (1) TCLK Input Rise/Fall Time Conditions Typ. Feedback Divide = 2 10 175 Feedback Divide = 4 10 85 Feedback Divide = 8 10 42 TR_IN/TF_IN – 3.0 ns (1) TCLK Input Duty Cycle DT_IN 25 75 % Output Frequency Range FOUT Output to Output Skew TSK1 QA; DIV_SEL A = 0V 175 MHz QB, QC & QD; DIV_SEL B, C, D = 0V 88 MHz VTH = VDD/2; DIV_SEL A = 0 750 pS VTH = VDD/2; DIV_SEL A = 1 Input to FBIN Delay TSK2 TCLK PECL_CLK 4 Min. -300 300 50 400 -950 -600 pS REV. 1.0.0 1/9/01 FMS7951 PRODUCT SPECIFICATION AC Electrical Characteristics (Cont.) TA = 0 to 70°C; Supply Voltage VDD = 3.3V ±0.2V, CL = 10 pF (unless otherwise stated) Parameter Rise Time(1) Fall Time(1) Symbol Conditions Min. Max. Units TR 0.8 to 2.0V 0.10 1.0 nS 0.10 1.0 nS 45 55 % 450 pS TF 2.0 to 0.8V Cycle(1) DT VTH = VDD/2 Jitter (Cycle-Cycle) TJIT QA: DIV_SEL A = 0 Duty Typ. QA: DIV_SEL A = 1 200 QB Output 200 QC(0:1) Outputs 300 QD(0:4) Outputs 375 Note: 1. Guaranteed by design, not subject to 100% production testing. REV. 1.0.0 1/9/01 5 PRODUCT SPECIFICATION FMS7951 Parameter Measurement Information Duty Cycle (DT) T1 T2 DT = 1.5V 1.5V 1.5V T2 x 100 T1 Rise/Fall Time (TR/TF) 2.0V 2.0V 0.8V Output 3.3V 0.8V 0V TR TF Output to Output Skew (TSK1) 1.5V Q0 1.5V Any Output TSK1 Input to Output Delay (TSK2) 1.5V TCLK 1.5V FBIN TSK2 PECL_CLK PECL_CLK 6 REV. 1.0.0 1/9/01 FMS7951 PRODUCT SPECIFICATION Mechanical Dimensions 32-Pin LQFP Inches Symbol A A1 A2 B C D/E D1/E1 e L N ND α ccc Millimeters Min. Max. Min. Max. – 0.063 0.006 0.057 – 1.60 0.15 0.002 0.053 0.012 0.018 – 0.004 0.354 BSC 0.276 BSC 0.032 BSC 0.018 0.030 32 8 0° 7° – 0.004 0.05 1.35 1.45 0.30 0.45 – 0.10 9.00 BSC 7.00 BSC 0.800 BSC 0.45 0.75 32 8 0° 7° – 0.10 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. 3. Pin 1 identifier is optional. 4. Dimension N: number of terminals. 5. Dimension ND: Number of terminals per package edge. 7 6. "L" is the length of terminal for soldering to a substrate. 7. "B" includes lead finish thickness. 2 6 4 5 D D1 e PIN 1 E E1 IDENTIFIER C L α .039" Ref (1.00mm) See Lead Detail A Base Plane A2 B A1 Seating Plane -CLEAD COPLANARITY ccc REV. 1.0.0 1/9/01 C 7 PRODUCT SPECIFICATION FMS7951 Ordering Information Product Number FMS7951KWC FMS7951KWCX Package Description Package Marking LQFP-32 7951KWC LQFP-32 w/T+R 7951KWC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 1/9/01 0.0m 003 Stock#DS3007951 2000 Fairchild Semiconductor Corporation