FAIRCHILD 100325SC

Revised August 2000
100325
Low Power Hex ECL-to-TTL Translator
General Description
Features
The 100325 is a hex translator for converting F100K logic
levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential
receiver. An internal reference voltage generator provides
VBB for single-ended operation, or for use in Schmitt trigger
applications. All inputs have 50kΩ pull-down resistors.
When the inputs are either unconnected or at the same
potential the outputs will go LOW.
■ Pin/function compatible with 100125
When used in single-ended operation the apparent input
threshold of the true inputs is 20mV to 40mV higher (positive) than the threshold of the complementary inputs. The
VEE and VTTL power may be applied in either order.
■ Meets 100125 AC specifications
■ 50% power reduction of the 100125
■ Differential inputs with built in offset
■ Standard FAST outputs
■ 2000V ESD protection
■ −4.2V to −5.7V operating range
■ Available to industrial grade temperature range
Ordering Code:
Order Number
Package Number
Package Description
100325SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100325PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100325QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100325QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Pin Descriptions
Pin Names
Description
D0–D5
Data Inputs
D0–D5
Inverting Data Inputs
Q0–Q5
Data Outputs
FAST is a registered trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS009879
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100325 Low Power Hex ECL-to-TTL Translator
July 1988
100325
Truth Table
Logic Diagram
Inputs
Outputs
Dn
Dn
L
H
L
H
L
H
Qn
L
L
L
H
H
L
OPEN
OPEN
L
VEE
VEE
L
L
VBB
L
H
VBB
H
VBB
L
H
VBB
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
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Recommended Operating
Conditions
−65°C to +150 °C
Storage Temperature (TSTG)
+150 °C
Maximum Junction Temperature (TJ)
VEE Pin Potential to Ground Pin
−7.0V to +0.5V
VTTL Pin Potential to Ground Pin
−0.5V to +6.0V
Case Temperature (TC)
0°C to +85°C
Commercial
−40°C to +85°C
Industrial
VEE to +0.5V
Input Voltage (DC)
100325
Absolute Maximum Ratings(Note 1)
−5.7V to −4.2V
Supply Voltage (VEE)
Voltage Applied to Output
in HIGH State (with VCC = 0V)
−0.5V to VCC
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
≥2000V
ESD (Note 2)
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to 5.5V, TC = 0°C to +85°C (Note 3)
Symbol
Parameter
VBB
Output Reference Voltage
VIH
Single-Ended Input
HIGH Voltage
VIL
Single-Ended Input
LOW Voltage
Min
Typ
Max
Units
−1380
−1320
−1260
mV
−1165
−870
mV
−1830
−1475
mV
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VDIFF
Input Voltage Differential
150
VCM
Common Mode Voltage
VCC − 2.0
IIH
Input HIGH Current
2.5
0.5
Conditions
IVBB = −2.1 mA
Guaranteed HIGH Signal for All Inputs
(with One Input Tied to VBB)
Guaranteed LOW Signal for All Inputs
(with One Input Tied to VBB)
V
IOH = −2.0 mA
VIN = VIH (Max)
V
IOL = 20 mA
or VIL (Min)
mV
VCC − 0.5
V
350
µA
Required for Full Output Swing
VIN = VIH (Max), D0–D5 = VBB,
D0–D5 = VIL (Min)
IIL
Input LOW Current
IOS
Output Short-Circuit Current
−150
IEE
VEE Power Supply Current
−37
ITTL
VTTL Power Supply Current
µA
VIN = VIL (Min), D0–D5 = VBB
−60
mA
VOUT = GND (Note 4)
−27
−17
mA
D0–D5 = VBB
45
65
mA
D0–D5 = VBB
0.5
Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
Note 4: Test one output at a time.
DIP AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to +5.5V
TC = 0°C
Symbol
Parameter
Min
Max
tPLH
Propagation Delay
tPHL
Data to Output
tPLH
Propagation Delay
tPHL
Data to Output
TC = +25°C
TC = +85°C
Min
Max
Min
Max
Units
0.80
3.50
0.90
3.70
1.00
4.00
ns
1.60
4.30
1.70
4.50
1.80
4.80
ns
3
Conditions
CL = 15 pF
Figures 1, 2
CL = 50 pF
Figures 1, 3
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100325
Commercial Version (Continued)
SOIC and PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to +5.5V
TC = 0°C
Symbol
Parameter
Min
Max
tPLH
Propagation Delay
tPHL
Data to Output
tPLH
Propagation Delay
tPHL
Data to Output
tOSHL
Maximum Skew Common Edge
Output-to-Output Variation
TC = +25°C
TC = +85°C
Min
Max
Min
Max
Units
0.80
3.30
0.90
3.50
1.00
3.80
ns
1.60
4.10
1.70
4.30
1.80
4.60
ns
Conditions
CL = 15 pF
Figures 1, 2
CL = 50 pF
Figures 1, 3
PLCC Only
0.65
0.65
0.65
ns
(Note 5)
0.65
0.65
0.65
ns
(Note 5)
2.20
2.20
2.20
ns
(Note 5)
2.10
2.10
2.10
ns
Data to Output Path
tOSLH
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
Data to Output Path
tOST
Maximum Skew Opposite Edge
Output-to-Output Variation
PLCC Only
Data to Output Path
tPS
Maximum Skew
Pin (Signal) Transition Variation
PLCC Only
(Note 5)
Data to Output Path
Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
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100325
Industrial Version
PLCC DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = GND, TC = −40°C to +85°C (Note 6)
TC = 0°C to +85°C
TC = −40°C
Symbol
Parameter
Min
Max
Min
Max
VBB
Output Reference Voltage
VIH
Single-Ended Input
HIGH Voltage
VIL
Single-Ended Input
LOW Voltage
−1395
−1255
−1380
−1260
Units
mV
−1170
−870
−1165
−870
mV
−1830
−1480
−1830
−1475
mV
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VDIFF
Input Voltage Differential
VCM
Common Mode Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
IOS
Output Short-Circuit Current
−150
−60
−150
IEE
VEE Power Supply Current
−37
−15
−37
ITTL
VTTL Power Supply Current
2.5
2.5
0.5
0.5
150
150
450
IVBB = −2.1 mA
Guaranteed HIGH Signal for All Inputs
(with One Input Tied to VBB)
Guaranteed LOW Signal for All Inputs
(with One Input Tied to VBB)
V
IOH = −2.0 mA
VIN = VIH (Max)
V
IOL = 20 mA
or VIL (Min)
mV
VCC − 2.0 VCC − 0.5 VCC − 2.0 VCC − 0.5
Conditions
Required for Full Output Swing
V
µA
350
VIN = VIH (Max), D0–D5 = VBB,
D0–D5 = VIL (Min)
0.5
µA
VIN = VIL (Min), D0–D5 = VBB
−60
mA
VOUT = GND (Note 7)
−17
mA
D0–D5 = VBB
65
mA
D0–D5 = VBB
0.5
65
Note 6: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
Note 7: Test one output at a time.
PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to +5.5V
Symbol
Parameter
tPLH
Propagation Delay
tPHL
Data to Output
tPLH
Propagation Delay
tPHL
Data to Output
TC = −40°C
TC = +25°C
TC = +85°C
Min
Max
Min
Max
Min
Max
0.80
3.30
0.90
3.50
1.00
3.80
1.60
4.10
1.70
4.30
1.80
4.60
Units
ns
ns
Conditions
CL = 15 pF
Figures 1, 2
CL = 50 pF
Figures 1, 3
Switching Waveform
FIGURE 1. Propagation Delay
5
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100325
Test Circuits
Note:
•
VCC = 0V, VEE = −4.5V, VTTL = +5V
•
L1 and L2 = equal length 50Ω impedance lines
•
RT = 50Ω terminator internal to scope
•
Decoupling 0.1 µF from GND to VCC, VEE and VTTL
•
All unused outputs are loaded with 500Ω to GND
•
CL = Fixture and stray capacitance = 15 pF
FIGURE 2. AC Test Circuit for 15 pF Loading
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100325
Test Circuits
(Continued)
Note:
•
VCC = 0V, V EE = −4.5V, VTTL = +5V
•
L1 and L2 = equal length 50Ω impedance lines
•
RT = 50Ω terminator internal to scope
•
Decoupling 0.1 µF from GND to VCC, VEE and VTTL
•
All unused outputs are loaded with 500Ω to GND
•
CL = Fixture and stray capacitance = 50 pF
FIGURE 3. AC Test Circuit for 50 pF Loading
7
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100325
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Package Number N24E
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100325 Low Power Hex ECL-to-TTL Translator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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