60A Exposed Top Integrated PowIRstage® FEATURES DESCRIPTION Peak efficiency up to 95% at 1.2V Integrated driver, control MOSFET, synchronous MOSFET and Schottky diode Input voltage (VIN) operating range up to 15V Output voltage range from 0.25V up to 3.3 Output current capability of 60A DC Operation up to 1.0MHz The IR3575 exposed-top integrated PowIRstage® is a synchronous buck gate driver co-packed with a control MOSFET and a synchronous MOSFET with integrated Schottky diode. It is optimized internally for PCB layout, heat transfer and driver/MOSFET timing. Custom designed gate driver and MOSFET combination enables higher efficiency at lower output voltages required by cutting edge CPU, GPU and DDR memory designs. Up to 1.0MHz switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading efficiency. The IR3575’s superior efficiency enables smallest size and lower solution cost. The IR3575 PCB footprint is compatible with the IR3576 (50A). Integrated current sense amplifier VCC under voltage lockout Thermal flag Body-Braking™ load transient support Diode-emulation high efficiency mode Compatible with 3.3V PWM logic and VCC tolerant Compliant with Intel DrMOS V4.0 PCB footprint compatible with IR3576 Enhanced top side cooling through exposed pad Small 6mm x 6mm x 0.65mm PQFN package Lead free RoHS compliant package APPLICATIONS Integrated current sense amplifier achieves superior current sense accuracy and signal to noise ratio vs. best-inclass controller based Inductor DCR sense methods. The IR3575 incorporates the Body-Braking™ feature which enables reduction of output capacitors and is activated quickly. Synchronous diode emulation mode in the IR3575 removes the zero-current detection burden from the PWM controller and increases system light-load efficiency. High current, low profile DC-DC converters BASIC APPLICATION VIN 4.5V to 7V VIN 4.5V to 15V BOOST PHSFLT# PHSFLT# SW PWM PWM BBRK# BBRK# REFIN REFIN CSIN+ IOUT IOUT CSIN- LGND PGND VOUT Power Loss (W) VCC IR3575 95 20 93 18 91 16 89 14 87 12 85 10 83 8 81 6 79 4 77 2 75 0 0 5 10 15 20 25 30 35 40 45 50 55 60 Output Current (A) Figure 1: IR3575 Basic Application Circuit 1 June 20, 2012 | FINAL DATASHEET | V1.1 Figure 2: Typical IR3575 Efficiency & Power Loss (See Note 2 on Page 8) Power Loss (W) The IR3575 is optimized specifically for CPU core power delivery in server applications. The ability to meet the stringent requirements of the server market also makes the IR3575 ideally suited to powering GPU and DDR memory designs and other high current applications. Voltage Regulators for CPUs, GPUs, and DDR memory arrays VCC IR3575 60A Exposed Top Integrated PowIRstage® IR3575 PINOUT DIAGRAM ORDERING INFORMATION Package Tape & Reel Qty Part Number PQFN, 32 Lead 6mm x 6mm 3000 IR3575MTRPBF Figure 3: IR3575 Pin Diagram, Top View TYPICAL APPLICATION DIAGRAM VCC 4.5V to 7V C3 1uF R1 10k PHSFLT# PWM BBRK# Optional for diode emulation setup REFIN C8 1nF IR3575 25 PHSFLT# 26 PWM 27 BBRK# C9 22nF 28 LGND 29 REFIN 30 IOUT 3 18-23 VCC VIN C1 0.1uF BOOST Gate Drivers and Current Sense Amplifier 24 C5 0.22uF 31 1 No Connect R2 2.49k CSIN+ 2 Figure 4: Application Circuit with Current Sense Amplifier 2 June 20, 2012 | FINAL DATASHEET | V1.1 VIN 4.5V to 15V C6 22uF C7 470uF VOUT 6-15 PGND 16, 17 PGND 4 CSIN- L1 150nH SW IOUT TGND C2 10uF x 2 C4 0.22uF 60A Exposed Top Integrated PowIRstage® IR3575 TYPICAL APPLICATION DIAGRAM (CONTINUED) VCC 4.5V to 7V C3 0.1uF R1 10k IR3575 PHSFLT# PWM BBRK# 25 PHSFLT# 26 PWM 27 BBRK# 28 LGND 29 REFIN 30 IOUT 3 18-23 VCC VIN C1 0.1uF BOOST Gate Drivers and Current Sense Amplifier 24 C2 10uF x 2 C5 0.22uF L1 150nH CSIN- C6 22uF SW C7 470uF VOUT 6-15 R2 2.49k PGND 16, 17 PGND 4 TGND VIN 4.5V to 15V C4 0.22uF CS+ CS- CSIN+ 1 31 No Connect 2 Figure 5: Application Circuit without Current Sense Amplifier FUNCTIONAL BLOCK DIAGRAM BOOST VIN VIN VIN VIN VIN VIN 24 18 19 20 21 22 23 IR3575 VCC 3 VCC 3.3V 200k BBRK# 27 S Power-on Reset (POR), 3.3V Reference, and Dead-time Control Q R POR 3.3V PWM 26 PHSFLT# 25 LGND 28 IOUT 30 REFIN 29 MOSFET & Thermal Detection Driver Diode Emulation Comparator - 5 32 GATEL GATEL Figure 6: IR3575 Functional Block Diagram 3 15 SW + 31 June 20, 2012 | FINAL DATASHEET | V1.1 SW 14 SW Driver 4 9 13 SW VCC 2 SW 12 SW 18k Offset +- 1 SW 8 11 SW - CSIN- CSIN+ PGND TGND SW 7 10 SW + Current Sense Amplifier 6 16 17 PGND PGND 60A Exposed Top Integrated PowIRstage® IR3575 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 CSIN- Inverting input to the current sense amplifier. Connect to LGND if the current sense amplifier is not used. 2 CSIN+ Non-Inverting input to the current sense amplifier. Connect to LGND if the current sense amplifier is not used. 3 VCC Bias voltage for control logic. Connect a minimum 1uF cap between VCC and PGND (pin 4) if current sense amplifier is used. Connect a minimum 0.1uF cap between VCC and PGND (pin 4) if current sense amplifier is not used. 4, 16, 17 PGND Power ground of MOSFET driver and the synchronous MOSFET. MOSFET driver signal is referenced to this pin. 5, 32 GATEL Low-side MOSFET driver pins that can be connected to a test point in order to observe the waveform. 6 – 15 SW Switch node of synchronous buck converter. VIN High current input voltage connection. Recommended operating range is 4.5V to 15V. Connect at least two 10uF 1206 ceramic capacitors and a 0.1uF 0402 ceramic capacitor. Place the capacitors as close as possible to VIN pins and PGND pins (16-17). The 0.1uF 0402 capacitor should be on the same side of the PCB as the IR3575. 24 BOOST Bootstrap capacitor connection. The bootstrap capacitor provides the charge to turn on the control MOSFET. Connect a minimum 0.22µF capacitor from BOOST to SW pin. Place the capacitor as close to BOOST pin as possible and minimize the parasitic inductance of the connection from the capacitor to SW pin. 25 PHSFLT# Open drain output of the phase fault circuits. Connect to an external pull-up resistor. Output is low when a MOSFET fault or over temperature condition is detected. PWM 3.3V logic level tri-state PWM input and 7V tolerant. “High” turns the control MOSFET on, and “Low” turns the synchronous MOSFET on. “Tri-state” turns both MOSFETs off in Body-Braking® mode. In diode emulation mode, “Tri-state” activates internal diode emulation control. See “PWM Tri-state Input” Section for further details about the PWM Tri-State functions. 27 BBRK# 3.3V logic level input and 7V tolerant with internal weak pull-up to 3.3V. Logic low disables both MOSFETs. Pull up to VCC if Body-Braking® is not used. Pulling BBRK# low at least 20ns after VCC passes its UVLO threshold selects internal diode emulation control. See “Body-Braking® Mode” Section for further details. 28 LGND Signal ground. Driver control logic, analog circuits and IC substrate are referenced to this pin. 29 REFIN Reference voltage input from the PWM controller. IOUT signal is referenced to the voltage on this pin. Connect to LGND if the current sense amplifier is not used. 30 IOUT Current output signal. Voltage on this pin is equal to V(REFIN) + 32.5 * [V(CSIN+) – V(CSIN-)]. Float this pin if the current sense amplifier is not used. 31 TGND This pin is connected to internal power and signal ground of the driver. For best performance of the current sense amplifier, TGND must be electrically isolated from Power Ground (PGND) and Signal Ground (LGND) in the PCB layout. Exposed Pad SW Exposed pad on top side of the package. Connect to a heat sink through insulated thermal material to improve the thermal performance of the package. 18 – 23 26 4 June 20, 2012 | FINAL DATASHEET | V1.1 60A Exposed Top Integrated PowIRstage® IR3575 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PIN Number PIN NAME VMAX VMIN ISOURCE ISINK 1 CSIN- VCC + 0.3V -0.3V 1mA 1mA 2 CSIN+ VCC + 0.3V -0.3V 1mA 3 VCC 8V -0.3V NA 4 PGND 0.3V 5, 32 GATEL VCC + 0.3V 15mA 1A for 100ns, 200mA DC 6-15 SW 2 25V 65A RMS 30A RMS 16, 17 PGND NA -0.3V -3V for 20ns, -0.3V DC -5V for 20ns, -0.3V DC NA 1mA 5A for 100ns, 200mA DC 15mA 1A for 100ns, 200mA DC 30A RMS 65A RMS 18-23 2 25V -0.3V VIN 5A RMS 25A RMS 5A for 100ns, 100mA DC 20mA 33V -0.3V PHSFLT# VCC + 0.3V -0.3V 1A for 100ns, 100mA DC 1mA 26 PWM VCC + 0.3V -0.3V 1mA 1mA 27 BBRK# VCC + 0.3V -0.3V 1mA 1mA 28 LGND 0.3V -0.3V 15mA 15mA 29 REFIN 3.5V -0.3V 1mA 1mA 30 IOUT VCC + 0.3V -0.3V 5mA 5mA 31 TGND 0.3V -0.3V NA NA 24 BOOST 25 1 Note: 1. Maximum BOOST – SW = 8V. 2. Maximum VIN – SW = 25V. 3. All the maximum voltage ratings are referenced to PGND (Pins 16 and 17). THERMAL INFORMATION Thermal Resistance, Junction to Top (θJC_TOP) 0.5 °C/W Thermal Resistance, Junction to PCB (pin 17) (θJC_PCB) 1.7 °C/W Thermal Resistance (θJA) 1 19.1 °C/W Maximum Operating Junction Temperature -40 to 150°C Maximum Storage Temperature Range -65°C to 150°C ESD rating HBM Class 1C JEDEC Standard MSL Rating 3 Reflow Temperature 260°C Note: 1. Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal conductivity test board in free air. Refer to International Rectifier Application Note AN-994 for details. 5 June 20, 2012 | FINAL DATASHEET | V1.1 60A Exposed Top Integrated PowIRstage® IR3575 ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN PARAMETER SYMBOL MIN MAX UNIT Recommended VIN Range VIN 4.5 15 V Recommended VCC Range VCC 4.5 7 V REFIN 0.25 VCC - 2.5 V Recommended Switching Frequency ƒSW 200 1000 kHz Recommended Operating Junction Temperature TJ -40 125 °C Recommended REFIN Range ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Efficiency IR3575 Peak Efficiency Note 1 η Note 2. See Figure 2. 94.5 % Note 3. See Figure 7. 93.5 % PWM Comparator PWM Input High Threshold VPWM_HIGH PWM Tri-state to High PWM Input Low Threshold VPWM_LOW PWM Tri-state to Low PWM Tri-state Float Voltage VPWM_TRI Hysteresis VPWM_HYS Tri-state Propagation Delay tPWM_DELAY PWM Floating Active to Tri-state or Tristate to Active, Note 1 PWM Tri-state to Low transition to GATEL >1V PWM Tri-state to High transition to GATEH >1V 2.5 V 0.8 V 1.2 1.65 2.1 V 65 76 100 mV 38 ns 18 ns PWM Sink Impedance RPWM_SINK 3.67 5.1 8.70 kΩ PWM Source Impedance RPWM_SOURCE 3.67 5.1 8.70 kΩ Internal Pull up Voltage VPWM_PULLUP VCC > UVLO 3.3 Minimum Pulse Width tPWM_MIN Note 1 41 58 ns V Current Sense Amplifier CSIN+/- Bias Current ICSIN_BIAS -100 0 100 nA CSIN+/- Bias Current Mismatch ICSIN_BIASMM -50 0 50 nA Calibrated Input Offset Voltage VCSIN_OFFSET Self-calibrated offset, 0.5V ≤ V(REFIN) ≤ 2.25V Gain GCS 0.5V ≤ V(REFIN) ≤ 2.25V fBW Unity Gain Bandwidth 6 June 20, 2012 | FINAL DATASHEET | V1.1 C(IOUT) = 10pF. Measure at IOUT. Note 1 ±450 µV 30.0 32.5 35.0 V/V 4.8 6.8 8.8 MHz 60A Exposed Top Integrated PowIRstage® PARAMETER SYMBOL CONDITIONS Slew Rate SR Differential Input Range VD_IN Common Mode Input Range VC_IN Output Impedance (IOUT) RCS_OUT IOUT Sink Current ICS_SINK Driving external 3 kΩ Input Offset Voltage VIN_OFFSET Leading Edge Blanking Time Negative Current Time-Out MIN TYP IR3575 MAX 6 0.8V ≤ V(REFIN) ≤ 2.25V, UNIT V/µs -10 25 mV 0 VCC2.5 V 62 200 Ω 0.5 0.8 1.1 mA Note 3 -12 -3 3 mV tBLANK V(GATEL)>1V Starts Timer 50 150 200 ns tNC_TOUT PWM = Tri-State, V(SW) ≤ -10mV 12 28 46 µs Diode Emulation Mode Comparator Digital Input – BBRK# Input voltage high VBBRK#_IH 2.0 Input voltage low VBBRK#_IL Internal Pull Up Resistance RBBRK#_PULLUP VCC > UVLO Internal Pull Up Voltage VBBRK#_PULLUP VCC > UVLO 69 V 200 0.8 V 338 kΩ 3.3 V Digital Output – PHSFLT# Output voltage high VPHASFLT#_OH VCC V Output voltage low VPHASFLT#_OL 4mA 150 300 mV Input current IPHASFLT#_IN V(PHSFLT#) = 5.5V 0 1 µA Control MOSFET Short Threshold VCM_SHORT Measure from SW to PGND Synchronous MOSFET Short Threshold VSM_SHORT Measure from SW to PGND 150 200 250 mV Synchronous MOSFET Open Threshold VSM_OPEN Measure from SW to PGND -250 -200 -150 mV Propagation Delay tPROP PWM High to Low Cycles 15 Cycle Rising Threshold TRISE PHSFLT# Drives Low, Note 1 160 °C Falling Threshold TFALL Note 1 135 °C Phase Fault Detection 3.3 V Thermal Flag Bootstrap Diode Forward Voltage VFWD I(BOOST) = 30mA, VCC = 6.8V 360 520 920 mV VCC Under Voltage Lockout Start Threshold VVCC_START 3.3 3.7 4.1 V Stop Threshold VVCC_STOP 3.0 3.4 3.8 V Hysteresis VVCC_HYS 0.2 0.3 0.4 V General 7 June 20, 2012 | FINAL DATASHEET | V1.1 60A Exposed Top Integrated PowIRstage® PARAMETER SYMBOL CONDITIONS VCC Supply Current IVCC VCC = 4.5V to 7V VIN Supply Leakage Current IVIN VIN = 20V, 125C, V(PWM) = Tri-State BOOST Supply Current IBOOST 4.75V < V(BOOST)-V(SW) < 8V REFIN Bias Current IREFIN SW Floating Voltage VSW_FLOAT SW Pull Down Resistance RSW_PULLDOWN IR3575 MIN TYP MAX UNIT 4 8 12 mA 1 µA 0.5 1.5 3.0 mA -1.5 0 1 µA V(PWM) = Tri-State 0.2 0.4 V BBRK# is Low or VCC = 0V 18 kΩ Notes 1. Guaranteed by design but not tested in production 2. VIN=12V, VOUT=1.2V, ƒSW = 300kHz, L=210nH (0.2mΩ), VCC=6.8V, CIN=47uF x 4, COUT =470uF x3, 400LFM airflow, no heat sink, 25°C ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included. 3. VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, CIN=47uF x 4, COUT =470uF x3, no airflow, no heat sink, 25°C ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included. 8 June 20, 2012 | FINAL DATASHEET | V1.1 60A Exposed Top Integrated PowIRstage® IR3575 TYPICAL OPERATING CHARACTERISTICS Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise. 94 1.15 2.25 1.10 1.50 1.05 0.75 1.00 0.00 0.95 -0.75 0.90 -1.50 92 91 Normalized Power Loss (W) 90 Efficiency (%) 89 88 87 86 85 84 83 82 Case Temperature Adjustment (°C) 93 81 80 0.85 5 10 15 20 25 30 35 40 45 50 55 -2.25 5 6 7 8 9 Output Current (A) 11 12 13 14 15 Input Voltage (V) Figure 7: Typical IR3575 Efficiency Figure 10: Normalized Power Loss vs. Input Voltage 10 1.40 6.00 1.35 5.25 8 1.30 4.50 7 1.25 3.75 1.20 3.00 1.15 2.25 1.10 1.50 1.05 0.75 1.00 0.00 0.95 -0.75 0.90 -1.50 Normalized Power Loss (W) 9 Power Loss (W) 10 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 45 50 55 Output Current (A) Figure 8: Typical IR3575 Power Loss (To be added) Figure 9: Safe Operating Area, TCASE <= 125°C 9 June 20, 2012 | FINAL DATASHEET | V1.1 0.85 -2.25 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 Output Voltage (V) Figure 11: Normalized Power Loss vs. Output Voltage Case Temperature Adjustment (°C) 0 1.40 6.00 1.35 5.25 1.30 4.50 1.25 3.75 1.20 3.00 1.15 2.25 1.10 1.50 1.05 0.75 1.00 0.00 0.95 -0.75 0.90 -1.50 0.85 200 Case Temperature Adjustment (°C) Normalized Power Loss (W) 60A Exposed Top Integrated PowIRstage® -2.25 300 400 500 600 700 800 900 1000 Switching Frequency (kHz) Figure 12: Normalized Power Loss vs. Switching Frequency 10 June 20, 2012 | FINAL DATASHEET | V1.1 IR3575 60A Exposed Top Integrated PowIRstage® IR3575 TYPICAL OPERATING CHARACTERISTICS (CONTINUED) 1.20 3.00 1.15 2.25 1.10 1.50 1.05 0.75 1.00 0.00 0.95 -0.75 0.90 -1.50 0.85 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75 PWM 5V/div Case Temperature Adjustment (°C) Normalized Power Loss (W) Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise. SW 5V/div GATEL 10V/div -2.25 7.00 VCC Voltage (V) 400ns/div 1.15 2.25 1.10 1.50 1.05 0.75 1.00 0.00 0.95 -0.75 0.90 -1.50 0.85 120 130 140 150 160 170 180 190 200 Figure 16: Switching Waveform, IOUT = 0A PWM 5V/div Case Temperature Adjustment (°C) Normalized Power Loss (W) Figure 13: Normalized Power Loss vs. VCC Voltage SW 5V/div GATEL 10V/div -2.25 210 Output Inductor (nH) 400ns/div Figure 14: Power Loss vs. Output Inductor Figure 17: Switching Waveform, IOUT = 50A 80 PWM 2V/div VCC Current (mA) 70 60 Vcc=6.8V 50 Vcc=5V 40 30 SW 5V/div 20 10 0 200 300 400 500 600 700 800 900 1000 fsw (kHz) Figure 15: VCC Current vs. Switching Frequency 11 June 20, 2012 | FINAL DATASHEET | V1.1 40ns/div Figure 18: PWM to SW Delays, IOUT = 10A 60A Exposed Top Integrated PowIRstage® IR3575 TYPICAL OPERATING CHARACTERISTICS (CONTINUED) Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise. PWM 2V/div BBRK# 5V/div PWM 5V/div SW 5V/div GATEL 5V/div GATEL 10V/div 40ns/div 400ns/div Figure 19: Body-BrakingTM Delays Figure 22: Diode Emulation Mode, IOUT = 3A PWM 2V/div PWM 2V/div SW 5V/div SW 5V/div GAETL 10V/div 100ns/div 400ns/div Figure 20: PWM Tri-state Delays, IOUT = 10A Figure 23: Body-Braking TM Mode, IOUT = 3A VCC 2V/div PWM 2V/div BBRK# 1V/div SW 5V/div SW 10V/div 100ns/div Figure 21: PWM Tri-state Delays, IOUT = 10A 12 June 20, 2012 | FINAL DATASHEET | V1.1 2ms/div Figure 24: Diode Emulation Setup through BBRK# Capacitor 60A Exposed Top Integrated PowIRstage® IR3575 TYPICAL OPERATING CHARACTERISTICS (CONTINUED) Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise. V(IOUT)V(REFIN) 0.2V/div VCC 2V/div IL 10A/div BBRK# 2V/div SW 20V/div 2us/div 4ms/div Figure 25: Diode Emulation Setup through BBRK# Input Figure 28: Current Sense Amplifier Output, IOUT = 0A V(IOUT)V(REFIN) 0.2V/div VCC 2V/div IL 10A/div BBRK# 2V/div SW 20V/div 2us/div 4ms/div Figure 26: Diode Emulation Setup through BBRK# Input Figure 29: Current Sense Amplifier Output, IOUT = 20A 0.60 0.55 V(IOUT)V(REFIN) 0.2V/div 0.50 0.45 IOUT-REFIN (V) 0.40 0.35 IL 10A/div 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 5 10 15 20 25 30 35 40 45 SW 20V/div 50 Output Current (A) 2us/div Figure 27: Current Sense Amplifier Output vs. Current 13 June 20, 2012 | FINAL DATASHEET | V1.1 Figure 30: Current Sense Amplifier Output, IOUT = 40A 60A Exposed Top Integrated PowIRstage® THEORY OF OPERATION DESCRIPTION The IR3575 exposed-top PowIRstage® is a synchronous buck driver with co-packed MOSFETs with integrated Schottky diode, which provides system designers with ease of use and flexibility required in cutting edge CPU, GPU and DDR memory power delivery designs and other highcurrent low-profile applications. The IR3575 is designed to work with a PWM controller. It incorporates a continuously self-calibrated current sense amplifier, optimized for use with inductor DCR sensing. The current sense amplifier provides signal gain and noise immunity, supplying multiphase systems with a superior design toolbox for programmed impedance designs. The IR3575 provides a phase fault signal capable of detecting open or shorted MOSFETs, or an overtemperature condition in the vicinity of the power stage. IR3575 set. PWM input in tri-state will activate a synchronous diode emulation feature allowing designers to maximize system efficiency at light loads without compromising transient performance. BODY-BRAKING® MODE International Rectifier’s Body-Braking® is a operation mode in which two MOSFETs are turned off. When the synchronous MOSFET is off, the higher voltage across the Shottky diode in parallel helps discharging the inductor current faster, which reduces the output voltage overshoot. The Body-Braking® can be used either to enhance transient response of the converter after load release or to provide a high impedance output. There are two ways to place the IR3575 in Body-Braking® mode, either controlling the BBRK# pin directly or through a PWM tri-state signal. Both control signals are usually from the PWM controller. The IR3575 accepts an active low Body-Braking® input which disables both MOSFETs to enhance transient performance or provide a high impedance output. Pulling BBRK# low forces the IR3575 into Body-Braking® mode rapidly, which is usually used to enhance converter transient response after load release, as shown in Figure 19. Releasing BBRK# forces the IR3575 out of BodyBraking® mode quickly. The IR3575 provides diode emulation feature which avoids negative current in the synchronous MOSFET and improves light load efficiency. The BBRK# low turns off both MOSFETs and therefore can also be used to disable/enable a converter. The IR3575 PWM input is compatible with 3.3V logic signal and 7V tolerant. It accepts 3-level PWM input signals with tri-state. PWM TRI-STATE INPUT The IR3575 PWM accepts 3-level input signals. When PWM input is high, the synchronous MOSFET is turned off and the control MOSFET is turned on. When PWM input is low, control MOSFET is turned off and synchronous MOSFET is turned on. Figures 16-18 show the PWM input and the corresponding SW and GATEL output of the IR3575. If PWM pin is floated , the built-in resistors pull the PWM pin into a tri-state region centered around 1.65V. When PWM input is in tri-state, two operation modes can be selected by controlling BBRK# input. If the BBRK# input is always high, the default operation mode is BodyBraking®, in which both MOSFETs will be turned off when the PWM input is in tri-state. If the BBRK# input has been pulled low for at least 20ns after the VCC passes its UVLO threshold during power up, the diode emulation mode is 14 June 20, 2012 | FINAL DATASHEET | V1.1 If the BBRK# input is always high, the Body-Braking® is activated when the PWM input enters the tri-state region, as shown in Figures 20 and 21. Comparing to pulling down the BBRK# pin directly, the Body-Braking® response to PWM tri-state signal is slower due to the hold-off time created by the PWM pin parasitic capacitor with the pullup and pull-down resistors of PWM pin. For better performance, no more than 100pF parasitic capacitive load should be present on the PWM line of IR3575. SYNCHRONOUS DIODE EMULATION MODE An additional feature of the IR3575 is the synchronous diode emulation mode. This function enables increased efficiency by preventing negative inductor current from flowing in the synchronous MOSFET. As shown in Figure 22, when the PWM input enters the tristate region the control MOSFET is turned off first, and the synchronous MOSFET is initially turned on and then is turned off when the output current reaches zero. If the sensed output current does not reach zero within a set amount of time the gate driver will assume that the output 60A Exposed Top Integrated PowIRstage® IR3575 is de-biased and turn off the synchronous MOSFET, allowing the switch node to float. number of consecutive faults the phase fault signal is asserted. This is in contrast to the Body-Braking® mode shown in Figure 23, where GATEL follows PWM input. The Schottky diode in parallel with the synchronous MOSFET conducts for a longer period of time and therefore lowers the light load efficiency. Thermal flag circuit monitors the temperature of the IR3575. If the temperature goes above a threshold (160°C typical) the PHSFLT# pin is pulled low after a maximum delay of 100us. The zero current detection circuit in the IR3575 is independent of the current sense amplifier and therefore still functions even if the current sense amplifier is not used. As shown in Figure 6, an offset is added to the diode emulation comparator so that a slightly positive output current in the inductor and synchronous MOSFET is treated as zero current to accommodate propagation delays, preventing any negative current flowing in the synchronous MOSFET. This causes the Schottky diode in parallel with the synchronous MOSFET to conduct before the inductor current actually reaches zero, and the conduction time increases with inductance of the output inductor. To set the IR3575 in diode emulation mode, the BBRK# pin must be toggled low at least once after the VCC passes its UVLO threshold during power up. One simple way is to use the internal BBRK# pull-up resistor (200kΩ typical) with an external capacitor from BBRK# pin to LGND, as shown in Figure 4. To ensure the diode emulation mode is properly set, the BBRK# voltage should be lower than 0.8V when the VCC voltage passes its UVLO threshold (3.3V minimum and 3.7V typical), as shown in Figure 24. A digital signal from the PWM controller can also be used to set the diode emulation mode. The BBRK# signal can either be pulled low for at least 20ns after the VCC passes its UVLO threshold, as shown in Figure 25, or be pulled low before VCC power up and then released after the VCC passes its UVLO threshold, as shown in Figure 26. Once the diode emulation mode is set, it cannot be reset until the VCC power is recycled. The PHSFLT# pin can be pulled low by either the phase fault circuit or the thermal flag circuit. The phase fault signal could be used to turn off the AC/DC converter or blow a fuse to disconnect the DC/DC converter input from the supply. If PHSFLT# is not used it can be floated or connected to LGND. LOSSLESS AVERAGE INDUCTOR CURRENT SENSING Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 31. IR3575 VIN VIN CIN + vL - L SW RL iL RCS Current Sense Amplifier CCS VOUT COUT + vCS + CSIN+ - CSIN- Figure 31: Inductor current sensing The equation of the current sensing network is as follows. PHASE FAULT AND THERMAL FLAG OUTPUT The phase fault circuit looks at the switch node with respect to ground to determine whether there is a defective MOSFET in the phase. The output of the phase fault signal is high during normal operation and is pulled low when there is a fault. Each driver monitors the MOSFET it drives. If the switch node is less than a certain voltage above ground when the PWM signal goes low or if the switch node is a certain voltage above ground when the PWM signal rises, this gives a fault signal. If there are a 15 June 20, 2012 | FINAL DATASHEET | V1.1 L 1 s 1 RL vCS ( s ) vL ( s ) iL ( s ) RL 1 sRCS CCS 1 sRCS CCS iL ( s) RL when L RL RCSCCS Usually the resistor RCS and capacitor CCS are chosen so that the time constant of RCS and CCS equals the inductor time 60A Exposed Top Integrated PowIRstage® IR3575 constant, which is the inductance L over the inductor DCR (RL). If the two time constants match, the voltage across CCS is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. If the IR3575 current sense amplifier is required, connect its output IOUT and the reference voltage REFIN to the PWM controller and connect the inductor sense circuit as shown in Figure 4. If the current sense amplifier is not needed, tie CSIN+, CSIN- and REFIN pins to LGND and float IOUT pin, as shown in Figure 5. The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. This is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). DESIGN PROCEDURES POWER LOSS CALCULATION The single-phase IR3575 efficiency and power loss measurement circuit is shown in Figure 32. C3 1uF VCC IVCC CURRENT SENSE AMPLIFIER PHSFLT# BOOST PWM BBRK# C5 0.22uF C2 47uF x4 L1 150nH IOUT VOUT SW LGND REFIN CSIN+ IOUT PGND C7 1nF VIN C1 0.1uF x2 IR3575 R1 10k A high speed differential current sense amplifier is located in the IR3575, as shown in Figure 6. Its gain is nominally 32.5, and the inductor DCR increase with temperature is not compensated inside the IR3575. The current sense amplifier output IOUT is referenced to REFIN, which is usually connected to a reference voltage from the PWM controller. Figure 27 shows the differential voltage of V(IOUT) – V(REFIN) versus the inductor current and reflects the inductor DCR increase with temperature at higher current. IIN VIN VCC R2 2.49k C6 470uF x3 C4 0.22uF CSIN- VSW Figure 32: IR3575 Power Loss Measurement The IR3575 power loss is determined by, The current sense amplifier can accept positive differential input up to 25mV and negative input up to -10mV before clipping. The output of the current sense amplifier is summed with the reference voltage REFIN and sent to the IOUT pin. The REFIN voltage is to ensure at light loads there is enough output range to accommodate the negative current ripple shown in Figure 28. In a multiphase converter, the IOUT pins of all the phases can be tied together through resistors, and the IOUT voltage represents the average current through all the inductors and is used by the controller for adaptive voltage positioning. The input offset voltage is the primary source of error for the current signal. In order to obtain very accurate current signal, the current sense amplifier continuously calibrates itself, and the input offset of this amplifier is within +/450uV. This calibration algorithm can create a small ripple on IOUT with a frequency of fsw/128. 16 June 20, 2012 | FINAL DATASHEET | V1.1 PLOSS VIN I IN VCC IVCC VSW I OUT Where both MOSFET loss and the driver loss are included, but the PWM controller and the inductor losses are not included. Figure 7 shows the measured single-phase IR3575 efficiency under the default test conditions, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, and no air flow. The efficiency of an interleaved multiphase IR3575 converter is always higher than that of a single-phase under the same conditions due to the reduced input RMS current and more input/output capacitors. The measured single-phase IR3575 power loss under the same conditions is provided in Figure 8. 60A Exposed Top Integrated PowIRstage® If any of the application condition, i.e. input voltage, output voltage, switching frequency, VCC MOSFET driver voltage or inductance, is different from those of Figure 8, a set of normalized power loss curves should be used. Obtain the normalizing factors from Figure 10 to Figure 14 for the new application conditions; multiply these factors by the power loss obtained from Figure 8 for the required load current. As an example, the power loss calculation procedures under different conditions, VIN=10V, VOUT=1V, ƒSW = 300kHz, VCC=5V, L=210nH, VCC=5V, IOUT=40A, TAMBIENT = 25°C, no heat sink, and no air flow, are as follows. 1) Determine the power loss at 40A under the default test conditions of VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH, VCC=7V, TAMBIENT = 25°C, no heat sink, and no air flow. It is 4.8W from Figure 8. 2) Determine the input voltage normalizing factor with VIN=10V, which is 0.96 based on the dashed lines in Figure 10. 3) Determine the output voltage normalizing factor with VOUT=1V, which is 0.92 based on the dashed lines in Figure 11. 4) Determine the switching frequency normalizing factor with ƒSW = 300kHz, which is 0.98 based on the dashed lines in Figure 12. 5) Determine the VCC MOSFET drive voltage normalizing factor with VCC=5V, which is 1.16 based on the dashed lines in Figure 13. 6) Determine the inductance normalizing factor with L=210nH, which is 0.95 based on the dashed lines in Figure 14. 7) Multiply the power loss under the default conditions by the five normalizing factors to obtain the power loss under the new conditions, which is 4.8W x 0.96 x 0.92 x 0.98 x 1.16 x 0.95 = 4.58W. SAFE OPERATING AREA Figure 9 shows the IR3575 safe operating area with the case temperature controlled at or below 125°C. The test conditions are VIN=12V, VOUT=1.2V, ƒSW=400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 0°C to 90°C, no heat sink, and Airflow = 0LFM / 100LFM / 200LFM / 400LFM. 17 June 20, 2012 | FINAL DATASHEET | V1.1 IR3575 If any of the application condition, i.e. input voltage, output voltage, switching frequency, VCC MOSFET driver voltage, or inductance is different from those of Figure 9, a set of IR3575 case temperature adjustment curves should be used. Obtain the temperature deltas from Figure 10 to Figure 14 for the new application conditions; sum these deltas and then subtract from the IR3575 case temperature obtained from Figure 9 for the required load current. 8) From Figure 9, determine the highest ambient temperature at the required load current under the default conditions, which is 77°C at 40A with 0LFM airflow and the IR3575 case temperature of 125°C. 9) Determine the case temperature with VIN=10V, which is -0.6° based on the dashed lines in Figure 10. 10) Determine the case temperature with VOUT=1V, which is -1.2° based on the dashed lines in Figure 11. 11) Determine the case temperature with ƒSW = 300kHz, which is -0.3° based on the dashed lines in Figure 12. 12) Determine the case temperature with VCC = 5V, which is +2.4° based on the dashed lines in Figure 13. 13) Determine the case temperature with L=210nH, which is -0.8° based on the dashed lines in Figure 14. 14) Sum the case temperature adjustment from 9) to 13), -0.6° -1.2° -0.3° +2.4° -0.8° = -0.5°. Deduct the delta from the highest ambient temperature in step 8), 77°C - (-0.5°C) = 77.5°C. INDUCTOR CURRENT SENSING CAPACITOR CCS AND RESISTOR RCS If the IR3575 is used with inductor DCR sensing, care must be taken in the printed circuit board layout to make a Kelvin connection across the inductor DCR. The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS represents the inductor current. Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as follows. RCS L RL C CS 60A Exposed Top Integrated PowIRstage® INPUT CAPACITORS CVIN At least two 10uF 1206 ceramic capacitors and one 0.1uF 0402 ceramic capacitor are recommended for decoupling the VIN to PGND connection. The 0.1uF 0402 capacitor should be on the same side of the PCB as the IR3575 and next to the VIN and PGND pins. Adding additional capacitance and use of capacitors with lower ESR and mounted with low inductance routing will improve efficiency and reduce overall system noise, especially in single-phase designs or during high current operation. BOOTSTRAP CAPACITOR CBOOST A minimum of 0.22uF 0402 capacitor is required for the bootstrap circuit. A high temperature 0.22uF or greater value 0402 capacitor is recommended. It should be mounted on the same side of the PCB as the IR3575 and as close as possible to the BOOST pin. A low inductance routing of the SW pin connection to the other terminal of the bootstrap capacitor is strongly recommended. VCC DECOUPLING CAPACITOR CVCC A 0.1uF to 1uF ceramic decoupling capacitor is required at the VCC pin. It should be mounted on the same side of the PCB as the IR3575 and as close as possible to the VCC and PGND (pin 4). Low inductance routing between the VCC capacitor and the IR3575 pins is strongly recommended. BODY-BRAKING® FEATURE The BBRK# pin should be pulled up to VCC if the feature is not used by the PWM controller. Use of a small value resistor or a direct connection to VCC is recommended. MOUNTING OF HEAT SINKS Care should be taken in the mounting of heat sinks so as not to short-circuit nearby components. The VCC and Bootstrap capacitors are typically mounted on the same side of the PCB as the IR3575. The mounting height of these capacitors must be considered when selecting their package sizes. HIGH OUTPUT VOLTAGE DESIGN CONSIDERATIONS The IR3575 is capable of creating output voltages above the 3.3V recommended maximum output voltage as there are no restrictions inside the IR3575 on the duty cycle applied to the PWM pin. However if the current sense feature is required, the common mode range of the 18 June 20, 2012 | FINAL DATASHEET | V1.1 IR3575 current sense amplifier inputs must be considered. A violation of the current sense input common mode range may cause unexpected IR3575 behavior. Also the output current rating of the device will be reduced as the duty cycle increases. In very high duty cycle applications sufficient time must be provided for replenishment of the Bootstrap capacitor for the control MOSFET drive. LAYOUT EXAMPLE Contact International Rectifier for a layout example suitable for your specific application. 60A Exposed Top Integrated PowIRstage® IR3575 METAL AND COMPONENT PLACEMENT Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to prevent shorting. Center pad land length and width should be equal to maximum part pad length and width. Only 0.30mm diameter via shall be placed in the area of the power pad lands and connected to power planes to minimize the noise effect on the IC and to improve thermal performance. Lead land length should be equal to maximum part lead length +0.15 - 0.3 mm outboard extension and 0 to + 0.05mm inboard extension. The outboard extension ensures a large and visible toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. 30 29 28 27 26 25 24 23 22 21 20 1 19 2 3 4 18 5 31 17 32 16 6 7 8 9 10 11 12 13 14 15 Figure 33: Metal and component placement * Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format. 19 June 20, 2012 | FINAL DATASHEET | V1.1 60A Exposed Top Integrated PowIRstage® SOLDER RESIST The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist miss-alignment is a maximum of 0.05mm and it is recommended that the low power signal lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. The minimum solder resist width is 0.13mm typical. At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. The power land pads VIN, PGND, TGND and SW should be Solder Mask Defined (SMD). Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Figure 34: Solder resist * Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format. 20 June 20, 2012 | FINAL DATASHEET | V1.1 IR3575 60A Exposed Top Integrated PowIRstage® IR3575 STENCIL DESIGN The stencil apertures for the lead lands should be approximately 65% to 75% of the area of the lead lands depending on stencil thickness. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. The low power signal stencil lead land apertures should therefore be shortened in length to keep area ratio of 65% to 75% while centered on lead land. The power pads VIN, PGND, TGND and SW, land pad apertures should be approximately 65% to 75% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. Solder paste on large pads is broken down into small sections with a minimum gap of 0.2mm between allowing for out-gassing during solder reflow. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Figure 35: Stencil design * Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format. 21 June 20, 2012 | FINAL DATASHEET | V1.1 60A Exposed Top Integrated PowIRstage® MARKING INFORMATION Site/Date/Marking Code Lot Code 3575M ?YWW? xxxxx Figure 36: PQFN 6mm x 6mm PACKAGE INFORMATION Figure 37: PQFN 6mm x 6mm 22 June 20, 2012 | FINAL DATASHEET | V1.1 IR3575 60A Exposed Top Integrated PowIRstage® IR3575 Data and specifications subject to change without notice. This product will be designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com 23 June 20, 2012 | FINAL DATASHEET | V1.1