IRF IR3558

45A Integrated PowIRstage®
FEATURES
DESCRIPTION
 Peak efficiency up to 94.0% at 1.2V
 Integrated driver, control MOSFET, synchronous
MOSFET and Schottky diode
 Input voltage (VIN) operating range of 4.5V to 15V
 Separate LVCC and HVCC from 4.5V to 13.2V to
optimize converter efficiency
 Output current capability of 45A DC
 Switching frequency up to 1.0MHz
 Programmable thermal flag threshold from 70°C to
150°C
 5V VCC with under voltage lockout
 Low quiescent current
 Enable control
 Selectable regular 3.3V tri-state PWM logic or IR
Active Tri-Level (ATL) PWM logic
 PCB footprint compatible with most IR3551 pins
 Efficient dual sided cooling
The IR3558 integrated PowIRstage® is a synchronous buck
gate driver co-packed with a control MOSFET and a
synchronous MOSFET with integrated Schottky diode. It is
optimized internally for PCB layout, heat transfer and
driver/MOSFET timing. Custom designed gate driver and
MOSFET combination enables higher efficiency at lower
output voltages required by cutting edge CPU, GPU and
DDR memory designs.
Up to 1.0MHz switching frequency enables fast transient
response, allowing miniaturization of output inductors as
well as input and output capacitors while maintaining high
efficiency. The IR3558’s superior efficiency enables
smallest size and lower solution cost. The IR3558 PCB
footprint is compatible with most pins of the IR3551 (50A).
The IR3558 provides two selectable PWM logic modes, the
3.3V tri-state PWM logic or International Rectifier’s Active
TM
Tri-Level (ATL) PWM logic. The ATL PWM logic eliminates
a dedicated Body-Braking® pin and improves the transient
response of the converter during load release.
The IR3558 provides a thermal flag output with
programmable threshold from 70°C to 150°C, which makes
it possible to adjust the thermal protection threshold
based on the PCB layout and thermal distribution.
 Small 5mm x 6mm x 0.9mm PQFN package
 Lead free RoHS compliant package
APPLICATIONS
 High current, low profile DC-DC converters
BASIC APPLICATION
IR3558 VIN
LGND
VIN
4.5V to 15V
BOOST
OT#
OT#
OTSET
VOUT
SW
PWM
PWM
ENABLE
EN
MODE
CS+
PVCC
CS-
HVCC
4.5V to 13.2V
LVCC
PGND
Efficiency (%)
VCC
5V
95
20
93
18
91
16
89
14
87
12
85
10
83
8
81
6
79
4
77
2
75
Power Loss (W)
The IR3558 is optimized specifically for CPU core power
delivery in server applications. The ability to meet the
stringent requirements of the server market also makes
the IR3558 ideally suited to powering GPU and DDR
memory designs and other high current applications.
 Voltage Regulators for CPUs, GPUs, and DDR
memory arrays
VCC
IR3558
0
0
5
10
15
20
25
30
35
40
45
Output Current (A)
Figure 1: IR3558 Basic Application Circuit
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September 10, 2012 | FINAL DATASHEET
Figure 2: Typical IR3558 Efficiency & Power Loss (See Note 2 on Page 7)
45A Integrated PowIRstage®
PINOUT DIAGRAM
IR3558
ORDERING INFORMATION
Package
Tape & Reel Qty
Part Number
PQFN, 28 Lead
5mm x 6mm
4000
IR3558MTRPBF
Figure 3: IR3558 Pin Diagram, Top View
TYPICAL APPLICATION DIAGRAM
VCC
4.5V to 5.5V
C3
0.1uF
R1
10k
IR3558
OT#
PWM
ENABLE
21
OT#
22
PWM
23
EN
25 MODE
MODE
OTSET
PVCC
4.5V to 13.2V
C4
1uF
26
OTSET
2
LVCC
3
HVCC
1
16-19
VCC
VIN
C1
0.1uF
BOOST
Gate
Drivers
and
Over
Temperature
Detection
L1
150nH
C8
470uF
VOUT
R2
2.49k
PGND 14, 15
PGND 4, 27
VIN
4.5V to 15V
C7
22uF
6-13
LGND
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September 10, 2012 | FINAL DATASHEET
C5
0.22uF
SW
Figure 4: Application Circuit
2
20
C2
10uF x 2
C6
0.22uF
CS+
CS-
45A Integrated PowIRstage®
IR3558
FUNCTIONAL BLOCK DIAGRAM
BOOST LVCC
20
2
VIN
VIN
VIN
VIN
16
17
18
19
IR3558
HVCC
3
VCC
1
PWM
22
EN
23
MODE
25
OT#
21
OTSET
26
LGND
24
VCC
Thermal
Detection
Power-on
Reset
(POR),
PWM
Mode,
Reference,
and
Dead-time
Control
4
27
PGND PGND
Driver
September 10, 2012 | FINAL DATASHEET
SW
7
SW
8
SW
9
SW
10 SW
11 SW
12 SW
13 SW
Driver
5
28
GATEL GATEL
Figure 5: IR3558 Functional Block Diagram
3
6
14
15
PGND PGND
45A Integrated PowIRstage®
IR3558
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
VCC
Bias voltage for control logic. Connect VCC to a 5V supply. Connect a minimum 0.1uF
capacitor between VCC and LGND.
2
LVCC
Supply voltage for the low-side driver. Connect LVCC to a 4.5V to 13.2V supply. Connect
a minimum 0.1uF capacitor between LVCC and PGND (pin 4).
3
HVCC
Supply voltage for the high-side driver. Connect HVCC to a 4.5V to 13.2V supply.
Connect a minimum 0.1uF capacitor between HVCC and PGND (pin 4).
4, 14, 15, 27
PGND
Power ground of low-side MOSFET driver and the synchronous MOSFET.
5, 28
GATEL
Low-side MOSFET driver pins that can be connected to a test point in order to observe
the waveform.
6 – 13
SW
Switch node of synchronous buck converter.
VIN
High current input voltage connection. Recommended operating range is 4.5V to 15V.
Connect at least two 10uF 1206 ceramic capacitors and a 0.1uF 0402 ceramic capacitor.
Place the capacitors as close as possible to VIN pins and PGND pins (14-15). The 0.1uF
0402 capacitor should be on the same side of the PCB as the IR3558.
20
BOOST
Bootstrap capacitor connection. The bootstrap capacitor provides the charge to turn on
the control MOSFET. Connect a minimum 0.22µF capacitor from BOOST to SW pin. Place
the capacitor as close to BOOST pin as possible and minimize the parasitic inductance of
the connection from the capacitor to SW pin. A 1Ω to 4Ω series resistor may be added
to slow down the SW rising and limit the surge current into the bootstrap capacitor on
start-up.
21
OT#
Open drain output of the phase fault circuits. Connect to an external pull-up resistor.
Output is low when an over temperature condition inside the device is detected.
22
PWM
PWM control input. Connect this pin to the PWM output of a controller that outputs
either a 3.3V tri-state PWM signal or a 1.8V International Rectifier’s Active Tri-Level
PWM signal.
23
EN
Enable control. 3.3V logic level input. Pulling this pin high to enable the device and
grounding it to shut down both MOSFETs and enter low quiescent mode.
24
LGND
Signal ground. Driver control logic, analog circuits and IC substrate are referenced to
this pin.
25
MODE
PWM mode selection. Grounding this pin to select the regular 3.3V tri-state PWM logic
or connecting it to VCC to select International Rectifier’s Active Tri-Level PWM logic.
26
OTSET
Over temperature set. The default is 150°C when this pin is floated. A resistor from this
pin to ground programs the over temperature threshold from 70°C to 150°C. See “Over
Temperature Threshold Set Resistor ROTSET” Section for the resistor selection details.
16 – 19
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September 10, 2012 | FINAL DATASHEET
45A Integrated PowIRstage®
IR3558
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.
PIN Number
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1
VCC
6.5V
-0.3V
NA
10mA
2
LVCC
15V
-0.3V
NA
3
HVCC
15V
-0.3V
NA
4, 27
PGND
0.3V
-0.3V
15mA
1A for 100ns,
100mA DC
1A for 100ns,
100mA DC
15mA
5, 28
GATEL
LVCC + 0.3V
1A for 100ns,
200mA DC
1A for 100ns,
200mA DC
6-13
SW 2
25V
55A RMS
25A RMS
14, 15
PGND
NA
-3V for 20ns,
-0.3V DC
-5V for 20ns,
-0.3V DC
NA
25A RMS
55A RMS
16-19
2
25V
-0.3V
VIN
5A RMS
20A RMS
5A for 100ns,
100mA DC
20mA
35V
-0.3V
OT#
VCC + 0.3V
-0.3V
1A for 100ns,
100mA DC
1mA
22
PWM
VCC + 0.3V
-0.3V
1mA
1mA
23
EN
VCC + 0.3V
-0.3V
1mA
1mA
20
BOOST
21
1
24
LGND
0.3V
-0.3V
10mA
NA
25
MODE
VCC + 0.3V
-0.3V
1mA
1mA
26
OTSET
VCC + 0.3V
-0.3V
1mA
1mA
Note:
1. Maximum BOOST – SW = 15V.
2. Maximum VIN – SW = 25V.
3. All the maximum voltage ratings are referenced to PGND (Pins 14 and 15).
THERMAL INFORMATION
Thermal Resistance, Junction to Top (θJC_TOP)
18.2 °C/W
Thermal Resistance, Junction to PCB (pin 15) (θJB)
2.6 °C/W
Thermal Resistance (θJA)
1
20.8 °C/W
Maximum Operating Junction Temperature
-40 to 150°C
Maximum Storage Temperature Range
-65°C to 150°C
ESD rating
HBM Class 1A JEDEC Standard
MSL Rating
3
Reflow Temperature
260°C
Note:
1. Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal conductivity test board in free air.
Refer to International Rectifier Application Note AN-994 for details.
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September 10, 2012 | FINAL DATASHEET
45A Integrated PowIRstage®
IR3558
ELECTRICAL SPECIFICATIONS
The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25°C.
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
PARAMETER
SYMBOL
MIN
MAX
UNIT
Recommended VIN Range
VIN
4.5
15
V
Recommended VCC Range
VCC
4.5
5.5
V
Recommended LVCC Range
LVCC
4.5
13.2
V
Recommended HVCC Range
HVCC
4.5
13.2
V
Recommended Switching Frequency
ƒSW
200
1000
kHz
Recommended Operating Junction Temperature
TJ
-40
125
°C
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Efficiency
PowIRstage Peak Efficiency
η
Note 2, Figure 2
94.0
%
Note 3, Figure 8
93.0
%
PWM Tri-state Mode (Figure 6)
PWM Input High Threshold
VPWM_HIGH
PWM Tri-state to High
2.0
2.5
3.0
V
PWM Input Low Threshold
VPWM_LOW
PWM Tri-state to Low
0.7
0.8
0.9
V
PWM Tri-state Float Voltage
VPWM_TRI
0.85
1.60
2.55
V
Hysteresis
VPWM_HYS
Tri-state Hold OFF Time
TPWM_HOLD
PWM Floating
Active to Tri-state or Tristate to Active, Note 1
Note 1
PWM Input Impedance
RPWM_SINK
Minimum Pulse Width
TPWM_MIN
3.00
Note 1
200
mV
80
ns
3.75
4.50
kΩ
40
60
ns
PWM Active Tri-Level (ATL) Mode (Figure 7)
PWM Input High Threshold
VATL_HIGH
0.8
1.0
1.2
V
PWM Input High Threshold
VATL_LOW
0.65
0.8
0.95
V
PWM Tri-Level High Voltage
VATL_TRI_HIGH
2.1
2.5
2.9
V
PWM Tri-Level Low Voltage
VATL_TRI_LOW
2.00
2.30
2.42
V
PWM Input Current Low
VPWM = 0V
-1.0
-1.5
mA
PWM Input Current High
VPWM = 1.8V
-1.0
-1.5
mA
Enable Input – EN
Input Voltage High
VN_H
Input Voltage Low
VEN_L
Input Current
IEN
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September 10, 2012 | FINAL DATASHEET
2.0
V(EN) = 5.5V
V
0.1
0.8
V
1
µA
45A Integrated PowIRstage®
PARAMETER
SYMBOL
CONDITIONS
MIN
IR3558
TYP
MAX
UNIT
Thermal Warning - OTSET Input and OT# Output
Over Temperature High Threshold
OT
ROTSET = open, Note 1
150
°C
Programmable Over Temperature High
Threshold
OT
ROTSET = 100kΩ, Note 1
125
°C
Over Temperature Hysteresis
OTHYS
Note 1
-20
°C
1.5
mA
OT# Sink Current
1.0
OT# Output Low Voltage
1.5mA
0.4
1.0
V
0.65
0.80
0.95
mV
Bootstrap Diode
Forward Voltage
BDFV
I(BOOST) = 30mA, LVCC =
6.8V
VCC Under Voltage Lockout
Start Threshold
VVCC_START
3.5
3.8
4.1
V
Stop Threshold
VVCC_STOP
3.2
3.5
3.8
V
Hysteresis
VVCC_HYS
0.15
0.30
0.45
V
General
VCC Supply Quiescent Current
IVCC
V(VCC) = 5V, V(EN) =0V
1.5
2.5
mA
VCC Supply Current
IVCC_SW
V(VCC) = 5V, V(EN) =5V
2.7
3.5
mA
LVCC Supply Quiescent Current
ILVCC
V(LVCC) = 5V, V(EN) =0V
15
25
uA
V(LVCC) = 7V, V(EN) =0V
20
30
uA
V(LVCC) = 5V, V(EN) =5V,
fsw=400kHz
10
20
mA
V(LVCC) = 7V, V(EN) =5V,
fsw=400kHz
15
25
mA
V(HVCC) = 5V, V(EN) =0V
15
25
uA
V(HVCC) = 7V, V(EN) =0V
20
30
uA
V(HVCC) =5V, V(EN) =5V,
fsw=400kHz
5
10
mA
V(HVCC) =7V, V(EN) =5V,
fsw=400kHz
6.5
15
mA
1
µA
LVCC Supply Current
HVCC Supply Quiescent Current
HVCC Supply Current
VIN Supply Leakage Current
ILVCC_SW
IBOOST
IBOOST_SW
IVIN
VIN = 20V, 125°C, V(PWM) =
Tri-State
Notes
1. Guaranteed by design but not tested in production
2. VIN=12V, VOUT=1.2V, ƒSW = 300kHz, L=210nH (0.2mΩ), HVCC=LVCC=6.8V, CIN=47uF x 4, COUT =470uF x3, 400LFM airflow, no heat sink,
25°C ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included.
3. VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), HVCC=LVCC=7V, CIN=47uF x 4, COUT =470uF x3, no airflow, no heat sink, 25°C
ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included.
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September 10, 2012 | FINAL DATASHEET
45A Integrated PowIRstage®
IR3558
TIMING DIAGRAMS
Normal PWM
Normal PWM
VPWM_HIGH
VPWM_TRI
PWM
Tri-state
Tri-state
VPWM_LOW
SW
GATEL
Figure 6: IR3558 Switching Waveforms in 3.3V Tri-state PWM Mode
ATL Tri-state
Normal PWM
VATL_TRI_HIGH
VATL_TRI_LOW
ATL Tri-state
Normal
PWM
VATL_HIGH
VATL_LOW
PWM
SW
GATEL
Figure 7: IR3558 Switching Waveforms in International Rectifier’s Active Tri-Level® (ATL) PWM Mode
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September 10, 2012 | FINAL DATASHEET
45A Integrated PowIRstage®
IR3558
TYPICAL OPERATING CHARACTERISTICS
Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW=400kHz, L=150nH (0.29mΩ), VCC=5V, HVCC=LVCC=7V, TAMB=25°C, no heat sink,
no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise.
94
1.15
3.3
1.10
2.2
1.05
1.1
1.00
0.0
0.95
-1.1
0.90
-2.2
92
91
Normalized Power Loss
Efficiency (%)
90
89
88
87
86
85
84
83
82
Case Temperature Adjustment (°C)
93
81
80
0.85
10
15
20
25
30
35
-3.3
40
5
6
7
8
9
Output Current (A)
12
13
14
15
Figure 11: Normalized Power Loss vs. Input Voltage
10
1.40
8.8
9
1.35
7.7
1.30
6.6
1.25
5.5
1.20
4.4
1.15
3.3
1.10
2.2
1.05
1.1
1.00
0.0
0.95
-1.1
0.90
-2.2
1
0.85
-3.3
0
0.80
8
Normalized Power Loss
7
Power Loss (W)
11
Input Voltage (V)
Figure 8: Typical IR3558 Efficiency
6
5
4
3
2
0
5
10
15
20
25
30
35
40
-4.4
0.8
0.9
1
1.1
Output Current (A)
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
Output Voltage (V)
Figure 9: Typical IR3558 Power Loss
Figure 12: Normalized Power Loss vs. Output Voltage
50
1.45
9.9
45
1.40
8.8
1.35
7.7
1.30
6.6
1.25
5.5
1.20
4.4
1.15
3.3
1.10
2.2
1.05
1.1
1.00
0.0
0.95
-1.1
0.90
-2.2
40
35
Normalized Power Loss
Output Current (A)
10
30
25
20
400LFM
15
200LFM
10
100LFM
0LFM
5
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
Ambient Temperature (°C)
Figure 10: Safe Operating Area, TCASE <= 125°C
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September 10, 2012 | FINAL DATASHEET
Case Temperature Adjustment (°C)
5
0.85
200
Case Temperature Adjustment (°C)
0
-3.3
300
400
500
600
700
800
900
1000
Switching Frequency (kHz)
Figure 13: Normalized Power Loss vs. Switching Frequency
45A Integrated PowIRstage®
IR3558
TYPICAL OPERATING CHARACTERISTICS (CONTINUED)
Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW=400kHz, L=150nH (0.29mΩ), VCC=5V, HVCC=LVCC=7V, TAMB=25°C, no heat sink,
no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise.
60
1.25
5.5
1.20
4.4
1.15
3.3
1.10
2.2
1.05
1.1
1.00
0.0
0.95
-1.1
0.90
-2.2
10
0.85
-3.3
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0
5
50
LVCC=12V
45
LVCC Current (mA)
Case Temperature Adjustment (°C)
Normalized Power Loss
55
LVCC=7V
40
LVCC=5V
35
30
25
20
15
0
200
HVCC and LVCC Voltage (V)
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950 1000
fsw (kHz)
Figure 17: LVCC Current vs. Switching Frequency
Figure 14: Normalized Power Loss vs. HVCC & LVCC Voltage
1.15
3.3
1.10
2.2
30.0
1.1
1.00
0.0
0.95
-1.1
0.90
-2.2
HVCC=12V
25.0
HVCC=7V
22.5
LVCC Current (mA)
1.05
Case Temperature Adjustment (°C)
Normalized Power Loss
27.5
HVCC=5V
20.0
17.5
15.0
12.5
10.0
7.5
5.0
0.85
120
130
140
150
160
170
180
190
200
-3.3
210
2.5
0.0
200
Output Inductor (nH)
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950 1000
fsw (kHz)
Figure 18: HVCC Current vs. Switching Frequency
Figure 15: Power Loss vs. Output Inductor
3.0
PWM
5V/div
2.5
VCC Current (mA)
2.0
SW
5V/div
Vcc=5.5V
1.5
Vcc=5V
1.0
0.5
GATEL
10V/div
0.0
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950 1000
fsw (kHz)
Figure 16: VCC Current vs. Switching Frequency
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September 10, 2012 | FINAL DATASHEET
400ns/div
Figure 19: Switching Waveform in Tri-state Mode, IOUT = 0A
45A Integrated PowIRstage®
IR3558
TYPICAL OPERATING CHARACTERISTICS (CONTINUED)
Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW=400kHz, L=150nH (0.29mΩ), VCC=5V, HVCC=LVCC=7V, TAMB=25°C, no heat sink,
no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise.
PWM
5V/div
PWM
2V/div
SW
5V/div
SW
5V/div
GATEL
5V/div
GATEL
10V/div
100ns/div
400ns/div
Figure 20: Switching Waveform in Tri-state Mode, IOUT = 40A
Figure 23: PWM Tri-state Delays in Tri-state Mode, IOUT = 10A
PWM
2V/div
PWM
5V/div
SW
5V/div
SW
5V/div
GATEL
5V/div
GATEL
10V/div
400ns/div
40ns/div
Figure 21: PWM to SW Delays in Tri-state Mode, IOUT = 10A
Figure 24: Switching Waveform in ATL Mode, IOUT = 0A
PWM
2V/div
PWM
2V/div
SW
5V/div
SW
5V/div
GATEL
5V/div
100ns/div
Figure 22: PWM Tri-state Delays in Tri-state Mode, IOUT = 10A
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September 10, 2012 | FINAL DATASHEET
GATEL
10V/div
400ns/div
Figure 25: Switching Waveform in ATL Mode, IOUT = 40A
45A Integrated PowIRstage®
IR3558
TYPICAL OPERATING CHARACTERISTICS (CONTINUED)
Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW=400kHz, L=150nH (0.29mΩ), VCC=5V, HVCC=LVCC=7V, TAMB=25°C, no heat sink,
no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise.
PWM
2V/div
EN
5V/div
SW
5V/div
SW
5V/div
GATEL
5V/div
GATEL
5V/div
40ns/div
400ns/div
Figure 26: PWM to SW Delays in ATL Mode, IOUT = 10A
Figure 29: EN Disable Delay, IOUT = 0A
150
SW
5V/div
GATEL
5V/div
140
Over Temperature Thresholds (oC)
PWM
2V/div
130
High Threshold
120
110
Low Threshold
100
90
80
70
60
50
40
30
1
10
100
1000
OTSET Resistor (kΩ)
40ns/div
Figure 27: PWM Tri-state Delays in ATL Mode, IOUT = 10A
Figure 30: Over Temperature Threshold vs. OTSET Resistor
PWM
2V/div
PWM
2V/div
SW
5V/div
SW
5V/div
SW
5V/div
40ns/div
Figure 28: PWM Tri-state Delays in ATL Mode, IOUT = 0A
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GATEL
10V/div
400ns/div
Figure 31: Switching Waveform, IOUT = 40A, HVCC = LVCC = 12V
45A Integrated PowIRstage®
THEORY OF OPERATION
DESCRIPTION
The IR3558 PowIRstage® is a synchronous buck driver with
co-packed MOSFETs with integrated Schottky diode, which
provides system designers with ease of use and flexibility
required in cutting edge CPU, GPU and DDR memory
power delivery designs and other high-current low-profile
applications.
The IR3558 is designed to work with a PWM controller.
It accepts either regular 3.3V tri-state PWM signal or
International Rectifier’s Active Tri-Level (ATL) PWM signal,
which is selectable by MODE pin.
The IR3558 provides Enable input to control the converter
output and reduce quiesecent current.
The IR3558 provides a over temperature fault signal
capable of detecting an over-temperature condition in the
vicinity of the power stage. The over-temperature
threshold is programmable from 70°C to 150°C.
PWM MODE SELECTION
The IR3558 features a MODE pin which allows operation
with two different PWM signal levels. Grounding the
MODE pin allows the IR3558 to accept a regular tri-state
PWM with signal from 0V to 3.3V for low to high
transitions. A PWM voltage level in the tri-state window of
0.85V and 2.55V for 80ns hold off time results in turning
off both the control and synchronous MOSFETs. Floating
MODE pin or connecting it to VCC enables the IR3558 to
accept IR’s proprietary ATL mode, in which the PWM
voltage level is from 0V to 1.8V for low to high transitions.
A PWM voltage level greater than the tri-state high
threshold (2.5V typical) turns off both the control and
synchronous MOSFETs.
REGULAR 3.3V PWM MODE
If MODE pin is grounded, the IR3558 accepts regular 3level 3.3V PWM input signals. As shown in Figure 6, when
PWM input is above VPWM_HIGH, the synchronous MOSFET is
turned off and the control MOSFET is turned on. When
PWM input is below VPWM_LOW, the control MOSFET is
turned off and synchronous MOSFET is turned on. If PWM
pin is floated, the built-in resistors pull the PWM pin into a
tri-state region centered around 1.6V. Figures 19-23 show
the PWM input and the corresponding SW and GATEL
output of the IR3558.
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IR3558
ACTIVE TRI-LEVEL PWM MODE
When MODE pin is floating, the IR3558 accepts a unique
tri-level PWM control signal provided by an IR digital PWM
controller. As shown in Figure 7, the rising and falling
edges of the PWM signal transition between 0V and 1.8V
to switch both the control and synchronous MOSFETs
during normal PWM operation. To turn both MOSFETs off
simultaneously, the PWM signal crosses a tri-state voltage
level higher than the VATL_TRI_HIGH threshold (2.5V typical).
This threshold based tri-state results in a very fast disable
with only a small propagation delay. MOSFET switching
resumes when the PWM signal falls below the VATL_TRI_LOW
threshold (2.3V typical) into the normal PWM operating
voltage range. Figures 24-28 show the PWM input and the
corresponding SW and GATEL output of the IR3558.
This fast tri-state operation eliminates the need for the
PWM signal to dwell in the shutdown window, eliminating
the delay time created by the PWM pull-up and pull-down
resistors with the PWM trace routing capacitance. A
dedicated Body-Braking® pin is not required, which
simplifies the routing and layout.
One advantage of the ATL is the ability to quickly turn-off
all synchronous MOSFETs during a load release event. This
is known as Body-Braking® since all the load current is
forced to flow momentarily through the body diodes of the
MOSFETs, which discharges the inductor current faster and
results in a much lower overshoot on the output voltage.
The IR3558 provides a 1mA typical pull-up current to drive
the PWM input to the tri-state condition of 3.3V when the
PWM controller output is in its high impedance state. The
1mA typical current is designed for driving worst case stray
capacitances and transition the IR3558 into the tri-state
condition rapidly to avoid a prolonged period of
conduction of the control or synchronous MOSFET during
faulty conditions. Once the PWM signal has been pulled
up, the 1mA current is disabled to reduce power
consumption.
ENABLE CONTROL
EN is a 3.3V logic input. Logic low disables PWM operation
and places the power stage in tri-state, as shown in Figure
29. It also places the driver in a low power state with
minimum quiescent current. Logic high enables the device.
INTEGRATED BOOTSTRAP DIODE
The bootstrap circuit is used to establish the gate voltage
for the high-side driver. It consists of a diode and capacitor
45A Integrated PowIRstage®
connected between the SW and BOOST pins of the device.
The bootstrap capacitor stores the charge and provides the
voltage required to drive the internal control MOSFET gate.
The IR3558 features an integrated bootstrap diode to
reduce external component count. This enables the IR3558
to be used effectively in cost and space sensitive designs.
For ultra high efficiency designs, an external bootstrap
diode in parallel with the integrated bootstrap diode is
recommended.
A series resistor, 1Ω to 4Ω, may be added to slow down the
SW rising and limit the surge current into the bootstrap
capacitor on start-up.
ADJUSTABLE OVER TEMPERATURE THRESHOLD
In a single phase regulator, over temperature of the power
stage can happen due to the over current, inductor
saturation or other faulty conditions. In a multiphase
voltage regulator, differences in temperature from phase
to phase can occur due to current unbalance, mismatched
thermal solutions, airflow, surrounding components or
manufacturing errors and can often cause poor efficiency
or even system failures if not monitored.
The IR3558 detects the die temperature of its internal
MOSFET driver. The OTSET feature allows the user to
adjust the over temperature threshold from 70°C to 150°C
using a simple resistor between OTSET pin and ground. The
equation defining the over temperature threshold, TOTSET as
a function of ROTSET is:
TOTSET  150C  89C 
38k
38k  ROTSET
Leaving the OTSET pin open will set the over temperature
threshold at the default 150°C. Figure 30 shows the values
of ROTSET chosen as a function of the desired over
temperature threshold.
The OT# flag is an open drain signal and is active low as the
temperature of the IR3558 die exceeds the OTSET
threshold. The OT# becomes high once the IR3558
temperature drops by the 20°C hysteresis. The OT# pin can
be tied to a system level Enable to implement an overtemperature shutdown feature in a voltage regulator. To
monitor all the phases in a multiphase system, tie the OT#
of all IR3558 together and connect it to system Enable.
If OT# is not used it can be floated or connected to LGND.
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IR3558
ADJUSTABLE HVCC AND LVCC DRIVE VOLTAGES
HVCC and LVCC voltages can be independently adjusted to
optimize high-side and low-side MOSFET efficiency
respectively. Both voltage ranges are from 4.5V to 13.2V.
Higher HVCC and LVCC gate drive voltages improve
efficiency at heavy load but lower efficiency at light load.
Higher HVCC voltage also causes undesirable higher
switching node spike, as shown in Figure 31.
DESIGN PROCEDURES
POWER LOSS CALCULATION
The single-phase IR3558 efficiency and power loss
measurement circuit is shown in Figure 32.
VCC IVCC
C3
0.1uF
IIN
VIN
VCC
R1
10k
IR3558
OT#
PWM
BOOST
C5
0.22uF
L1
150nH
IOUT VOUT
SW
EN
R2
2.49k
MODE
LVCC
C6
470uF x3
C4
0.22uF
HVCC
C7
1uF
C2
47uF x4
LGND
OTSET
PVCC IPVCC
VIN
C1
0.1uF x2
CS+
CS-
PGND
VSW
Figure 32: IR3558 Power Loss Measurement
The IR3558 power loss is determined by,
PLOSS  VIN  I IN  VCC  IVCC  VPVCC  I PVCC  VSW  I OUT
Where both MOSFET loss and the driver loss are included,
but the PWM controller and the inductor losses are not
included.
Figure 8 shows the measured single-phase IR3558
efficiency under the default test conditions, VIN=12V,
VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), PVCC (HVCC/
LVCC) = 7V, TAMBIENT = 25°C, no heat sink, and no air flow.
The efficiency of an interleaved multiphase IR3558
converter is always higher than that of a single-phase
under the same conditions due to the reduced input RMS
current and more input/output capacitors.
The measured single-phase IR3558 power loss under the
same conditions is provided in Figure 9.
45A Integrated PowIRstage®
If any of the application condition, i.e. input voltage,
output voltage, switching frequency, PVCC (HVCC/LVCC)
MOSFET driver voltage or inductance, is different from
those of Figure 9, a set of normalized power loss curves
should be used. Obtain the normalizing factors from
Figures 11-15 for the new application conditions; multiply
these factors by the power loss obtained from Figure 9 for
the required load current.
As an example, the power loss calculation procedures
under different conditions, VIN=10V, VOUT=1V, ƒSW = 300kHz,
L=210nH, PVCC (HVCC/LVCC) = 5V, IOUT=35A, TAMBIENT =
25°C, no heat sink, and no air flow, are as follows.
1) Determine the power loss at 35A under the default
test conditions of VIN=12V, VOUT=1.2V, ƒSW = 400kHz,
L=150nH, PVCC (HVCC/LVCC) = 7V, TAMBIENT = 25°C, no
heat sink, and no air flow. It is 5.2W from Figure 9.
2) Determine the input voltage normalizing factor with
VIN=10V, which is 0.97 based on the dashed lines in
Figure 11.
3) Determine the output voltage normalizing factor with
VOUT=1V, which is 0.90 based on the dashed lines in
Figure 12.
4) Determine the switching frequency normalizing factor
with ƒSW = 300kHz, which is 0.99 based on the dashed
lines in Figure 13.
IR3558
If any of the application condition, i.e. input voltage,
output voltage, switching frequency, HVCC/LVCC MOSFET
driver voltage, or inductance is different from those of
Figure 10, a set of IR3558 case temperature adjustment
curves should be used. Obtain the temperature deltas
from Figures 11-15 for the new application conditions; sum
these deltas and then subtract from the IR3558 case
temperature obtained from Figure 10 for the required load
current.
The IR3558 safe operating area is obtained with the case
temperature controlled at or below 125°C. If a lower case
temperature is desired, reduce the highest ambient
temperature by the same delta.
As an example, the highest ambient temperature
calculation procedures for a different operating condition,
VIN=10V, VOUT=1V, ƒSW = 300kHz, L=210nH, PVCC
(HVCC/LVCC) = 5V, IOUT=35A, TAMBIENT = 25°C, no heat sink,
and no air flow, are as follows.
8) From Figure 10, determine the highest ambient
temperature at the required load current under the
default conditions, which is 65°C at 35A with 0LFM
airflow and the IR3558 case temperature of 125°C.
9) Determine the case temperature with VIN=10V, which
is -0.7° based on the dashed lines in Figure 11.
10) Determine the case temperature with VOUT=1V, which
is -2.2° based on the dashed lines in Figure 12.
5) Determine the MOSFET drive voltage normalizing
factor with PVCC (HVCC/LVCC) = 5V, which is 1.22
based on the dashed lines in Figure 14.
11) Determine the case temperature with ƒSW = 300kHz,
which is -0.2° based on the dashed lines in Figure 13.
6) Determine the inductance normalizing factor with
L=210nH, which is 0.96 based on the dashed lines in
Figure 15.
12) Determine the case temperature with PVCC
(HVCC/LVCC) = 5V, which is +4.9° based on the dashed
lines in Figure 14.
7) Multiply the power loss under the default conditions
by the five normalizing factors to obtain the power
loss under the new conditions, which is 5.2W x 0.97 x
0.90 x 0.99 x 1.22 x 0.96 = 5.3W.
13) Determine the case temperature with L=210nH, which
is -0.9° based on the dashed lines in Figure 15.
SAFE OPERATING AREA
Figure 10 shows the IR3558 safe operating area with the
case temperature controlled at or below 125°C. The test
conditions are VIN=12V, VOUT=1.2V, ƒSW=400kHz, L=150nH
(0.29mΩ), HVCC=LVCC=7V, TAMBIENT = 0°C to 90°C, no heat
sink, and Airflow = 0LFM / 100LFM / 200LFM / 400LFM.
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14) Sum the case temperature adjustment from 9) to 13),
-0.7° -2.2° -0.2° +4.9° -0.9° = +0.9°. Deduct the delta
from the highest ambient temperature in step 8), 65°C
- (+0.9°C) = 64.1°C.
15) If the desired IR3558 case temperature is 105°C
instead of 125°C, subtract 20°C ( =125°C - 105°C) from
the highest ambient temperature obtained from 14),
i.e. 64.1°C - 20°C = 44.1°C.
45A Integrated PowIRstage®
OVER TEMPERATURE THRESHOLD SET RESISTOR
ROTSET
Decide the desired over temperature threshold, TOTSET,
based on the system requirement. Leaving the OTSET pin
open will set the over temperature threshold at the 150°C.
If the desired over temperature threshold is between 70°C
and 150°C, use the following equation to calculate the
OTSET resistor ROTSET.
150
o
close as possible to the BOOST pin. A low inductance
routing of the SW pin connection to the other terminal of
the bootstrap capacitor is strongly recommended.
A series resistor, 1Ω to 4Ω, may be added to slow down the
SW rising and limit the surge current into the bootstrap
capacitor on start-up.
VCC, HVCC AND LVCC DECOUPLING CAPACITORS
CVCC, CHVCC AND CLVCC
A 0.1uF ceramic decoupling capacitor is required at the
VCC pin. A 0.1uF to 1uF ceramic decoupling capacitor is
required at the HVCC or LVCC pin. They should be mounted
on the same side of the PCB as the IR3558. The VCC
capacitor should be as close as possible to the VCC and
LGND. The HVCC and LVCC capacitors should be as close as
possible to HVCC/LVCC and PGND (pin 4). Low inductance
routing for the decoupling capacitors is strongly
recommended.
140
Over TemperatureT Threshold ( C)
IR3558
130
120
110
100
90
80
70
60
50
40
30
1
10
100
1000
OTSET Resistor (kΩ)
Figure 33: Over Temperature Threshold vs. ORSET Resistor
ROTSET 
38k  89C
 38k
150C  TOTSET
Figure 33 can also be used to determine the values of
ROTSET. A 1% or better resistor should be used for the best
accuracy.
INPUT CAPACITORS CVIN
At least two 10uF 1206 ceramic capacitors and one 0.1uF
0402 ceramic capacitor are recommended for decoupling
the VIN to PGND connection. The 0.1uF 0402 capacitor
should be on the same side of the PCB as the IR3558 and
next to the VIN and PGND pins. Adding additional
capacitance and use of capacitors with lower ESR and
mounted with low inductance routing will improve
efficiency and reduce overall system noise, especially in
single-phase designs or during high current operation.
BOOTSTRAP CAPACITOR CBOOST
A minimum of 0.22uF 0402 capacitor is required for the
bootstrap circuit. A high temperature 0.22uF or greater
value 0402 capacitor is recommended. It should be
mounted on the same side of the PCB as the IR3558 and as
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MOUNTING OF HEAT SINKS
Care should be taken in the mounting of heat sinks so as
not to short-circuit nearby components. The VCC and
bootstrap capacitors are typically mounted on the same
side of the PCB as the IR3558. The mounting height of
these capacitors must be considered when selecting their
package sizes.
HIGH OUTPUT VOLTAGE DESIGN
CONSIDERATIONS
The IR3558 is capable of creating output voltages above
the 3.3V recommended maximum output voltage as there
are no restrictions inside the IR3558 on the duty cycle
applied to the PWM pin. However the output current
rating of the device will be reduced as the duty cycle
increases. In very high duty cycle applications sufficient
time must be provided for replenishment of the Bootstrap
capacitor for the control MOSFET drive.
LAYOUT EXAMPLE
Contact International Rectifier for a layout example
suitable for your specific application.
45A Integrated PowIRstage®
IR3558
METAL AND COMPONENT PLACEMENT
 Lead land width should be equal to nominal part
lead width. The minimum lead to lead spacing
should be ≥ 0.2mm to prevent shorting.
 Lead land length should be equal to maximum
part lead length +0.15 - 0.3 mm outboard
extension and 0 to + 0.05mm inboard extension.
The outboard extension ensures a large and
visible toe fillet, and the inboard extension will
accommodate any part misalignment and
ensure a fillet.
 Center pad land length and width should be
equal to maximum part pad length and width.
 Only 0.30mm diameter via shall be placed in the
area of the power pad lands and connected to
power planes to minimize the noise effect on the
IC and to improve thermal performance.
Figure 34: Metal and component placement
* Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format.
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45A Integrated PowIRstage®
to provide a fillet so a solder resist width of ≥
0.17mm remains.
SOLDER RESIST
 The solder resist should be pulled away from
the metal lead lands by a minimum of 0.06mm.
The solder resist miss-alignment is a maximum
of 0.05mm and it is recommended that the low
power signal lead lands are all Non Solder Mask
Defined (NSMD). Therefore pulling the S/R
0.06mm will always ensure NSMD pads.
 The minimum solder resist width is 0.13mm
typical.
 The dimensions of power land pads, VIN, PGND,
and SW, are Non Solder Mask Defined (NSMD).
The equivalent PCB layout becomes Solder Mask
Defined (SMD) after power shape routing.
 Ensure that the solder resist in-between the lead
lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip
separating the lead lands from the pad land.
 At the inside corner of the solder resist where
the lead land groups meet, it is recommended
Figure 35: Solder resist
* Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format.
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IR3558
45A Integrated PowIRstage®
IR3558
STENCIL DESIGN
 The stencil apertures for the lead lands should be
approximately 65% to 75% of the area of the lead
lands depending on stencil thickness. Reducing
the amount of solder deposited will minimize the
occurrence of lead shorts. Since for 0.5mm pitch
devices the leads are only 0.25mm wide, the
stencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult
to maintain repeatable solder release.
 The low power signal stencil lead land apertures
should therefore be shortened in length to keep
area ratio of 65% to 75% while centered on lead
land.
 The power pads VIN, PGND and SW, land pad
apertures should be approximately 65% to 75%
area of solder on the center pad. If too much
solder is deposited on the center pad the part will
float and the lead lands will be open. Solder
paste on large pads is broken down into small
sections with a minimum gap of 0.2mm between
allowing for out-gassing during solder reflow.
 The maximum length and width of the land pad
stencil aperture should be equal to the solder
resist opening minus an annular 0.2mm pull back
to decrease the incidence of shorting the center
land to the lead lands when the part is pushed
into the solder paste.
Figure 36: Stencil design
* Contact International Rectifier to receive an electronic PCB Library file in Cadence Allegro or CAD DXF/DWG format.
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45A Integrated PowIRstage®
MARKING INFORMATION
Site/Date/M arking Code
Lot Code
3558M
?Y W W ?
xxxxx
Figure 37: PQFN 5mm x 6mm
PACKAGE INFORMATION
Figure 38: PQFN 5mm x 6mm
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IR3558
45A Integrated PowIRstage®
IR3558
Data and specifications subject to change without notice.
This product will be designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
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