AD ADV7202

PRELIMINARY TECHNICAL DATA
a
Simultaneous Sampling
Video Rate Codec
ADV7202
Preliminary Technical Data
FEATURES
Four 10-Bit Video DACs (4:2:2, YCrCb, RGB I/P
Supported)
10-Bit Video Rate Digitization at Up to 54 Mhz
AGC Control (ⴞ6 dB)
Front-End 3-Channel Clamp Control
Up to Five CVBS Input Channels, Two Component YUV,
Three S-Video, or a combination of the above. Simultaneous Digitization of Two CVBS Input Channels.
Aux 8-Bit SAR ADC @ 843 kHz Sampling Giving up to
Eight General Purpose Inputs
I2C and SPI Compatible Interface with I2C Filter
RGB Inputs for Picture-on-Picture of the RGB DACs
APPLICATIONS
Picture-on-Picture Video Systems
Simultaneous Video Rate Processing
Hybrid Set-Top Box TV Systems
Direct Digital Synthesis/I-Q Demodulation
Image Processing
GENERAL DESCRIPTION
The ADV7202 is a video rate sampling Codec.
It has the capability of sampling up to five NTSC/PAL/SECAM
video I/P signals. The resolution on the front-end digitizer is
12 bits; 2 bits (12 dB) are used for gain and offset adjustment.
The digitizer has a conversion rate of 54 MHz.
It also has up to eight auxiliary inputs that can be sampled by
an 843 kHz SAR ADC for system monitoring, etc.
The back end consists of four 10-bit DACs that run at up to
54 MHz and can be used to output CVBS, S-Video, Component
YCrCb, and RGB.
This Codec also supports Picture-on-Picture with the 3-channel
I/P mux that also muxes to the DAC O/Ps.
The ADV7202 can operate at 3.3 V or 5 V. Its monolithic CMOS
construction ensures greater functionality with lower power
dissipation.
The ADV7202 is packaged in a small 64-lead LQFP package.
FUNCTIONAL BLOCK DIAGRAM
XTAL
DOUT
[9:0]
DAC DATA
[9:0]
OSD I/P "S"
AIN1P
SHA AND
CLAMP
AIN1M
AIN2P
AIN2M
SHA AND
CLAMP
AIN3P
AIN3M
AIN4P
10-BIT
ADC BLOCK
D/A
12-BIT
I/P
MUX
MUX
10-BIT
SHA AND
CLAMP
D/A
ADC
LOGIC
AIN4M
DAC1
DAC
LOGIC
AIN5P
AIN5M
DAC0
A/D
10-BIT
8-BIT 843KHz
A/D
D/A
DAC2
AIN6P
AIN6M
10-BIT
D/A
DAC3
ADV7202
12C/SPI
REV. PrB
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
ADV7202–SPECIFICATIONS
5 V SPECIFICATIONS (AVDD/DVDD = 5 V ⴞ 5%, V
REF = 1.235 V RSET = 1.2 k⍀,
Parameter
Min
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
VIDEO ADC
Resolution
Accuracy
Integral Nonlinearity
Differential Nonlinearity
Input Voltage Range2
SNR
AUX ADC
Resolution
Differential Nonlinearity
Integral Nonlinearity
SNR
Input Voltage Range
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Output Capacitance
Digital Output Access Time, t14
Digital Output Hold Time, t15
ANALOG OUTPUTS
Output Current
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Analog Output Delay3
DAC Output Skew
VOLTAGE REFERENCE
Reference Range, VREFDAC
Reference Range, VREFADC
Reference Range, VREFADC
Typ
Max
10
10
±2
±2
Unit
LSB
LSB
10-Bit Operation
10-Bit Operation
Bits
(plus 2-Bits for gain ranging) 2.2 V Ref.
LSB
LSB
10-Bit
10-Bit
See Figure TBD
27 MHz Clock, fIN = 100 kHz
54 MHz Clock, fIN = 100 kHz
+VREFADC
62
50
dB
dB
8
±1
±2
44
Bits
LSB
LSB
dB
V
0
2 VREFADC
2
0.8
±1
TBD
2.4
0.4
10
10
8
3
4.33
2
V
V
µA
pF
ns
ns
7
0
1.235
2.200
1.100
V
V
V
+1.4
50
30
Guaranteed Monotonic
27 MHz Clock
V
V
µA
pF
mA
%
V
kΩ
pF
ns
ns
0
Test Conditions
Bits
10
10
±1
± 0.25
–VREFADC
all specifications TMIN to TMAX1 unless otherwise noted.)
ISOURCE = 400 µA
ISINK = 3.2 mA
See Figure 16
RSET = 1.2 kΩ, RL = 300 Ω
IOUT = 0 mA
Programmable 1.1 V or 2.2 V
NOTES
1
0°C to 70°C
2
SHA gain = 1, half range for SHA gain = 2, see Table II.
3
Output Delay measured from 50% of the rising edge of the clock to the 50% point of full-scale transition.
Specifications subject to change without notice.
–2–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
5 V SPECIFICATIONS
(AVDD/DVDD = 5 V ⴞ 5%, VREF = 1.235 V RSET = 1.2 k⍀, all specifications TMIN to TMAX unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
4.75
5
5.25
V
Test Conditions
1
POWER REQUIREMENTS
AVDD/DVDD
Normal Power Mode
IDAC2
IDSC3
IADC4
Sleep Mode
Current
PSU Rejection Ratio
DACs
Video ADC
Aux ADC
Power-Up Time
MPU PORT—I2C5
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
4
34
21
mA
mA
mA
RSET = 1.2 kΩ, RL = 300 Ω
100
µA
RSET = 1.2 kΩ, RL = 300 Ω
0.5
0.5
TBD
%/%
%/%
TBD
TBD
COMP = 0.1 µF
400
kHz
µs
µs
µs
0.01
0.01
TBD
TBD
0
0.6
1.3
0.6
0.6
100
300
300
0.6
µs
ns
ns
ns
µs
5, 6
MPU PORT—SPI
SCLOCK Frequency
SCLOCK High Pulsewidth, t21
SCLOCK Low Pulsewidth, t22
SI Data Setup Time, t20
SI Data Hold Time, t19
0
TBD
TBD
TBD
TBD
RESET Low Time
100
10
TBD
TBD
TBD
TBD
MHz
kHz
ns
ns
ns
ns
NOTES
1
All DACs and ADCs on.
2
IDAC is the DAC supply current.
3
IDSC is the digital core supply current.
4
IADC is the ADC supply current.
5
TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, as measured between the 10% and 90% points.
Timing reference points at 50% for inputs and outputs.
6
See SPI timing diagram Figures 10 and 11.
Specifications subject to change without notice.
REV. PrB
–3–
TBD
Ref. power-up time
After this period the first clock is
generated.
Relevant for Repeated Start Condition
PRELIMINARY TECHNICAL DATA
ADV7202–SPECIFICATIONS
5 V SPECIFICATIONS
(AVDD/DVDD = 4.75 – 5.25, VREF = 1.235 V RSET = 1.2 k⍀, all specifications TMIN to TMAX1 unless otherwise noted.)
Parameter
Min
PROGRAMMABLE GAIN
AMPLIFIER
Video ADC Gain
Max
Unit
Condition2
+6
dB
Setup Conditions
TBD
3
0.5
µA
µA
mA
27
80
27
2
2
MHz
MHz
MHz
ns
ns
TBD
TBD
Clock Cycles
Clock Cycles
10
ns
Typ
–6
3
CLAMP CIRCUITRY
Clamp Off Leakage Current
Clamp Fine Source/Sink Current
Clamp Coarse Source/Sink Current
CLOCK CONTROL4
DACCLK0/16, 7
DACCLK1
DACCLK18
Data Setup Time, t12
Data Hold Time, t13
Pipeline Delay5, t18
Video ADC
SAR
RESET CONTROL
RESET Low Time
Dual CLK Dual Edge Mode
Single Edge Single Clock Mode
4:2:2 Mode
All Input Modes
NOTES
1
Temperature range T MIN to TMAX: 0oC to 70oC.
2
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.
3
External clamp capacitor = 0.1 µF.
4
TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤10 pF.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full scale transition.
6
Maximum clock speed determined by setup and hold conditions.
7
Single DAC only.
8
Guaranteed by Characterization.
Specifications subject to change without notice.
–4–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
3.3 V SPECIFICATIONS
(AVDD/DVDD = 3.3 V ⴞ 5%, VREF = 1.235 V RSET = 1.2 k⍀, all specifications TMIN to TMAX1 unless otherwise noted.)
Parameter
Min
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
VIDEO ADC
Resolution
Accuracy
Integral Nonlinearity
Differential Nonlinearity
Differential Input Voltage Range2
SNR
AUX ADC
Resolution
Differential Nonlinearity
Integral Nonlinearity
SNR
Input Voltage Range
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Output Capacitance
Digital Output Access Time, t14
Digital Output Hold Time, t15
ANALOG OUTPUTS
Output Current
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Analog Output Delay3
DAC Output Skew
VOLTAGE REFERENCE
Reference Range, VREFDAC
Reference Range, VREFADC
Typ
Max
10
10
±2
±2
10
10
±1
± 0.25
–VREFADC
Unit
Bits
10
LSB
LSB
10-Bit Operation
10-Bit Operation
Bits
(Plus 2-Bits for gain ranging) 2.2 V Ref.
LSB
LSB
10-Bit
10-Bit
See Table II
27 MHz Clock, fIN = 100 kHz
54 MHz Clock, fIN = 100 kHz
+VREFADC
62
50
dB
dB
±1
±2
44
Bits
LSB
LSB
dB
V
0
2 VREFADC
2
0.8
±1
10
2.4
0.4
10
30
8
3
4.33
2
V
V
µA
pF
ns
ns
50
30
7
0
1.235
1.100
V
V
1.4
NOTES
1
0°C to 70°C.
2
SHA gain = 1, half range for SHA gain = 2, see Table II.
3
Output delay measured from 50% of the rising edge of the clock to the 50% point of full scale transition.
Specifications subject to change without notice.
REV. PrB
–5–
Guaranteed Monotonic
27 MHz Clock
V
V
µA
pF
mA
%
V
kΩ
pF
ns
ns
0
Test Conditions
ISOURCE = 400 µA
ISINK = 3.2 mA
See Figure 16
RSET = 1.2 kΩ, RL = 300 Ω
IOUT = 0 mA
PRELIMINARY TECHNICAL DATA
ADV7202–SPECIFICATIONS
3.3 V SPECIFICATIONS
(AVDD/DVDD = 3.3 V ⴞ 5%, VREF = 1.235 V RSET = 1.2 k⍀, all specifications TMIN to TMAX unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
3.15
3.3
3.45
V
Test Conditions
1
POWER REQUIREMENTS
AVDD/DVDD
Normal Power Mode
IDAC2
IDSC3
IADC4
Sleep Mode
Current
PSU Rejection Ratio
DACs
Video ADC
Aux ADC
Power-Up Time
MPU PORT—I2C5
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
4
34
21
mA
mA
mA
RSET = 1.2 kΩ, RL = 300 Ω
100
µA
RSET = 1.2 kΩ, RL = 300 Ω
0.5
0.5
TBD
%/%
%/%
TBD
TBD
COMP = 0.1 µF
400
kHz
µs
µs
µs
0.01
0.01
TBD
TBD
0
0.6
1.3
0.6
0.6
100
300
300
0.6
µs
ns
ns
ns
µs
TBD
TBD
After this period the first clock is
generated.
Relevant for Repeated Start Condition
5, 6
MPU PORT—SPI
SCLOCK Frequency
SCLOCK High Pulsewidth, t21
SCLOCK Low Pulsewidth, t22
SI Data Setup Time, t20
SI Data Hold Time, t19
TBD
TBD
TBD
TBD
TBD
RESET Low Time
100
TBD
TBD
TBD
TBD
TBD
kHz
kHz
ns
ns
ns
ns
NOTES
1
All DACs and ADCs on.
2
IDAC is the DAC supply current.
3
IDSC is the digital core supply current.
4
IADC is the ADC supply current.
5
TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, as measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
6
See SPI timing diagram Figures 10 and 11.
Specifications subject to change without notice.
–6–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
3.3 V SPECIFICATIONS (AVDD/DVDD = 3.3 V ⴞ 5%, V
REF = 1.235 V RSET = 1.2 k⍀,
Parameter
Min
PROGRAMMABLE GAIN
AMPLIFIER
Video ADC Gain
all specifications TMIN to TMAX1 unless otherwise noted.)
Max
Unit
Condition2
+6
dB
Setup Conditions
TBD
3
0.5
µA
µA
mA
27
54
27
18
18
18
18
2
2
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
TBD
TBD
Clock Cycles
Clock Cycles
10
ns
Typ
–6
3
CLAMP CIRCUITRY
Clamp Off Leakage Current
Clamp Fine Source/Sink Current
Clamp Coarse Source/Sink Current
CLOCK CONTROL4
DACCLK0/1
DACCLK1
DACCLK1
Clock High Time, t10 (DACCLK0)
Clock Low Time, t11 (DACCLK0)
Clock High Time, t10 (DACCLK1)
Clock Low Time, t11 (DACCLK1)
Data Setup Time, t12
Data Hold Time, t13
Pipeline Delay5, t18
Video ADC
SAR
RESET CONTROL
RESET Low Time
Dual CLK Dual Edge Mode
Single Edge Dual Clock Mode
4 : 2 : 2 Mode
Dual Edge Dual Clock Mode
All Input Modes
NOTES
1
Temperature range T MIN to TMAX: 0oC to 70oC.
2
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.15 V to 3.45 V range.
3
External clamp capacitor = 0.1 µF.
4
TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤10 pF.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Specifications subject to change without notice.
REV. PrB
–7–
PRELIMINARY TECHNICAL DATA
ADV7202
ABSOLUTE MAXIMUM RATINGS 1
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DVDD to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Ambient Operating Temperature (TA) . . . . . . . . 0°C to 70°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Analog output short circuit to any power supply or common can be of an indefinite
duration.
ORDERING INFORMATION1
Model
Temperature Range
Package Description
Package Option
ADV7202
0°C to 70°C
64-Lead Plastic Quad Flatpack (LQFP)
ST-64
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7202 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
DAC_DATA8
DAC_DATA9
DAC_DATA7
DAC_DATA5
DVDD
DVSS
DAC_DATA6
DAC_DATA4
DACCLK0
DACCLK1
DAC_DATA2
DAC_DATA3
DAC_DATA1
SYNC_OUT
DAC_DATA0
SI_DATA9
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SYNC_IN 1
CLK/SCK 2
48 RESET
47 RSET
PIN 1
IDENTIFIER
LE/ALSB 3
46 VREFDAC
XTAL0 4
XTAL1 5
45 COMP
44 DAC0_OUT
AVDD_ADC 6
43 DAC1_OUT
AVSS_ADC 7
AIN1P 8
42 AVSDD_DAC
ADV7202
41 AVSS_DAC
TOP VIEW
(Not to Scale)
AIN1M 9
AIN2P 10
40 DAC2_OUT
39 DAC3_OUT
AIN12M 11
38 OSDIN0
AIN3P 12
AIN3M 13
37 OSDIN1
36 OSDIN2
AIN4P 14
AIN4M 15
AIN5P 16
35 DOUT0
34 DOUT1
33 DOUT2
–8–
DOUT5
DOUT4
DOUT3
DOUT7
DOUT6
DOUT8
OSDEN
DOUT9
CML
CAP2
CAP1
REFADC
AIN6P
AIN6M
SPI_SEL
AIN5M
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Input/
Output
1
SYNC_IN
I
2
CLK/SCK
I
3
LE/ALSB
I
4
XTAL0
I
5
XTAL1
O
6
7
8–19
20
AVDD_ADC
AVSS_ADC
AIN1–6
SPI_SEL
P
G
I
I
21
22
23, 24
25
26–35
36
37
38
39
40
41
42
43
44
45
REFADC
CML
CAP2, CAP1
OSDEN
DOUT[9:0]
OSDIN2
OSDIN1
OSDIN0
DAC3_OUT
DAC2_OUT
AVSS_DAC
AVDD_DAC
DAC1_OUT
DAC0_OUT
COMP
I/O
O
I
I
O
I
I
I
O
O
G
P
O
O
O
46
VREFDAC
I/O
47
RSET
I
48
49–52, 55, 56,
59–62
53
54
57, 58
63
RESET
DAC_DATA[9:0]
I
I
DVSS
DVDD
DAC_CLK[1:0]
SYNC_OUT
G
P
I
O
64
SI_SDA
I/O
REV. PrB
Function
This signal can be used to synchronize the updating of clamps. Polarity is programmable via I2C or SPI.
MPU Port Serial Interface Clock Input. If the SPI interface is enabled, this pin is
clock input. If the I2C interface is enabled, this pin is SCK.
If the SPI interface is enabled, this pin is Latch Enable. If the I2C interface is enabled, this pin is the ALSB Address Select Pin. This signal sets up the LSB of the
MPU address. MPU address = 2cH, ALSB = 0, MPU address = 2eH, ALSB = 1.
When this pin is tied high, the I2C filter is activated, which reduces noise on the
I2C interface. When this pin is tied low, the input bandwidth on the I2C lines is
increased.
Input Terminal for crystal oscillator or connection for external oscillator with
CMOS-compatible square wave clock signal.
Second Terminal for Crystal Oscillator. Not connected if external clock source
is used.
ADC Analog Supply Voltage (5 V or 3.3 V)
Ground for ADC Analog Supply
Analog Signal Inputs. Can be configured differentially or single-ended.
A high signal on the pin selects SPI MPU port serial operation; a low signal selects
I2C MPU port serial operation.
Internally generated Voltage Reference or programmable reference out.
Common-Mode Level for ADCs
ADC Capacitor Network
Enable data from OSDIN0–2 to be switched to the outputs when set to a logic high.
ADC data output
Third Input Channel for On-Screen Display
Second Input Channel for On-Screen Display
First Input Channel for On-Screen Display
General Purpose Analog Output
Analog Output. Can Be Used to Output CVBS, R or U
Ground for DAC Analog Supply
DAC Analog Supply Voltage (5 V or 3.3 V)
Analog Output. Can Be Used to Output CVBS, Y, G, or Luma.
Analog Output. Can Be Used to Output CVBS, V, B, or Chroma.
Compensation Pin for DACs. Connect 0.1µF capacitor from COMP pin to
AVDD_DAC.
DAC Voltage Reference Output Pin, Nominally 1.235 V. Can be driven by an
external voltage reference.
Used to control the amplitude of the DAC output current, 1200 Ω gives an I max
of 4.33 µA.
Master Reset (Asynchronous)
DAC Input Data for Four Video Rate DACs
Ground for Digital Core Supply
Analog Supply Voltage for Digital Core (5 V or 3.3 V)
DAC Clocks
Output Sync Signal, which goes to a high state while Cr data sample from a
YCrCb data stream or C data from a Y/C data stream is output on DOUT[9:0].
If the SPI interface is enabled, this pin is serial data In. If the I2C interface is
enabled, this pin is MPU Port Serial Data Input/Output.
–9–
PRELIMINARY TECHNICAL DATA
ADV7202
FUNCTIONAL DESCRIPTION
Analog Inputs
Digital Inputs
The ADV7202 has the capability of sampling up to five CVBS
video input signals, or two component YUV, or three S-Video
inputs. Eight auxiliary general-purpose inputs are also available.
Table I shows the analog signal input options available and programmable by I2C/SPI. When configured for auxiliary input
mode, the CVBS inputs are single-ended with the second differential input internally set to VREFADC. The resolution on the
front end digitizer is 12 bits; two bits (12 dB) are used for gain
and offset adjustment. The digitizer has a conversion rate of up
to 54 MHz. The eight auxiliary inputs can be used for system
monitoring, etc., and are sampled by a 843 kHz SAR ADC. The
analog input signal range will be dependent on the value of
VREFADC and the SHA gain see (Table II). Three on-screen
display inputs OSDIN[2:0] mux to the DAC outputs to enable
support for Picture-on-Picture applications.
The DAC digital inputs on the ADV7202 [9:0] are TTL-compatible. Data may be latched into the device in three different
modes programmable via I2C or SPI.
DAC Mode 1, single clock, single edge (see Figure 13) uses only
the rising edge of DAC_CLK1 to latch data into the device.
DAC_CLK0 is a data line that goes high to indicate that the data
is for DAC0. Subsequent data words go to the next DAC in
sequence.
DAC Mode 2, dual edge, dual clock (see Figure 14) clocks data
in on both edges of DAC_CLK0 and DAC_CLK1. Using this
option, data can is latched into the device at four times the
clock speed.
DAC Mode 3, 4:2:2 mode (see Figure 15). Using this option, 4:2:2
video data is latched in using DAC_CLK1, while DAC_CLK0 is used
as a data line that is brought to a high state when Cr data is input;
hence Y will appear on DAC1, Cr on DAC2, and Cb on DAC0.
Table I. Analog Input Signal Data
Register
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
SHA
Used
Description
CVBS in on AIN1
CVBS in on AIN2
CVBS in on AIN3
Reserved
CVBS in on AIN5
CVBS in on AIN6
Y/C, Y on AIN1, C on AIN4
Y/C, Y on AIN2, C on AIN3
YUV, Y on AIN2, U on AIN3,
V on AIN6
CVBS on AIN1 and 8 AUX.
I/Ps AIN3–6*
CVBS on AIN2 and 8 AUX.
I/Ps AIN3–6*
0
0
1
1
0
2
0, 1
0, 1
0, 1, 2
Analog Outputs
Sync_Out
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 2
Figure 2
Figure 3
0, 1, 2 Figure 1
0, 1, 2 Figure 1
*AUX inputs are single-ended. All other inputs are differential.
Table II. Analog Input Signal Range
I/P
Mode
SHA
VREFOUT (V) Gain
Input Range (V)
Min
Typ
Max
Differential
Differential
Differential
Differential
Single-ended
Single-ended
Single-ended
Single-ended
2.2
2.2
1.1
1.1
2.2
2.2
1.1
1.1
–2.2
–1.1
–1.1
–0.55
0
1.1
0
0.55
2.2
1.1
1.1
0.55
4.4
3.3
2.2
1.65
1
2
1
2
1
2
1
2
0
0
0
0
2.2
2.2
1.1
1.1
Analog Outputs [DAC0–3] consist of four 10-bit DACs that run at
up to 54 MHz or up to 108 MHz if only DAC0 is used. These outputs
can be used to output CVBS, S-Video, Component YCrCb, and RGB.
Digital Outputs
Video data will be clocked out on DOUT[9:0] during the rising
edge of XTAL0. See Figure 17. Auxiliary data can be read out
vial2C compatible MPU port.
I2C and SPI Control
The ADV7202 is both I2C- and SPI-compatible. It should be
noted though that only register write applications are possible
with SPI control. I2C operation allows both reading and writing
of system registers. Its operation is explained in detail in the MPU
Port Description section. A logic high level on the SPI_SEL line
selects SPI MPU operation. In this mode the first eight bits of
the 16-bit word on the SI data line will select the register address
and the next eight bits are the value to be programmed into the
register, i.e., the register data. See Figure 10. Latch Enable (LE)
goes low while valid address or data information is present. Figure
10 shows latch enable low for the entire 16 bits of address and
data information. As shown in Figure 11, the register eight-bit data
information does not always have to be clocked in directly after
the address. LE may go high and then low again when valid data
is available. If LE goes low for anything less than eight cycles of
SCLK, the SPI MPU will reset (not register values); hence this
method may be used to initiate a start condition.
NOTE
Fclk/32, 843kHz for nominal 27 Mhz
–10–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
Video Clamping and AGC Control
When Analog signal clamping is required the input signal should
be AC coupled to the input via a capacitor, the clamping control
is via the MPU port. The AGC is implemented digitally. For
correct operation the user must program the clamp value to which
the signal has been clamped into the ADV7202 I2C Register. This
allows the user to specify which signal level is unaffected by the
AGC. The digital output signal will be a function of the ADC
output, the AGC Gain, and the Clamp Level, and can be represented as follows,
[
]
D _OUT = ADC Gain × ( ADC – Clamp Level ) + Clamp Level (1)
D_OUT will be a 10-bit number (0–1023), the AGC Gain
defaults to 2 and can have a value between 0 to 7.99. The Clamp
Level is a 10-bit number (0–1023) although only the top eight
bits of clamp level are specified in the I2C Register; the ADC
value can be regarded as a 10-bit number (0–1023) for the
equation. It should be noted that the ADC resolution is 12 bits.
The above equation is used to give a basic perspective, and is
mathematically correct.
The first three bits give the integer value 3, hence these will be
set to ‘0 1 1.’ The remaining nine bits will have to be set to give
the fractional value 0.65, 512 ⫻ 0.65 = 333 = ‘10100110 1.’
From Equation (2) it can be seen that the Clamp Level is
taken from the signal before AGC is applied and then added on
again afterwards; hence, if the AGC Gain is set to a value of
one, the result would be as follows,
(AGC Gain = 1)
D_OUT = ADC - Clamp Level + Clamp Level = ADC
FUNCTIONAL DESCRIPTION
Clamp and AGC Control
The ADV7202 has a front end 3-channel clamp control. In
order to perform an accurate AGC gain operation, it is necessary to know to what level the user is clamping the black level;
this value is programmable in Clamp Register 0 CR00–CR07.
Each channel has a fine and coarse clamp; the clamp direction
and its duration are programmable. Synchronization of the clamps
and AGC to the input signal is possible using the SYNC_IN control pin and setting mode register CR14 to Logic Level “1.” Using
this method, it is possible to ensure that AGC and clamping are
only applied outside the active video area.
When the clamps are operational, the operation described by
Equation (1) is how the ADV7202 ensures that the level to
which the user is clamping is unaffected by the AGC loop.
When no clamps are operational, the operation should be
regarded as a straightforward gain-and-level shift.
Control Signals
The function and operation of the SYNC_IN signal is described
in the Clamp Control section. The SYNC_OUT will go high
while Cr data from a YCrCb data stream or C data from a Y/C
data stream has been output on DOUT[9:0]. See Figure 1 to
Figure 3.
Equation (1) maps the ADC input voltage range to its output.
AGC Gain
The AGC Gain can be set to a value from 0 to 7.9. The AGC
Gain Register holds a 12-bit number that corresponds to the
required gain. The first three MSBs hold the gain integer value
while the remaining nine bits hold the gain fractional value.
Example: The user requires a gain of 3.65.
I2C Filter
A selectable internal I2C filter allows significant noise reduction
on the I2C interface. In setting ALSB high, the input bandwidth
on the I2C lines is reduced and pulses of less than 50 ns are not
passed to the I2C controller. Setting ALSB low allows greater
input bandwidth on the I2C lines.
XTAL0
DAC_DATA [9:0]
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
SYNC_OUT
Figure 1. SYNC_OUT Output Timing, CVBS Input
XTAL0
DAC_DATA [9:0]
Y
C
Y
C
Y
C
SYNC_OUT
Figure 2. SYNC_OUT Output Timing, Y/C (S-VIDEO) Input
REV. PrB
(2)
–11–
Y
PRELIMINARY TECHNICAL DATA
ADV7202
XTAL0
DAC_DATA [9:0]
CR
Y
CB
Y
CR
Y
CB
SYNC_OUT
Figure 3. SYNC_OUT Output Timing, YCrCb Input
MPU PORT DESCRIPTION
A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7202 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two inputs,
Serial Data (SDA) and Serial Clock (SCL), carry information
between any device connected to the bus. Each slave device is
recognized by a unique address. The ADV7202 has four possible slave addresses for both read and write operations. These
are unique addresses for each device and are illustrated in
Figure 4. The LSB sets either a read or write operation. Logic
Level “1” corresponds to a read operation, while Logic Level
“0” corresponds to a write operation. A1 is set by setting the
ALSB pin of the ADV7202 to Logic Level “0” or Logic Level
“1.” When ALSB is set to “0,” there is greater input bandwidth
on the I2C lines, which allows high-speed data transfers on this
bus. When ALSB is set to “1,” there is reduced input bandwidth on the I2C lines, which means that pulses of less than
50 ns will not pass into the I2C internal controller. This mode is
recommended for noisy systems.
0
0
1
0
1
1
A1
The ADV7202A acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the
device address and the second byte as the starting subaddress.
The subaddresses auto-increment, allowing data to be written to
or read from the starting subaddress. A data transfer is always
terminated by a Stop condition. The user can access any unique
subaddress register on a one-by-one basis without updating all
the registers.
Stop and Start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should only issue one Start condition, one Stop condition,
or a single Stop condition followed by a single Start condition. If
an invalid subaddress is issued by the user, the ADV7202 will
not issue an acknowledge and will return to the idle condition. If
in auto-increment mode, the user exceeds the highest subaddress,
the following action will be taken:
X
ADDRESS
CONTROL
SET UP BY
ALSB
1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDA line is not
pulled low on the ninth pulse.
READ/WRITE
CONTROL
0
1
DISABLED
ENABLED
Figure 4. Slave Address
To control the various devices on the bus, the following protocol must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the Start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are tranferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
Acknowledge Bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
is where the device monitors the SDA and SCL lines waiting for
the Start condition and the correct transmitted address. The R/W
bit determines the direction of the data.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7202, and the part will return to the
idle condition.
Figure 5 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
SDATA
SCLOCK
–12–
S
1–7
8
9
1–7
8
9
START ADDR R/W ACK SUBADDRESS ACK
1–7
DATA
8
9
P
ACK
STOP
Figure 5. Bus Data Transfer
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
Figure 6 shows bus write and read sequences.
WRITE
SEQUENCE
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
A(S)
LSB = 0
READ
SEQUENCE
S
SLAVE ADDR
A(S)
S = START BIT
P = STOP BIT
A(S)
DATA
P
LSB = 1
SUB ADDR
A(S)
S
SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
A(M)
DATA
P
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 6. Write and Read Sequence
t5
t3
t3
SDA
t6
t1
SCL
t2
t7
t4
t8
Figure 7. I2C MPU Port Timing Diagram
t 12
DAC_CLK1
t 10
t 12 – SETUP TIME
t 13 – HOLD TIME
t 10 – CLOCK HIGH TIME
t 11 – CLOCK LOW TIME
t 13
t 11
DATA [9:0]
DAC_CLK0
DATA
DATA
Figure 8. Input Data Format Timing Diagram Single Clock
t 12
t 12
t 13
DAC_CLK0
DAC_CLK1
DAC_DATA[7:0]
DATA
t 13
t 12
t 13
t 13
t 12
t 11
t 10
Figure 9. Input Data Format Timing Diagram Dual Clock
REV. PrB
DATA
DATA
DATA
–13–
DATA
t10 – CLOCK HIGH TIME
t11 – CLOCK LOW TIME
t12 – DATA SETUP TIME
t13 – DATA HOLD TIME
PRELIMINARY TECHNICAL DATA
ADV7202
8 CLOCK CYCLES
8 CLOCK CYCLES
SCLK
LE
ADDRESS [7:0]
DATA [7:0]
SI
Figure 10. SPI Timing Mode 1
8 CLOCK CYCLES
8 CLOCK CYCLES
SCLK
LE
SI
ADDRESS [7:0]
DATA [7:0]
NOTE: TAKING LE LOW FOR < 8 CYCLES OF SCLK WILL
RESET THE SPI MPU INTERFACE.
Figure 11. SPI Timing Mode 2
t 19
t 21
t 20
SCLK
t 22
SI/LE
Figure 12. SPI Timing Diagram
–14–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
DIGITAL DATA INPUT TIMING DIAGRAMS
A1
A0
A2
A3
DAC_CLK1
At A3, NEW DAC0 DATA
IS CLOCKED IN AND A0,
A1, AND A3 ARE SENT TO
THE DACs. DATA APPEARS
AT THE OUTPUT DACs TWO
CLOCK CYCLES AFTER
BEING SENT TO THE DACs.
DAC_CLK0
DAC_DATA [9:0]
DAC0
DAC1
DAC2
DAC0
DAC1
DAC2
DAC0
Figure 13. DAC Mode 1, Single Clock, Single Edge Input Data Format Timing Diagram. As with Mode 1, DAC_CLK0 is a
Data Line that Indicates the Data is for DAC0. Above Example Shows Three DAC Usage.
A1
A2
A3
A4
A1 DAC1 DATA CLOCKED IN.
DAC_CLK0
A2 DAC2 DATA CLOCKED IN.
A3 DAC3 DATA CLOCKED IN.
A4 DAC0 DATA FOR THE NEXT
PIXEL AND THE PREVIOUS
FOUR CLOCKED OUT TO DACs.
DAC_CLK1
DAC_DATA [9:0]
DAC1
DAC2
DAC3
DAC0
DAC1
DAC2
DAC3
NOTE
DATA WILL BE CLOCKED TO THE
DACs TWO CLOCK CYCLES
AFTER A4.
DAC0
Figure 14. DAC Mode 2, Dual Clock, Dual Edge Input Data Format Timing Diagram
A1
A2
A3
A4
DAC_CLK1
AT A4, PREVIOUS A0, A2,
AND A3 DATA ARE SENT
TO THE DACs. AT A2, A1
DATA APPEARS AT THE
OUTPUT DACs TWO
CLOCK CYCLES AFTER
BEING SENT TO THE DACs.
DAC_CLK0
DAC_DATA [9:0]
DAC0
DAC1
DAC2
DAC1
DAC0
DAC1
DAC2
Figure 15. DAC Mode 3, 4:2:2 Input Data Format Timing Diagram
t 15
t 14
XTAL0
t 15
OUTPUT
ADC O/P DOUT[9:0]
SYNC_OUT, SYNC_IN
DATA
Figure 16. Digital O/P Timing
REV. PrB
–15–
DATA
t14 – ACCESS TIME
t15 – HOLD TIME
PRELIMINARY TECHNICAL DATA
ADV7202
XTAL0
DATA [9:0]
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 17. Standard Mode Digital Data O/P Format
REGISTER ACCESSES
Subaddress Register (SR7–SR0)
The MPU can write to or read from all of the registers of the
ADV7202 except the Subaddress Registers which are writeonly. The Subaddress Register determines which register the
next read or write operation accesses. All communications with
the part through the bus start with an access to the Subaddress
Register. A read/write operation is then performed from/to the
target address which then increments to the next address until a
Stop command on the bus is performed.
The Communications Register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation
takes place.
REGISTER PROGRAMMING
These bits are set up to point to the required starting address.
Figure 19 shows the various operations under the control of the
Subaddress Register. “0” should always be written to SR7.
Register Select (SR6–SR0)
The following section describes the functionality of each register. All registers can be read from as well as written to.
SR7
SR6
SR5
SR3
SR4
SR2
SR1
SR0
ADV7202 SUBADDRESS REGISTER
ADDRESS
SR6 SR5
SR4
SR3
SR2
SR1
SR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
ACG REGISTER 0
AGC REGISTER 1
CLAMP REGISTER 0
CLAMP REGISTER 1
CLAMP REGISTER 2
CLAMP REGISTER 3
TIMING REGISTER
VREF ADJUST REGISTER
RESERVED
RESERVED
RESERVED
RESERVED
AUX REGISTER 0
AUX REGISTER 1
AUX REGISTER 2
AUX REGISTER 3
AUX REGISTER 4
AUX REGISTER 5
AUX REGISTER 6
AUX REGISTER 7
Figure 19. Subaddress Registers
–16–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
External Reference Enable (MR01)
Setting this bit to “1” enables an external voltage reference for
the ADC.
Figure 20 shows the various operations under the control of
Mode Register 0.
Voltage Reference Power-Down (MR02)
MR0 BIT DESCRIPTION
ADC Reference Voltage (MR00)
ADC Power-Down (MR03)
Setting this bit to “1” causes the internal ADC voltage reference to
power down.
Setting this bit to “1” causes the video rate ADC to power down.
This control bit is used to select the ADC reference voltage.
When this bit is set to “0,” a reference voltage of 1.1 V is
selected. When the bit is set to “1,” a reference voltage of 2.2 V
is selected.
Power-Down (MR04)
Setting this bit to “1” puts the device into power-save mode.
Reserved (MR05–07)
“0” must be written to these bits.
MR7
MR6
MR5
MR4
MR3
MR2
ADC REF
VOLTAGE
VREF
POWER-DOWN
POWER-DOWN
MR0
MR2
MR14
0
1
MR0
MR1
0
1
NORMAL
POWER-DOWN
ADC
POWER-DOWN
MR7–MR5
1.1V
2.2V
EXT REF
ENABLE
MR3
ZERO MUST BE
WRITTEN TO
THESE BITS
0
1
NORMAL
POWER-DOWN
MR1
0
1
NORMAL
POWER-DOWN
0
1
INTERNAL
EXTERNAL
Figure 20. Mode Register 0
Dual Edge Clock (MR14)
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Setting this bit to “1” allows data to be read into the DACs on
both edges of the clock; hence, data may be read in at twice the
clock frequency. See Figure 21. If this bit is set to “0,” the data
will only be strobed on the rising edge of the clock.
Figure 21 shows the various operations under the control of
Mode Register 1.
Dual Clock (MR15)
MR1 BIT DESCRIPTION
DAC0 Control (MR10)
Setting this bit to “1” allows the use of two clocks to strobe data
into the DACs. It is possible to clock data in with only one clock
and use the second clock to contain timing information.
Setting this bit to “0” enables DAC 0; otherwise, this DAC is
powered down.
4:2:2 Mode (MR16)
DAC1 Control (MR11)
Setting this bit to “0” enables DAC 1; otherwise, this DAC is
powered down.
Setting this bit to “1” enables data to be input in 4:2:2 format
(see Figure 21). 4:2:2 mode will only work if TR14 and TR15
register bits are set to zero.
DAC2 Control (MR12)
DAC Input Invert (MR17)
Setting this bit to “0” enables DAC 2; otherwise, this DAC is
powered down.
Setting this bit to “1” causes the input data to the DACs to be
inverted allowing for an external inverting amplifier.
DAC3 Control (MR13)
Setting this bit to “0” enables DAC 3; otherwise, this DAC is
powered down.
MR17
MR16
MR15
DAC I/P INVERT
MR13
DISABLE
ENABLE
0
1
4:2:2 MODE
MR16
SINGLE EDGE
DUAL EDGE
0
1
DUAL CLOCK
0
1
MR10
NORMAL
POWER-DOWN
DAC3 CONTROL
MR13
SINGLE CLK
DUAL CLK
0
1
–17–
0
1
NORMAL
POWER-DOWN
DAC1 CONTROL
MR11
NORMAL
POWER-DOWN
Figure 21. Mode Register 1
REV. PrB
DAC0 CONTROL
MR12
MR15
DISABLE
ENABLE
MR10
MR11
DAC2 CONTROL
MR14
0
1
MR12
DUAL EDGE CLOCK
MR17
0
1
MR14
0
1
NORMAL
POWER-DOWN
PRELIMINARY TECHNICAL DATA
ADV7202
MODE REGISTER 2
MR2 (MR20–MR27)
(Address (SR4–SR0) = 02H)
SHA1 Control (MR25)
Figure 22 shows the various operations under the control of
Mode Register 2.
SHA2 Control (MR26)
Setting this bit to “0” enables SHA1; otherwise, this SHA is
powered down.
Setting this bit to “0” enables SHA2; otherwise, this SHA is
powered down.
MR1 BIT DESCRIPTION
Analog Input Configuration (MR20–MR23)
AUX Control (MR27)
This control selects the analog input configuration, up to six
CVBS input channels, or two component YUV, or three S-Video
and eight auxiliary inputs. See Figure 22 for details.
Setting this bit to “0” enables the auxiliary ADC; otherwise, this
Aux ADC is powered down.
SHA0 Control (MR24)
Setting this bit to “0” enables SHA0; otherwise, this SHA is
powered down (SHA = Sample and Hold Amplifier).
MR27
MR26
MR25
AUX CONTROL
MR24
MR23
MR22
SHA0 CONTROL
MR27
ANALOG INPUT CONFIGURATION*
MR24
0
1
NORMAL
POWER-DOWN
0
1
SHA2 CONTROL
NORMAL
POWER-DOWN
MR23 MR22 MR21 MR20
0
0
0
0
0
0
0
0
1
1
1
SHA1 CONTROL
MR26
0
1
MR20
MR21
MR25
NORMAL
POWER-DOWN
0
1
NORMAL
POWER-DOWN
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
CVBS IN ON AIN1
CVBS IN ON AIN2
CVBS IN ON AIN3
RESERVED
CVBS IN ON AIN5
CVBS IN ON AIN6
Y/C IN ON AIN1, AIN4
Y/C IN ON AIN2, AIN3
YUV IN ON AIN2, AIN3, AIN6
CVBS IN ON AIN1, 8 AUX INPUTS
CVBS IN ON AIN2, 8 AUX INPUTS
*SEE FIGURE : XX
Figure 22. Mode Register 2
MODE REGISTER 3
MR3 (MR30–MR37)
(Address (SR4–SR0) = 03H)
Voltage Clamp (MR33)
Figure 23 shows the various operations under the control of
Mode Register 3.
Setting this bit to “1” puts the digital outputs into high impedance.
Setting this bit to “1” will enable the voltage clamps.
Output Enable (MR34)
MR3 BIT DESCRIPTION
Clamp Current (MR30)
SYNC Polarity (MR35)
Setting this bit to “1” enables differential mode for the analog
inputs; otherwise, the inputs are single ended. See Figure 23.
This bit controls the polarity of the SYNC_IN pin. If the bit
is set to “0,” a logic low pulse corresponds to H-Sync. If the bit
is “1,” a logic high pulse corresponds to H-Sync. This sync in
pulse can then be used to control the synchronization of AGC/
Clamping, see AR12.
SHA Gain (MR32)
Reserved (MR36–MR37)
Setting this bit to “0” enables SHA gain of 1. If the bit is set to
“1,” the SHA gain is 2. The SHA gain will limit the input signal
range, see Figure 23.
Zero must be written to both these registers.
Setting this bit to “1” enables the doubling of all clamp currents.
Analog Input Mode (MR31)
MR37
MR36
MR35
MR36–MR37
MR34
MR33
MR32
OUTPUT ENABLE
SHA GAIN
MR34
ZERO MUST BE
WRITTEN TO
THESE REGISTERS
0
1
CLAMP CURRENT
MR32
NORMAL
HIGH Z
0
1
SYNC POLARITY
MR35
0
1
MR30
MR31
MR30
1
2
VOLTAGE CLAMP
MR33
LOW
HIGH
0
1
0
1
NORMAL
DOUBLE
ANALOG INPUT
MR31
OFF
ON
0
1
SINGLE-ENDED
POWER-DOWN
Figure 23. Mode Register 3
–18–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
AGC REGISTER 0
AR0 (AR00–AR07)
(Address (SR4–SR0) = 04H)
AGC REGISTER 0
AR1 (AR08–AR15)
(Address (SR4–SR0) = 05H)
Figure 24 shows the various operations under the control of
AGC Register 0.
Figure 24 shows the various operations under the control of
AGC Register 1.
AR0 BIT DESCRIPTION
AGC Multiplier (AR00–AR07)
AR1 BIT DESCRIPTION
AGC Multiplier (AR08–AR11)
This register holds the last eight bits of the 12-bit AGC
multiplier word.
These registers hold the first four bits of the 12-bit AGC
multiplier word.
AGC Sync Enable (AR12)
Setting this bit to “1” forces the AGC to wait until the next sync
pulse before switching on.
Reserved (AR13–AR15)
Zero must be written to these registers.
AR07
AR15
AR14
AR13
AR06
AR12
AR11
AR05
AR10
AR04
AR03
AR09
AR02
AR01
AR00
AR08
ACG MULTIPLIER
AR15–AR13
ZERO MUST BE
WRITTEN TO
THESE REGISTERS
ACG SYNC ENABLE
AR11–AR00
AR12
0
1
12-BIT ACG MULTIPLIER,
HOLDS THE LSB, AR11
THE MSB
OFF
ON
Figure 24. AGC Registers 0–1
REV. PrB
–19–
PRELIMINARY TECHNICAL DATA
ADV7202
CLAMP REGISTER 0
CR1 BIT DESCRIPTION
Fine Clamp On Time (CR10–CR12)
CR0 (CR00–CR07)
There are three fine clamp circuits on the chip. This I2C/SPI
word controls the number of clock cycles for which the fine
clamps are switched on per video line. The clamp is switched on
after a SYNC pulse is received on the SYNC_IN pin, provided
the relevant enabling bit is set (see CR16).
(Address (SR4–SR0) = 06H)
Figure 25 shows the various operations under the control of
Clamp Register 0.
CR0 BIT DESCRIPTION
Clamp Level/4 (CR00–CR07)
In order to perform an accurate AGC gain operation, it is
necessary to know to what level the user is clamping the black
level. This black level is then subtracted from the 10-bit ADC
output before gaining. It is then added on again afterwards. It
should be noted that this register is eight bit and will hold the
value of Clamp Value/4.
Coarse Clamp On Time (CR13–CR15)
There are three coarse clamp circuits on the chip. This I2C
word controls the number of clock cycles for which the fine
clamps are switched on per video line. The clamp is switched on
after a SYNC pulse is received on the SYNC_IN pin, provided
the relevant enabling bit is set (see CR16).
Synchronize Clamps (CR16)
CLAMP REGISTER 1
CR1 (CR10–CR17)
(Address (SR4–SR0) = 07H)
Setting this bit to “1” forces the clamps to wait until the next
sync pulse before switching on.
Reserved (CR17)
Figure 26 shows the various operations under the control of
Clamp Register 1.
CR07
CR06
CR05
Zero must be written to this bit.
CR04
CR03
CR02
CR00
CR01
CLAMP LEVEL
CR07–CR00
8-BIT [7:0] CLAMP
LEVEL, CR00 HOLDS THE
LSB, CR07 THE MSB
Figure 25. Clamp Register 0
CR17
CR16
CR17
ZERO MUST BE
WRITTEN TO
THIS BIT
SYNCHRONIZE
CLAMPS
CR16
0
1
OFF
ON
CR15
CR14
CR13
CR12
CR10
CR11
COARSE CLAMP ON TIME
CR15 CR14 CR13
FINE CLAMP ON TIME
CR12 CR11 CR10
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 CLOCK CYCLES
4 CLOCK CYCLES
8 CLOCK CYCLES
16 CLOCK CYCLES
32 CLOCK CYCLES
64 CLOCK CYCLES
128 CLOCK CYCLES
256 CLOCK CYCLES
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 CLOCK CYCLES
4 CLOCK CYCLES
8 CLOCK CYCLES
16 CLOCK CYCLES
32 CLOCK CYCLES
64 CLOCK CYCLES
128 CLOCK CYCLES
256 CLOCK CYCLES
Figure 26. Clamp Register 1
–20–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
CLAMP REGISTER 2
CR2 (CR20–CR27)
(Address (SR4–SR0) = 08H)
Fine Clamp 1 ON/OFF (CR23)
This bit switches fine clamp number 2 on for the prescribed
number of clock cycles (CR10–CR12).
Figure 27 shows the various operations under the control of
Clamp Register 2.
Fine Clamp 2 Up/Down (CR24)
This bit controls the direction of fine clamp number 3, valid
only if the clamp is enabled.
CR2 BIT DESCRIPTION
Fine Clamp 0 Up/Down (CR20)
Fine Clamp 2 ON/OFF (CR25)
This bit controls the direction of fine clamp number 1, valid
only if the clamp is enabled.
This bit switches fine clamp number 3 on for the prescribed
number of clock cycles (CR10–CR12).
Fine Clamp 0 ON/OFF (CR21)
Reserved (CR26–CR27)
This bit switches fine clamp number 1 on for the prescribed
number of clock cycles (CR10–CR12).
Zero must be written to these registers.
Fine Clamp 1 Up/Down (CR22)
This bit controls the direction of fine clamp number 2, valid
only if the clamp is enabled.
CR27
CR26
CR25
CR24
CR23
FINE CLAMP 2 UP/DOWN
CR27–CR26
CR20
CR21
FINE CLAMP 1 UP/DOWN
CR24
ZERO MUST BE
WRITTEN TO
THESE REGISTERS
CR22
FINE CLAMP 0 UP/DOWN
CR22
0
1
DOWN
UP
CR20
0
1
DOWN
UP
0
1
FINE CLAMP 2 ON/OFF
FINE CLAMP 1 ON/OFF
FINE CLAMP 0 ON/OFF
CR25
CR23
CR21
0
1
OFF
ON
0
1
OFF
ON
0
1
DOWN
UP
OFF
ON
Figure 27. Clamp Register 2
CLAMP REGISTER 3
CR3 (CR30–CR37)
(Address (SR4–SR0) = 09H)
Coarse Clamp 1 Up/Down (CR32)
Figure 28 shows the various operations under the control of
Clamp Register 3.
Coarse Clamp 1 ON/OFF (CR33)
This bit controls the direction of coarse clamp number 2, valid
only if the clamp is enabled.
This bit switches coarse clamp number 2 on for the prescribed
number of clock cycles (CR13–CR15).
CR3 BIT DESCRIPTION
Coarse Clamp 0 Up/Down (CR30)
Coarse Clamp 2 Up/Down (CR34)
This bit controls the direction of coarse clamp number 1, valid
only if the clamp is enabled.
This bit controls the direction of coarse clamp number 3, valid
only if the clamp is enabled.
Coarse Clamp 0 ON/OFF (CR31)
Coarse Clamp 2 ON/OFF (CR35)
This bit switches coarse clamp number 1 on for the prescribed
number of clock cycles (CR13–CR15).
This bit switches coarse clamp number 3 on for the prescribed
number of clock cycles (CR13–CR15).
Reserved (CR36–CR37)
Zero must be written to these registers.
CR36
CR37
CR35
CR34
CR33
COARSE CLAMP 2 UP/DOWN
CR37–CR36
ZERO MUST BE
WRITTEN TO
THESE REGISTERS
0
1
CR30
DOWN
UP
0
1
DOWN
UP
COARSE CLAMP 2 ON/OFF
COARSE CLAMP 1 ON/OFF
COARSE CLAMP 0 ON/OFF
CR35
CR33
CR31
0
1
OFF
ON
0
1
OFF
ON
Figure 28. Clamp Register 3
REV. PrB
COARSE CLAMP 0 UP/DOWN
CR32
DOWN
UP
CR30
CR31
COARSE CLAMP 1 UP/DOWN
CR34
0
1
CR32
–21–
0
1
OFF
ON
PRELIMINARY TECHNICAL DATA
ADV7202
TIMING REGISTER
TR (TR00–TR07)
(Address (SR4–SR0) = 0AH)
Duty Cycle Equalizer (TR03)
When this bit is set to “1,” the clock duty cycle equalizer circuit
is active. This will only have an effect on the ADC operation.
The digital core clock will not be affected.
Figure 29 shows the various operations under the control of the
Timing Register.
Clock Delay (TR05–TR06)
TR BIT DESCRIPTION
Crystal Oscillator Circuit (TR00)
Using these two bits, it is possible to insert a delay in the clock
signal to the digital core. These bits control the insertion of
the delay.
If this bit is set to “0,” the internal oscillator circuit will be
disabled. Disabling the oscillator circuit is possible when an
external clock module is used, thus, saving power.
Reserved (TR02, TR04, TR07)
Zero must be written to the bits in these registers.
ADC Bias Currents (TR01)
If this bit is set to “1,” all analog bias currents will be doubled.
TR07
TR06
TR05
TR04
TR03
TR02
CRYSTAL
OSC. CKT
TR07
TR04
TR02
ZERO MUST BE
WRITTEN TO
THIS BIT
ZERO MUST BE
WRITTEN TO
THIS BIT
ZERO MUST BE
WRITTEN TO
THIS BIT
DUTY CYCLE
EQUALIZER
CLOCK DELAY
TR01
TR06 TR05
0
0
1
1
0
1
0
1
0
1
0ns
4ns
6ns
8ns
TR00
TR01
TR00
0
1
DISABLE
ENABLE
ADC BIAS
CURRENTS
TR01
INACTIVE
ACTIVE
0
1
NORMAL
DOUBLE
Figure 29. Timing Register 0
VREF ADJUST REGISTER
VR (VR00–VR07)
(Address (SR4–SR0) = 0AH)
Reserved (VR01–VR03)
Figure 30 shows the various operations under the control of the
VREF Adjust Register.
By setting the value of this 3-bit word, it is possible to trim the
ADC internal voltage reference VREFADC.
Zero must be written to these registers.
Reference Voltage Adjust (VR04–VR06)
VR BIT DESCRIPTION
Reserved (VR00)
Reserved (VR07)
Zero must be written to this register.
This register is reserved and “1” must be written to this bit.
VR07
VR06
VR05
VR04
VR07
VR03
VR02
VR03–VR01
ZERO MUST BE
WRITTEN TO
THIS BIT
ZERO MUST BE
WRITTEN TO
THESE BITS
VR01
VR00
VR00
ONE MUST BE
WRITTEN TO
THIS BIT
ADC REFERENCE VOLTAGE ADJUST
VR06 VR05
VR04
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
DEFAULT NOMINAL
+14mV
+28mV
+42mV
–14mV
–28mV
–42mV
–56mV
Figure 30. ADC VREF Register
–22–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
AUXILIARY MONITORING REGISTERS
AU (AU00–AU07)
(Address (SR4–SR0) = 10H)
There are eight Auxiliary Monitoring Registers. These registers
are read-only; when the device is configured for auxiliary
inputs, they will display a value corresponding to the converted
AU07
AU06
AU05
AU04
auxiliary input. Auxiliary Register “0” will contain the value of
the converted auxiliary “0” input, auxiliary register “1” the
value of the converted auxiliary “1” input, and so on to auxiliary
register 7.
AU03
AU02
AU01
AU00
AU09
AU08
AU17
AU16
AU25
AU24
AUX REGISTER0
AU07–AU00
8-BIT [7:0] VALUE
CORRESPONDING TO
AUX0 INPUT VALUE
Figure 31. AUX Register 0
AU15
AU14
AU13
AU12
AU11
AU10
AUX REGISTER1
AU15–AU08
8-BIT [7:0] VALUE
CORRESPONDING TO
AUX1 INPUT VALUE
Figure 32. AUX Register 1
AU23
AU22
AU21
AU20
AU19
AU18
AUX REGISTER2
AU23–AU16
8-BIT [7:0] VALUE
CORRESPONDING TO
AUX2 INPUT VALUE
Figure 33. AUX Register 2
AU31
AU30
AU29
AU28
AU27
AU26
AUX REGISTER3
AU31–AU24
8-BIT [7:0] VALUE
CORRESPONDING TO
AUX3 INPUT VALUE
Figure 34. AUX Register 3
REV. PrB
–23–
PRELIMINARY TECHNICAL DATA
ADV7202
AU39
AU38
AU37
AU36
AU35
AU34
AU33
AU32
AU41
AU40
AU49
AU48
AU57
AU56
AUX REGISTER4
AU39–AU32
8-BIT [7:0] VALUE
CORRESPONDING TO
AUX4 INPUT VALUE
Figure 35. AUX Register 4
AU47
AU46
AU45
AU44
AU43
AU42
AUX REGISTER5
AU47–AU40
8-BIT [7:0] VALUE
CORRESPONDING TO
AUX5 INPUT VALUE
Figure 36. AUX Register 5
AU55
AU54
AU53
AU52
AU51
AU50
AUX REGISTER6
AU55–AU48
8-BIT [7:0] VALUE
CORRESPONDING TO
AUX6 INPUT VALUE
Figure 37. AUX Register 6
AU63
AU62
AU61
AU60
AU59
AU58
AUX REGISTER7
AU63–AU56
8-BIT [7:0] VALUE
CORRESPONDING TO
AUX7 INPUT VALUE
Figure 38. AUX Register 7
–24–
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
CLAMP CONTROL
The clamp control has 2 modes of operation, if the Synchronize
clamp control bit CR16 (bit-6 address 07h) is set to on the
clamps that are enabled will be switched on for the programmed
time when triggered by the Sync_in control signal, this control
signal is edge detected and its polarity can be set by MR35 (bit-5
address 03h). If the Synchronize clamp control bit is set to zero,
when enabled each clamp will switch on for the programmed time,
the enabled signal is edge detected hence the bit must first be
reset to zero before the next enable signal can be implemented.
DAC TERMINATION AND LAYOUT CONSIDERATIONS
The ADV7202 contains an on-board voltage reference. The
VREF pin is normally terminated to AVDD through a 0.1 µF
capacitor when the internal VREF is used. Alternatively, the
ADV7202 can be used with an external VREF (AD589).
Resistor RSET is connected between the RSET pin and AVSS
and is used to control the amplitude of the DAC output current.
IMAX = 5.196/Rset Amps
Therefore, a recommended RSET value of 1200 Ω will enable
an IMAX of 4.43 mA. VMAX = Rload × IMAX, Rload should have a
value of 300 Ω.
The ADV7202 has four analog outputs—DAC0, DAC1, DAC2,
and DAC3. The DACs must be used with external buffer circuits
in order to provide sufficient current to drive an output device.
Suitable op amps are the AD8009, AD8002, AD8001, or AD8057.
PC BOARD LAYOUT CONSIDERATIONS
The ADV7202 is optimally designed for lowest noise performance,
both radiated and conducted noise. To complement the excellent noise performance of the ADV7202, it is imperative that
great care be given to the PC board layout.
The layout should be optimized for lowest noise on the ADV7202
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of AVDD, AVSS, DVDD, and DVSS pins
should be kept as short as possible to minimize inductive ringing.
It is recommended that a 4-layer printed circuit board be
used, with power and ground planes separating the layer of the
signal carrying traces of the components and solder side layer.
Placement of components should be considered to separate
noisy circuits such as crystal clocks, high-speed logic circuitry,
and analog circuitry.
Power planes should encompass a digital power plane (DVDD)
and an analog power plane (AVDD). The analog power plane
should contain the DACs and all associated circuitry, VREF
circuitry. The digital power plane should contain all logic
circuitry. The analog and digital power planes should be individually
connected to the common power plane at one single point through
a suitable filtering device such as a ferrite bead.
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than three inches). The DAC
termination resistors should be placed as close as possible to
the DAC outputs and should overlay the PCB’s ground plane.
As well as minimizing reflections, short analog output traces will
reduce noise pickup due to neighboring digital circuitry.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the group of AVDD or DVDD pins should
be individually decoupled to ground. This should be done by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance.
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the ADV7202
should be avoided to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not the
analog power plane.
Analog Signal Interconnect
The ADV7202 should be located as close as possible to the output
connectors, thus minimizing noise pickup and reflections due to
impedance mismatch.
For optimum performance, the analog outputs should each be
source and load terminated, as shown in Figure TBD. The
termination resistors should be as close as possible to the
ADV7202 to minimize reflections.
Any unused inputs should be tied to the ground.
There should be a separate analog ground plane (AVSS) and a
separate digital ground plane (DVSS).
REV. PrB
–25–
PRELIMINARY TECHNICAL DATA
ADV7202
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
64-Lead Thin Plastic Quad Flatpack (LQFP)
(ST-64B)
0.063 (1.60)
MAX
0.472 (12.00)
BSC SQ
C02602–0–1/02(PrA)
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
33
48
49
32
SEATING
PLANE
0.394
(10.0)
BSC
SQ
TOP VIEW
(PINS DOWN)
VIEW A
PIN 1
64
17
1
16
0.020 (0.50)
BSC
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
0.011 (0.27)
0.009 (0.22)
0.007 (0.17)
0.008 (0.20)
0.004 (0.09)
0.006 (0.15)
0.002 (0.05)
0.003 (0.08)
MAX
7ⴗ
3.5ⴗ
0ⴗ
VIEW A
ROTATED 90ⴗ CCW
PRINTED IN U.S.A.
NOTE: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
–26–
REV. PrB