STMICROELECTRONICS TDA9203A

TDA9203A
I2C BUS CONTROLLED 70MHz RGB PREAMPLIFIER
.
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..
.
..
..
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70MHz TYPICAL BANDWIDTH AT 4VPP OUTPUT WITH 12pF CAPACITIVE LOAD
5.5ns TYPICAL RISE/FALL TIME AT 4VPP
OUTPUT WITH 12pF CAPACITIVE LOAD
POWERFULL OUTPUT DRIVE CAPABILITY
BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH ARE I2C BUS CONTROLLED
INTERNAL
BACK-PORCH
CLAMPING
PULSE GENERATOR
OSD WHITE BALANCE TRACKING
INTERNAL OSD SWITCHES
BLANKING AND FAST-BLANKING INPUTS
VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)
SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE
ABL CONTROL
SHRINK 24
(Plastic Package)
ORDER CODE : TDA9203A
PIN CONNECTIONS
The TDA9203A is a digitaly controlled wideband
video preamplifier intended for use in mid range
color monitor. All controls and adjustments are
digitaly performed thanks to I2C serial bus. Contrast, brightness and DC output level of RGB signals are common to the 3 channels and drive
adjustment is separate for each channel.Three I2C
gain controlled OSD inputs can be switched with
RGB signals using fast blanking command. Clamping of RGB signals is performed thanks to a flexible
integrated system. The white balance adjustment
is effective on brightness, video and OSD signals.
The TDA9203A works for application using AC or
DC coupled CRT driver.
The ABL input provides a 12dB Max. attenuation
on the current contrast value according average
beam limitation voltage.
Because of its features and due to component
saving the TDA9203A leads to a very performant
and cost effective application.
June 1998
IN1
1
24
HSYNC
OSD1
2
23
PVCC1
AVDD
3
22
OUT1
IN2
4
21
PGND1
OSD2
5
20
PVCC2
AGND
6
19
OUT2
IN3
7
18
PGND2
OSD3
8
17
PVCC3
ABL
9
16
OUT3
LGND
10
15
PGND3
SDA
11
14
BLK
SCL
12
13
FBLK
9203A-01.EPS
DESCRIPTION
1/13
TDA9203A
PIN DESCRIPTION
Name
Pin
Type
Function
Name
Pin
Type
IN1
1
I
1st Channel Main Picture Input
FBLK
13
I
Fast Blanking Input
OSD1
2
I
1st Channel OSD Input
Blanking Input
AVDD
3
I
12V Analog VDD
IN2
4
I
2
OSD2
5
I
2nd Channel OSD Input
AGND
6
I/O
IN3
7
Channel Main Picture Input
Analog Ground
rd
3 Channel Main Picture Input
I
rd
OSD3
8
I
3 Channel OSD Input
ABL
9
I
ABL Input
LGND
10
I/O
SDA
11
SCL
12
BLK
14
I
PGND3
15
I/O
3rd Channel Power Ground
OUT3
16
O
3rd Channel Output
PVCC3
17
I
3rd Channel Power VCC
PGND2
18
I/O
2nd Channel Power Ground
OUT2
19
O
2
nd
Channel Output
nd
Channel Power VCC
PVCC2
20
I
PGND1
21
I/O
2
1st Channel Power Ground
Logic Ground
OUT1
22
O
1st Channel Output
I/O
Serial Data Line
PVCC1
23
I
1st Channel Power VCC
I
Serial Clock Line
HSYNC
24
I
Horizontal Synch Input
9203A-01.TBL
nd
Function
BLOCK DIAGRAM
BLK
FBLK
PVCC1
14
13
23
CLAMP
CONTRAST
VREF
AVDD
3
IN1
1
AGND
6
BPCP
BRIGHTNESS
DRIVE
OUTPUT
STAGE
22 OUT1
21 PGND1
20 PVCC2
8 bits
IN2
BLUE CHANNEL
4
19 OUT2
18 PGND2
7
ABL
9
GREEN CHANNEL
16 OUT3
17 PVCC3
15 PGND3
BPCP
LGND 10
LATCHES
I2C
D/A
BUS
DECODER
OSD
2
IC
CONT
VREF
TDA9203A
2/13
24
11
12
2
5
8
HSYNC
SDA
SCL
OSD1
OSD2
OSD3
OUTPUT
DC LEVEL
ADJUST
9203A-02.EPS
IN3
TDA9203A
FUNCTIONAL DESCRIPTION
Input Stage
The R, G and B signals must be fed to the three
inputs through coupling capacitors (100nF).
The maximum input peak-to-peak video amplitude
is 1V.
The input stage includes a clamping function. This
clamp is using the input serial capacitor as ”memory capacitor” and is gated by an internally generated ”Back-Porch-Clamping-Pulse (BPCP)”.
The synchronization edge of the BPCP is selected
according bit 0 of register R8.
When B0R8 is set to 1, the BPCP is synchronized
on the leadingedgeof the blankingpulse BLKinputs
on Pin14 (seeFigure1). B7R8 allowsto usepositive
or negative blanking signal on Pin 14. At power on
reset TDA9203Ause only positive blanking.
R,G,B video signals according to beam intensity.
The operating range is 2.5V typicaly, from 5.3V to
2.8V. A typical 12dB Max. attenuationis applied to
the signal whatever the current gain is. Refer to
Figure 3 for ABL input attenuation range.
In case of software control, the ABL input must be
pulled to AVDD through a resistor to limit power
consumption (see Figure 11).
ABL input voltage must not exceeed AVDD. Input
resistor is 10kΩ and equivalent schematic given in
Figure 11.
Figure 3
2
Attenuation (dB)
0
-2
Figure 1
-4
BLK
-6
HSYNC
Figure 2
In both case BPCP width is adjustable by I2C, B1
and B2 of register R8 (see R8 Table P8).
Contrast Adjustment (8 bits)
The contrast adjustment is made by controlling
simultaneously the gain of three internal variable
gain amplifiers through the I2C bus interface.
The contrast adjustment allows to cover a typical
range of 48dB.
ABL Control
The TDA9203A I2C preamplifier provides an ABL
input (automatic beam limitation) to attenuate
9203A-04.EPS
HSYNC
Internal pulse width is controlled by I2C
-12
-14
When B0R8 is clear to 0, the BPCP is synchronized
on the second edge of the horizontal pulse HSYNC
inputs on Pin 24. An automatic function allows to
use positive or negative horizontal pulse on Pin 24
(see Figure 2).
BPCP
-10
VIN (V)
1
2
3
4
5
6
7
8
9
Brightness Adjustment (8 bits)
As for the contrast adjustment, the brightness is
controlled by I2C.
The brightness function consists to add the same
DC offset to the three R, G, B signals after contrast
amplification. This DC-Offset is present only outside the blanking pulse (see Figure 4).
The DC output level during the blanking pulse, is
forced to ”INFRA-BLACK” level (VDC).
Drive Adjustment (3 x 8 bits)
In order to adjust the white balance, the TDA9203A
offers the possibility to adjust separatelythe overall
gain of each complete video channel. The gain of
each channel is controlled by I2C (8bits each).
The very large drive adjustment range(48dB) allows
different standard or custom color temperature.
It can also be used to adjust the output voltages at
the optimum amplitude to drive the C.R.T drivers,
keepingthe whole contrast control for end-useronly.
The drive adjustment is located after the CONTRAST, BRIGHTNESS and OSD switch blocks, so
that the white balance will remains correct when
BRT is adjusted, and will also be correct on OSD
portion of the signal.
3/13
9203A-0X.EPS
Internal pulse width is controlled by I2C
9203A-03.EPS
-8
BPCP
TDA9203A
FUNCTIONAL DESCRIPTION (continued)
OSD Inputs
The TDA9203A includes all the circuitry necessary
to mix OSDsignals intothe RGB main-picture. Four
pins are dedicated to this function as follow.
Three TTL RGB On Screen Display inputs (Pin 2,
5 and 8). These three inputs are connected to the
three outputs of the corresponding ON-SCREENDISPLAY processor (ex : STV942x).
One Fast Blanking Input (FBLK, Pin 13) which is
also connected to the FBLK output of the same
ON-SCREEN-DISPLAY processor.
When a high level is present on FBLK, the IC will
acts as follow :
- The three main picture RGB input signals are
internally switched to the internal input clamp
reference voltage.
- The three output signals are set to voltages correspondingto the state (0 or 1) on the three OSD
inputs (see Figure 4).
Example :
If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1
respectively.
Then OUT1, OUT2, OUT3 will be equal to VOSD,
VBRT, VOSD,
where : VBRT = VBLACK + BRT, VOSD = VBRT + OSD
BRT is the brightness DC level I2C adjustable.
OSD is the On-Screen Display signal value I2C
adjustable from 0V to 5.5VPP by step of 0.36V.
Semi-transparent function is controlled thanks to
Bit 6 of R8 register (see Table 1).
When semi-transparent mode is activated, video
signal is divided by 2 (CONT).
Table 1
FBLK OSD1 OSD2 OSD3 B6R8
0
1
0
1
1
1
1
x
x
x
0
x
x
1
x
x
x
x
1
x
0
x
x
x
x
x
0
1
0
0
1
1
1
1
1
Output
Signal (OUTn)
Video
OSD (1)
Video
OSD
OSD
OSD
Semi-transparent (2)
Notes : 1. All OSD colors are displayed.
2. One OSD color is displayed as semi-transparent video
without effect on brightness and DC level adjustment.
4/13
Output Stage
The three output stagesincorporate threefunctions
which are :
- The blanking stage : When high level is applied
to the BLK input (Pin 14), the three outputs are
switched to a voltage which is 400mV lower than
the BLACK level. The black level is the output
voltage with minimum brightness when input signal video amplitude is equal to ”0”.
- The output stage itself : It is a large bandwidth
output amplifier which allow to deliver up to 5VPP
on the three outputs (for 0.7V video signal on the
inputs).
- The output CLAMP : The IC also incorporates
three internal output clamp (sample and hold
system) which allow to DC shift the three output
signals. The DC output voltage is adjustable
through I2C with 4 bits. Practicaly, the DC output
level allow to adjust the BLK level (VDC = 400mV
under VBLACK) from 0.9V to 2.9V with 12 x 165mV.
The overall waveforms of the output signal according to the different adjustment are shown in Figures 4 and 5.
Serial Interface
The 2-wires serial interface is an I2C interface.
The slave address of the TDA9203A is DC (in
hexadecimal).
A6
A5
A4
A3
A2
A1
A0
W
1
1
0
1
1
1
0
0
Data Transfer
The host MCU can write data into the TDA9203A
registers. Read mode is not available.
To write data into the TDA9203A, after a start, the
MCU must send (see Figure 6) :
- The I2C addressslave byte with a low level for the
R/W bit.
- The byte of the internal register address where
the MCU wants to write data(s).
- The data.
All bytes are sent MSB bit first and the write data
transter is closed by a stop.
TDA9203A
FUNCTIONAL DESCRIPTION (continued)
Figure 4 : Waveforms VOUT, BRT, CONT, OSD
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
VOUT1, VOUT2, VOUT3
VCONT (4)
VOSD (5)
VBRT (3)
OSD
VBLACK (2)
VDC (1)
CONT
BRT
0.4V fixed
VDC = 0.5 to 2.5V
VBLACK = VDC + 0.4V
VBRT = VBLACK + BRT (with BRT = 0 to 2.5V)
VCONT = VBRT + CONT with CONT = k x Video IN (CONT = 5VP P max. for VIN = 0.7VPP)
VOSD = VBRT + OSD with OSD = k1 x OSDIN (OSD max. = 5.5VPP, OSD min. = 360mVPP)
9203A-06.EPS
Notes : 1.
2.
3.
4.
5.
Figure 5 : Waveforms (DRIVE adjustment)
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
VOUT1, VOUT2, VOUT3
VCONT
VOSD
VBRT
V BLACK
V DC
9203A-07.EPS
Two exemples
of drive adjustment (1)
Note : 1. Drive adjustment modifies the following voltages : VCONT, VBRT and VOSD.
Drive adjustment do not modify the following voltages : V DC and VBLACK.
Figure 6 : I2C Write Operation
W
Start
I C Slave Address
2
A7
ACK
A6
A5
A4
A3
A2
Register Address
A1
A0
D7
ACK
D6
D5
D4
D3
Data Byte
D2
D1
D0
ACK
Stop
5/13
9203A-08.EPS
SCL
SDA
TDA9203A
QUICK REFERENCE DATA
Parameter
Min.
Typ.
Max.
Unit
Signal Bandwidth (4V PP/12pF load)
70
MHz
Rise and Fall Time (4VPP/12pF load)
5.5
ns
Drive Adjustment Range on the 3 Channels separately
48
dB
Maximum Output Voltage (VIN = 0.7 VPP)
5
VPP
Output Voltage Range (AC + DC)
8
V
9203A-02.TBL
Symbol
Parameter
Value
Unit
14
V
Voltage at any Input Pins (except SDA & SCL & Logical Inputs)
GND < VIN1 < VS
V
Voltage at Input Pins SDA & SCL
GND < VIN2 < 5.5
V
VIN3
Voltage at Logical Inputs (OSD, FBLK, BLK, HSYNC)
GND < VIN3 < 5.5
V
VESD
ESD Susceptability (Human body model ; 100pF Discharge through 1.5kΩ)
2
kV
- 40, + 150
°C
150
°C
0, + 70
°C
VS
Supply Voltage (Pins 3-9-17-20-23)
VIN1
VIN2
Tstg
Storage Temperature
Tj
Junction Temperature
Top er
Operating Temperature
THERMAL DATA
Symbol
Rth (j-a)
Parameter
Value
Junction-ambient Thermal Resistance
Unit
o
69
C/W
9203A-04.TBL
Symbol
9203A-03.TBL
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Parameter
Test Conditions
Min.
10.8
Typ.
Max.
12
13.2
VS
Supply Voltage
Pins 3-9-17-20-23
IS
Supply Current (All VS Pin current)
RL = 1kΩ
60
VI
Video Input Voltage Amplitude
Pins 1-4-7
0.7
VO
Typical Output Voltage Range
Pins 16-19-22
VIL
Low Level Input (OSD, FBLK, BLK, HSYNC)
Pins 2-5-8-13-14-24
VIH
High Level Input (OSD, FBLK, BLK, HSYNC)
Pins 2-5-8-13-14-24
2.4
IIN
Input Current (OSD, FBLK, BLK, HSYNC)
0.4V < VIN < 4.5V
-10
6/13
0.5
-
Unit
V
mA
1
VPP
8
V
0.8
V
V
+10
µA
9203A-05.TBL
Symbol
TDA9203A
AC ELECTRICAL CHARACTERISTICS
(Tamb = 25oC, VCC = 12V, CL = 12pF, RL = 1kΩ , unless otherwise specified)
Symbol
Parameter
AV
Maximum Gain (20 log x VOUT AC/VIN AC)
Contrast & Drive at maximum
18
dB
Contrast Attenuation Range
VIN = 0.7VPP, Contrast & Drive at POR
48
dB
DAR
Drive Attenuation Range
GM
Gain Match
VOUT = 2.5VPP, VIN = 0.7VPP
Contrast = Drive = Maxi x 0.7
(power-on reset value)
BW
Bandwidth Large Signal
DIS
Min.
Typ.
Max. Unit
48
dB
± 0.1
dB
At -3dB, VIN = 0.7VPP, VOUT = 4VPP
Contrast = Drive = Maxi x 0.87
70
MHz
Video Output Distorsion (see Note)
f = 1MHz, VOUT = 1VPP, VIN = 1VPP
0.3
%
tR , tF
Video Output Rise and Fall Time
(see Note)
VIN = 0.7VPP, VOUT = 4VPP
Contrast = Drive = Maxi x 0.87
5.5
ns
BRT
Brightness Maximum DC Level
Brightness Minimum DC Level
2.5
0
V
V
±20
mV
OSD
CAR
Contrast Attenuation Range
for OSD Input
24
dB
DC
Output Maximum DC Level
Output Minimum DC Level
2.5
0.5
V
V
RL
Equivalent Load on Video Output
with Tj ≤ Tj Max.
1
kΩ
CT
Croostalk between Video Channels
(see Note)
VOUT = 2.5VPP, VIN = 0.7VPP
Contrast = Drive = Maxi x 0.7
(power-on reset value)
fIN = 1MHz
GABL
ABL Min. Attenuation
ABL Max. Attenuation
VABL = 5.3V Typical
VABL = 2.8V Typical
0
12
IABL
ABL Input Current
VABL = 5.3V
20
µA
R ABL
ABL Input Resistor
See Figure 11
10
kΩ
BRTM
Brightness Matching
BRT = 50%, Drive at POR
44
dB
dB
dB
9203A-06.TBL
CAR
Test Conditions
Note : These parameters are not tested on each unit. They are measured during an internal qualification procedure which includes
characterization on batches coming from corners of our processes and also from temperature characterization.
I2C ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Parameter
VIL
Low Level Input Voltage
V IH
High Level Input Voltage
IIN
Input Current (Pins SDA, SCL)
fSCL(Max.)
VOL
Test Conditions
Typ.
Max.
Unit
1.5
V
+10
µA
3
0.4V < VIN < 4.5V
SCL Maximum Clock Frequency
Low Level Output Voltage
Min.
On Pins SDA, SCL
-10
V
200
SDA Pin when ACK
Sink Current = 6mA
kHz
0.6
V
7/13
9203A-08.TBL
Symbol
TDA9203A
I2C INTERFACE TIMINGS REQUIREMENTS (see Figure 7)
Parameter
Min.
Typ.
Max.
Unit
tBUF
Time the bus must be free between 2 access
1300
ns
tHDS
Hold Time for Start Condition
600
ns
tSUP
Set-up Time for Stop Condition
600
ns
tLOW
The Low Period of Clock
1300
ns
tHIGH
The High Period of Clock
600
ns
tHDAT
Hold Time Data
300
ns
tSUDAT
Set-up Time Data
250
Rise and Fall Time of both SDA and SCL
20
tR, tF
ns
300
ns
9203A-09.TBL
Symbol
Figure 7
tBUF
tHDAT
SDA
tSUDAT
tSUP
SCL
tHIGH
8/13
tLOW
9203A-09.EPS
tHDS
TDA9203A
REGISTER DESCRIPTION
Registers Sub-address
Address (Hex)
Register Names
Function
POR Value
01
Contrast
DAC 8-bit
B4
02
Brightness
DAC 8-bit
B4
03
Drive 1
DAC 8-bit
B4
04
Drive 2
DAC 8-bit
B4
05
Drive 3
DAC 8-bit
B4
06
Output DC Level
DAC 4-bit
08
07
OSD Contrast
DAC 4-bit
08
08
BP and Miscellaneous
See R8 Table
04
Contrast Register (R1) (Video IN = 0.5VPP, Brightness at minimum,Drive at maximum)
Hex
b7
b6
b5
b4
b3
b2
b1
b0
CONT (VPP)
G (dB)
00
0
0
0
0
0
0
0
0
0
-
01
0
0
0
0
0
0
0
1
0.015
-30
02
0
0
0
0
0
0
1
0
0.031
-24
04
0
0
0
0
0
1
0
0
0.062
-18
08
0
0
0
0
1
0
0
0
0.125
-12
10
0
0
0
1
0
0
0
0
0.25
-6
20
0
0
1
0
0
0
0
0
0.5
0
40
0
1
0
0
0
0
0
0
1
6
80
1
0
0
0
0
0
0
0
2
12
B4
1
0
1
1
0
1
0
0
2.812
15
FF
1
1
1
1
1
1
1
1
4
18
POR Value
X
Brightness Register (R2) (Drive at maximum)
Hex
b7
b6
b5
b4
b3
b2
b1
b0
BRT (V)
00
0
0
0
0
0
0
0
0
0
01
0
0
0
0
0
0
0
1
0.010
02
0
0
0
0
0
0
1
0
0.020
04
0
0
0
0
0
1
0
0
0.040
08
0
0
0
0
1
0
0
0
0.080
10
0
0
0
1
0
0
0
0
0.160
20
0
0
1
0
0
0
0
0
0.320
40
0
1
0
0
0
0
0
0
0.640
80
1
0
0
0
0
0
0
0
1.28
B4
1
0
1
1
0
1
0
0
1.8
FF
1
1
1
1
1
1
1
1
2.56
POR Value
X
9/13
TDA9203A
REGISTER DESCRIPTION (continued)
Drive Registers (R3, R4, R5) (Video IN = 0.5VPP, Brightness at minimum, Contrast at maximum)
Hex
b7
b6
b5
b4
b3
b2
b1
b0
CONT (VPP)
G (dB)
00
0
0
0
0
0
0
0
0
0
-
01
0
0
0
0
0
0
0
1
0.015
-30
02
0
0
0
0
0
0
1
0
0.031
-24
04
0
0
0
0
0
1
0
0
0.062
-18
08
0
0
0
0
1
0
0
0
0.125
-12
10
0
0
0
1
0
0
0
0
0.25
-6
20
0
0
1
0
0
0
0
0
0.5
0
40
0
1
0
0
0
0
0
0
1
6
80
1
0
0
0
0
0
0
0
2
12
B4
1
0
1
1
0
1
0
0
2.812
15
FF
1
1
1
1
1
1
1
1
4
18
POR Value
X
Output DC Level Register (R6)
Hex
b7
b6
b5
b4
b3
b2
b1
b0
DC (V)
03
0
0
0
0
0
0
1
1
0.52
04
0
0
0
0
0
1
0
0
0.69
08
0
0
0
0
1
0
0
0
1.35
0F
0
0
0
0
1
1
1
1
2.5
POR Value
X
Code 00Hex, 01Hex and 02Hex : not to be used
OSD Contrast Register (R7) (VOSD IN = 2.4VMin.., Drive at maximum)
Hex
b7
b6
b5
b4
b3
b2
b1
b0
OSD (V)
G (dB)
00
0
0
0
0
0
0
0
0
0
-
01
0
0
0
0
0
0
0
1
0.36
-24
02
0
0
0
0
0
0
1
0
0.73
-18
04
0
0
0
0
0
1
0
0
1.46
-12
08
0
0
0
0
1
0
0
0
2.93
-6
0F
0
0
0
0
1
1
1
1
5.5
0
POR Value
X
BP and Miscellaneous Register (R8)
b7
b6
b5
b4
b3
b2
b1
b0
Function
0
BP Source = HSYNC
1
BP Source = BLK
0
0
BP Pulse Width = 0.33µs
0
1
BP Pulse Width = 0.66µs
1
0
BP Pulse Width = 1µs
1
1
BP Pulse Width = 1.3µs
X
X
0
0
Test Purposes
X
0
0
0
Soft Blanking OFF
X
1
1
1
Soft Blanking ON
0
Semi Transparent OFF
1
Semi Transparent ON
0
Positive Blanking Polarity Selection
1
Negative Blanking Polarity Selection
10/13
POR Value
X
X
TDA9203A
INTERNAL SCHEMATICS
Figure 8
Figure 9
AVDD
P ins
1-4-7
AVDD
IN
OS D - BLK - FBLK
P ins 2-5-8-13-14
Figure 10
AGND
9203A-11.EPS
AGND
9203A-10.EPS
AGND
AGND
Figure 11
AVDD
3
AVDD
(20V)
Internal
5V
10kΩ
6
Figure 12
9
9203A-13.EPS
AGND
9203A-12.EPS
ABL
AGND
Figure 13
AVDD
S DA
S CL
P ins
11-12
LGND 10
(10V)
LGND
Figure 14
9203A-15.EPS
AGND
9203A-14.EPS
AGND
LGND
Figure 15
PVCC
AVDD
P ins 17-20-23
AVDD
HSYNC 24
OUT
Pins 16-19-22
9203A-17.EPS
LGND
9203A-16.EPS
AGND
AGND
P GND
P ins 15-18-21
11/13
TDA9203A
APPLICATION DIAGRAM
BLK
HSYNC
VSYNC
SYNCHRO
EXTRACTOR
+12V
47Ω
100nF
B
GND B
1kΩ
75Ω
47Ω
100nF
R
GND R
1kΩ
75Ω
47Ω
100nF
100nF
1kΩ
G
GND G
75Ω
1kΩ
ABL
GND
100nF
1
IN1
2
OSD1
3
AVDD
4
IN2
5
OSD2
6
AGND
7
IN3
8
OSD3
9
ABL
HSYNC 24
PVCC1 23
OUT1 22
T
D
A
9
2
0
3
A
BLUE OUT
PVCC2 20
OUT2 19
100nF
RED OUT
PGND2 18
PVCC3 17
OUT3 16
100nF
GREEN OUT
PGND3 15
10 LGND
11 SDA
BLK 14
12 SCL
FBLK 13
GND
100nF
PGND1 21
1kΩ
GND
+5V
100nF
12/13
VSYNC
3
HSYNC
4
VDD
5
PXCK
6
CKOUT
7
XTAL OUT
8
XTAL IN
S
T
V
9
4
2
6
B 15
G 14
2.7kΩ
2
TEST 16
R 13
GND 12
RESET 11
100Ω
SDA 10
SDA
SCL
SCL
I2C BUS
33pF
33pF
8MHz
FBLK
9
10µF
16V
22pF
9203A-18.EPS
+5V
1
TDA9203A
PACKAGE MECHANICAL DATA
24 PINS - PLASTIC DIP (SHRINK)
E
A2
A
L
A1
E1
Stand-o ff
B
B1
e
e1
e2
c
D
E
13
.015
F
24
0,38
1
PMSDIP24.EPS
Gage Plane
12
e3
Dimensions
A
A1
B
B1
C
D
E
E1
e
e1
e2
e3
L
Min.
0.51
3.05
0.36
0.76
0.23
22.61
7.62
6.10
2.54
Millimeters
Typ.
3.30
0.46
1.02
0.25
22.86
6.40
1.778
7.62
3.30
Max.
5.08
4.57
0.56
1.14
0.38
23.11
8.64
6.86
10.92
1.52
3.81
Min.
0.020
0.120
0.0142
0.030
0.0090
0.890
0.30
0.240
0.10
e2
Inches
Typ.
0.130
0.0181
0.040
0.0098
0.90
0.252
0.070
0.30
0.130
Max.
0.20
0.180
0.0220
0.045
0.0150
0.910
0.340
0270
0.430
0.060
0.150
SDIP24.TBL
SDIP24
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Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I 2C Patent.
2
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13/13