a FEATURES INPUT FORMATS YCrCb in 2 10-Bit (4:2:2) or 3 10-Bit (4:4:4) Format Compliant to SMPTE274M (1080i), SMPTE296M (720p) and Any Other High-Definition Standard Using Async Timing Mode RGB in 3 10-Bit 4:4:4 Format OUTPUT FORMATS YPrPb HDTV (EIA-770.3) RGB Levels Compliant to RS-170 and RS-343A 11-Bit + Sync (DAC A) 11-Bit DACs (DAC B, C) PROGRAMMABLE FEATURES Internal Test Pattern Generator with Color Control Y/C Delay () Individual DAC On/Off Control VBI Open Control I2C Filter 2-Wire Serial MPU Interface Single Supply 5 V/3.3 V Operation 52-Lead MQFP Package Multiformat HDTV Encoder with Three 11-Bit DACs ADV7197 FUNCTIONAL BLOCK DIAGRAM 11-BIT + SYNC DAC DAC A (Y) Y0–Y9 Cr0–Cr9 Cb0–Cb9 CLKIN HORIZONTAL SYNC VERTICAL SYNC TEST PATTERN GENERATOR AND DELAY CHROMA 4:2:2 TO 4:4:4 (SSAF) 11-BIT DAC DAC B CHROMA 4:2:2 TO 4:4:4 (SSAF) 11-BIT DAC DAC C SYNC GENERATOR TIMING GENERATOR DAC CONTROL BLOCK VREF RSET COMP BLANKING 2 RESET I C MPU PORT ADV7197 APPLICATIONS HDTV Display Devices HDTV Projection Systems Digital Video Systems High Resolution Color Graphics Image Processing/Instrumentation Digital Radio Modulation/Video Signal Reconstruction GENERAL DESCRIPTION The ADV7197 is a triple, high-speed, digital-to-analog encoder on a single monolithic chip. It consists of three high-speed video D/A converters with TTL-compatible inputs. The ADV7197 has three separate 10-bit-wide input ports that accept data in 4:4:4 10-bit YCrCb or RGB, or 4:2:2 10-bit YCrCb. This data is accepted in HDTV format at 74.25 MHz or 74.1758 MHz. For any other high definition standard but SMPTE274M or SMPTE296M, the Async Timing Mode can be used to input data to the ADV7197. For all standards, external horizontal, vertical, and blanking signals or EAV/SAV codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals. The ADV7197 outputs analog YPrPb HDTV complying to EIA-770.3, or RGB complying to RS-170/RS-343A. The ADV7197 requires a single 5 V/3.3 V power supply, an optional external 1.235 V reference, and a 74.25 MHz (or 74.1758 MHz) clock. The ADV7197 is packaged in a 52-lead MQFP package. *ADV is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 ADV7197–SPECIFICATIONS (VAA = 4.75 V to 5.25 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications TMIN to TMAX [0C to 5 V SPECIFICATIONS1 70C] unless otherwise noted.) Parameter Min STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current Input Capacitance, CIN ANALOG OUTPUTS Full-Scale Output Current Output Current Range 11 1.5 0.9 POWER REQUIREMENTS IDD2 IAA3, 4 Power Supply Rejection Ratio Max Unit Test Conditions 2.0 Bits LSB LSB Guaranteed Monotonic 2.4 0.4 10 V V µA pF 0.8 1 V V µA pF 4 2.0 0 4 3.92 2.54 3.92 2.39 4.25 2.83 4.25 2.66 1.4 1.4 100 7 4.56 3.11 4.56 2.93 mA mA mA mA % V kΩ pF 1.112 1.235 1.359 V 96 11 0.01 102 15 mA mA %/% DAC-to-DAC Matching Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE (External and Internal) Reference Range, VREF Typ ISOURCE = 400 µA ISINK = 3.2 mA VIN = 0.4 V VIN = 0.4 V or 2.4 V DAC A DAC B, C DAC A DAC B, C DAC A, B, C With fCLK = 74.25 MHz NOTES 1 Guaranteed by characterization. 2 IDD or the circuit current is the continuous current required to drive the digital core. 3 IAA is the total current required to supply all DACs including V REF circuitry. 4 All DACs on. Specifications subject to change without notice. –2– REV. 0 ADV7197 3.3 V SPECIFICATIONS1 (VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications TMIN to TMAX [0C to 70C] unless otherwise noted.) Parameter Min STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current Input Capacitance, CIN ANALOG OUTPUTS Full-Scale Output Current Output Current Range DAC-to-DAC Matching Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE (External) Reference Range, VREF POWER REQUIREMENTS IDD2 IAA3, 4 Power Supply Rejection Ratio Typ 11 1.5 0.9 Unit 2.0 Bits LSB LSB 2.4 0.4 10 V V µA pF 0.8 0 4 0.65 1 V V µA pF 4.25 2.83 4.25 2.66 1.4 1.4 100 7 4.56 3.11 4.56 2.93 mA mA mA mA % V kΩ pF 1.235 1.359 V 46 11 0.01 15 mA mA %/% 4 2 3.92 2.54 3.92 2.39 0 1.112 NOTES 1 Guaranteed by characterization. 2 IDD or the circuit current is the continuous current required to drive the digital core. 3 IAA is the total current required to supply all DACs including V REF circuitry. 4 All DACs on. Specifications subject to change without notice. REV. 0 Max –3– Test Conditions ISOURCE = 400 µA ISINK = 3.2 mA VIN = 0.4 V VIN = 0.4 V or = 2.4 V DAC A DAC B, C DAC A DAC B, C DAC A, B, C With fCLK = 74.25 MHz ADV7197–SPECIFICATIONS (VAA = 4.75 V to 5.25 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications TMIN MAX [0C to 70C] unless otherwise noted.) 5 V DYNAMIC–SPECIFICATIONS to T Parameter Min Typ Luma Bandwidth Chroma Bandwidth Signal-to-Noise Ratio Chroma/Luma Delay Inequality Max 13.5 6.75 64 0 Unit MHz MHz dB Luma Ramp Unweighted ns Specifications subject to change without notice. (VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications MIN to TMAX [0C to 70C] unless otherwise noted.) 3.3 V DYNAMIC–SPECIFICATIONS T Parameter Min Typ Luma Bandwidth Chroma Bandwidth Signal-to-Noise Ratio Chroma/Luma Delay Inequality Max 13.5 6.75 64 0 Unit MHz MHz dB Luma Ramp Unweighted ns Specifications subject to change without notice. 5 V TIMING–SPECIFICATIONS Parameter (VAA = 4.75 V to 5.25 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications TMIN to TMAX [0C to 70C] unless otherwise noted.) Min Typ Max Unit 400 kHz µs µs µs µs ns ns ns µs ns Conditions 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t 2 Hold Time (Start Condition), t 3 Setup Time (Start Condition), t 4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t 6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t 8 RESET Low Time 10 0.6 1.3 0.6 0.6 100 300 300 0.6 100 ANALOG OUTPUTS Analog Output Delay2 Analog Output Skew CLOCK CONTROL AND PIXEL PORT 3 fCLK tCLK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t 12 Control Setup Time, t 11 Control Hold Time, t 12 Pipeline Delay 10 0.5 ns ns 74.25 81 5 5 2.0 4.5 7 4.0 After This Period the 1st Clock Is Generated Relevant for Repeated Start Condition 1.5 2.0 16 MHz MHz ns ns ns ns ns ns Clock Cycles HDTV Mode Async Timing Mode For 4:4:4 Pixel Input Format NOTES 1 Guaranteed by characterization. 2 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3 Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV Specifications subject to change without notice. –4– REV. 0 ADV7197 3.3 V TIMING–SPECIFICATIONS Parameter (VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications TMIN to TMAX [0C to 70C] unless otherwise noted.) Min Typ Max Unit 400 kHz µs µs µs µs ns ns ns µs ns Conditions 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t 2 Hold Time (Start Condition), t 3 Setup Time (Start Condition), t 4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t 6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t 8 RESET Low Time 10 0.6 1.3 0.6 0.6 100 300 300 0.6 100 ANALOG OUTPUTS2 Analog Output Delay Analog Output Skew 10 0.5 CLOCK CONTROL AND PIXEL PORT 3 fCLK tCLK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t 12 Control Setup Time, t 11 Control Hold Time, t 12 Pipeline Delay ns ns 74.25 81 5 5 2.0 4.5 7 4.0 After This Period the 1st Clock Is Generated Relevant for Repeated Start Condition 1.5 2.0 16 MHz MHz ns ns ns ns ns ns Clock Cycles HDTV Mode Async Timing Mode For 4:4:4 Pixel Input Format NOTES 1 Guaranteed by characterization. 2 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3 Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV Specifications subject to change without notice. CLOCK t9 PIXEL INPUT DATA t10 Y0 Y1 Y2 ... ... Yxxx Yxxx Cb0 Cr0 Cb1 Cr1 ... Cbxxx Crxxx t12 t 9 – CLOCK HIGH TIME t10 – CLOCK LOW TIME t11 – DATA SETUP TIME t12 – DATA HOLD TIME t11 Figure 1. 4:2:2 Input Data Format Timing Diagram REV. 0 –5– ADV7197 CLOCK t9 PIXEL INPUT DATA t10 Y0 Y1 Y2 ... ... Yxxx Yxxx Cb0 Cb1 Cb2 Cb3 ... Cbxxx Cbxxx Cr0 Cr1 Cr2 Cr3 ... Crxxx Crxxx t12 t 9 – CLOCK HIGH TIME t10 – CLOCK LOW TIME t11 – DATA SETUP TIME t12 – DATA HOLD TIME t11 Figure 2. 4:4:4 YCrCb Input Data Format Timing Diagram CLOCK t9 PIXEL INPUT DATA t10 R0 R1 R2 ... ... Rxxx Rxxx G0 G1 G2 G3 ... Gxxx Gxxx B0 B1 B2 B3 ... Bxxx Bxxx t12 t 9 – CLOCK HIGH TIME t10 – CLOCK LOW TIME t11 – DATA SETUP TIME t12 – DATA HOLD TIME t11 Figure 3. 4:4:4 RGB Input Data Format Timing Diagram –6– REV. 0 ADV7197 HSYNC VSYNC A DV PIXEL DATA Y Y Y Y Cr Cr Cr Cr Cb Cb Cb Cb B AMIN = 44 CLK CYCLES FOR 1080i AMIN = 70 CLK CYCLES FOR 720P BMIN = 236 CLK CYCLES FOR 1080i BMIN = 300 CLK CYCLES FOR 720P Figure 4. Input Timing Diagram t5 t3 t3 SDA t6 t1 SCL t2 t7 t4 Figure 5. MPU Port Timing Diagram REV. 0 –7– t8 ADV7197 ABSOLUTE MAXIMUM RATINGS 1 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . –40°C to +85°C Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . 150°C Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . 225°C Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . 220°C IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7197KST 0°C to 70°C Plastic Quad Flatpack (MQFP) S-52 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7197 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE RESET ALSB Cb/Cr[9] Cb/Cr[8] Cb/Cr[7] Cb/Cr[6] Cb/Cr[5] Cb/Cr[4] Cb/Cr[3] Cb/Cr[2] Cb/Cr[1] Cb/Cr[0] GND PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 VDD 1 39 VREF 38 RSET PIN 1 IDENTIFIER Y[0] 2 Y[1] 3 37 COMP Y[2] 4 36 DAC B Y[3] 5 35 V AA 34 DAC A Y[4] 6 ADV7197 Y[5] 7 TOP VIEW (Not to Scale) Y[6] 8 33 AGND 32 DAC C Y[7] 9 31 SDA Y[8] 10 30 SCL Y[9] 11 29 HSYNC/SYNC VDD 12 28 VSYNC/TSYNC 27 DV GND 13 –8– AGND CLKIN VAA Cr[9] Cr[8] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] 14 15 16 17 18 19 20 21 22 23 24 25 26 REV. 0 ADV7197 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Input/Output Function 1, 12 2–11 13, 52 14–23 VDD Y0–Y9 GND Cr0–Cr9 P I G I 24, 35 25 26, 33 27 28 VAA CLKIN AGND DV VSYNC/ TSYNC HSYNC/ SYNC P I G I I Digital Power Supply. 10-Bit HDTV Input Port for Y Data. G data input in RGB mode. Digital Ground 10-Bit HDTV Input Port for Color Data in 4:4:4 Input Mode. In 4:2:2 mode this input port is not used. R data input in RGB mode. Analog Power Supply. Pixel Clock Input. Requires a 74.25 MHz (74.1758 MHz) reference clock. Analog Ground Video Blanking Control Signal Input. VSYNC, vertical sync control signal input or TSYNC input control signal in Async Timing Mode. 29 I HSYNC, horizontal sync control signal input or SYNC input control signal in Async Timing Mode. 30 31 32 34 36 37 38 SCL SDA DAC C DAC A DAC B COMP RSET I I/O O O O O I 39 VREF I/O 40 RESET I 41 ALSB I 42–51 Cb/Cr9–0 I REV. 0 MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. Color component analog output of input data on Cb/Cr9–0 input pins. Y Analog Output. Color component analog output of input data on Cr9–Cr0 input pins. Compensation Pin for DACs. Connect 0.1 µF Capacitor from COMP pin to VAA. A 2470 Ω resistor (for input ranges 64–940 and 64–960, output standards EIA-770.3) must be connected from this pin to ground and is used to control the amplitudes of the DAC outputs. For input ranges 0–1023 (output standards RS-170, RS-343A) the RSET value must be 2820 Ω. Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). This input resets the on-chip timing generator and sets the ADV7197 into Default Register setting. Reset is an active low signal. TTL Address Input. This signal sets up the LSB of the MPU address. When this pin is tied high, the I2C filter is activated which reduces noise on the I2C interface. When this pin is tied low, the input bandwidth on the I2C interface is increased. 10-Bit HDTV Input Port for Color Data. In 4:2:2 mode the multiplexed CrCb data must be input on these pins. B data input in RGB mode. –9– ADV7197 FUNCTIONAL DESCRIPTION Digital Inputs The digital inputs of the ADV7197 are TTL-compatible. 30-bit YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel data in 4:2:2 format is latched into the device on the rising edge of each clock cycle at 74.25 MHz or 74.1758 in HDTV mode. It is recommended to input data in 4:2:2 mode to make use of the Chroma SSAFs on the ADV7197. As can be seen in the figures below, these filters have 0 dB passband response and prevent signal components being folded back into the frequency band. In 4:4:4 input mode, the video data is already interpolated by an external input device and the chroma SSAFs of the ADV7197 are bypassed. ATTEN 10dB RL –10.0dBm VAVG 1 10dB/ (EIA-770.3), RLOAD has a value of 300 Ω. For the outputs to conform to RS-170/RS-343A standards RSET must have a value of 2820 Ω. Internal Test Pattern Generator The ADV7197 can generate a Cross-Hatch pattern (white lines against a black background). Additionally, the ADV7197 can output a uniform color pattern. The color of the lines or uniform field/frame can be programmed by the user. Y/CrCb Delay The Y output and the color component outputs can be delayed wrt the falling edge of the horizontal sync signal by up to four clock cycles. I2C Filter MKR 0dB 3.18MHz A selectable internal I2C filter allows significant noise reduction on the I2C interface. For setting ALSB high, the input bandwidth on the I2C lines is reduced and pulses of less than 50 ns are not passed to the I2C controller. Setting ALSB low allows greater input bandwidth on the I2C lines. MPU PORT DESCRIPTION START 100kHz RBW 10kHz STOP VBW 300Hz The ADV7197 support a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two inputs Serial Data (SDA) and Serial Clock (SCL) carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7197 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 8. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation while Logic Level “0” corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7197 to Logic Level “0” or Logic Level “1.” When ALSB is set to “0,” there is greater input bandwidth on the I2C lines, which allows high-speed data transfers on this bus. When ALSB is set to “1,” there is reduced input bandwidth on the I2C lines, which means that pulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems. 20.00MHz SWP 17.0SEC Figure 6. SSAF Response to a 2.5 MHz Chroma Sweep Using 4:2:2 Input Mode ATTEN 10dB RL –10.0dBm VAVG 4 10dB/ MKR –3.00dB 3.12MHz 0 1 0 1 0 1 A1 X ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ Figure 8. Slave Address START 100kHz RBW 10kHz STOP VBW 300Hz 20.00MHz SWP 17.0SEC Figure 7. Conventional Filter Response to a 2.5 MHz Chroma Sweep Using 4:4:4 Input Mode Control Signals The ADV7197 accepts sync control signals accompanied by valid 4:2:2 or 4:4:4 data. These external horizontal, vertical and blanking pulses (or EAV/SAV codes) control the insertion of appropriate sync information into the output signals. Analog Outputs The analog Y signal is output on the 11-bit + Sync DAC A, the color component analog signals on the 11-bit DACs B, C conforming to EIA-770.3 standards RSET has a value of 2470 Ω To control the various devices on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a Start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the Start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an Acknowledge Bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the Start condition and the correct transmitted address. The R/W bit determines the direction of the data. –10– REV. 0 ADV7197 A Logic “0” on the LSB of the first byte means that the master will write information to the peripheral. A Logic “1” on the LSB of the first byte means that the master will read information from the peripheral. SDATA SCLOCK S 1–7 8 9 1–7 8 9 START ADDR R/W ACK SUBADDRESS ACK The ADV7197 acts as a standard slave device on the bus. The data on the SDA pin is 8 bits long supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a Stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. 1–7 DATA 8 9 P ACK STOP Figure 9. Bus Data Transfer Figure 9 illustrates an example of data transfer for a read sequence and the Start and Stop conditions. Figure 10 shows bus write and read sequences. REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7197 except the Subaddress Registers, which are write-only registers. The Subaddress Register determines which register is accessed by the next read or write operation. Stop and Start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period the user should issue only one Start condition, one Stop condition or a single Stop condition followed by a single Start condition. If an invalid subaddress is issued by the user, the ADV7197 will not issue an acknowledge and will return to the idle condition. If in auto-increment mode, the user exceeds the highest subaddress, the following action will be taken: All communications with the part through the bus begin with an access to the Subaddress Register. A read/write operation is performed from/to the target address which then increments to the next address until a Stop command on the bus is performed. REGISTER PROGRAMMING The following section describes the functionality of each register. All registers can be read from as well as written to unless otherwise stated. 1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A noacknowledge condition is where the SDA line is not pulled low on the ninth pulse. Subaddress Register (SR7–SR0) The Communications Register is an eight bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place. 2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7197 and the part will return to the idle condition. Figure 11 shows the various operations under the control of the Subaddress Register. “0” should always be written to SR7. Register Select (SR6–SR0) These bits are set up to point to the required starting address. WRITE SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) LSB = 0 READ SEQUENCE S SLAVE ADDR A(S) S = START BIT P = STOP BIT DATA A(S) P LSB = 1 SUB ADDR A(S) S A(S) SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER DATA DATA A(M) A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 10. Write and Read Sequence SR7 SR6 SR5 SR7 ZERO SHOULD BE WRITTEN HERE SR3 SR4 SR2 ADV7197 SUBADDRESS REGISTER ADDRESS SR6 SR5 SR4 SR3 SR2 SR1 SR0 00h 01h 02h 03h 04h 05h 06h 07h 08h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Figure 11. Subaddress Registers REV. 0 SR1 –11– MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 COLOR Y COLOR CR COLOR CB SR0 A(M) P ADV7197 MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) data is input with embedded EAV/SAV codes. An Asynchronous timing mode is also available using TSYNC, SYNC and DV as input control signals. Figure 14 shows the various operations under the control of Mode Register 0. These timing control signals have to be programmed by the user and are used for any other high definition standard input but SMPTE274M and SMPTE296M. MR0 BIT DESCRIPTION Output Standard Selection (MR00–MR01) Figure 12 shows an example of how to program the ADV7197 to accept a different high definition standard but SMPTE274M or SMPTE296M. These bits are used to select the output levels from the ADV7197. If EIA 770.3 (MR01–00 = “00”) is selected, the output levels will be: 0 mV for blanking level, 700 mV for peak white (Y channel), ± 350 mV for Pr, Pb outputs and –300 mV for tri-level sync. Reserved (MR04) A “0” must be written to this bit. Input Standard (MR05) If Full Input Range (MR01–00 = “10”) is selected, the output levels will be 700 mV for peak white for the Y channel, ±350 mV for Pr, Pb outputs, and –300 mV for Sync. This mode is used for RS-170, RS-343A standard output compatibility. Select between 1080i or 720p input. DV Polarity (MR06) This control bit allows to select the polarity of the DV input control signal to be either active high or active low. This is in order to facilitate interfacing from input devices which use an active high blanking signal output. Sync insertion on the Pr, Pb channels is optional. For output levels refer to the Appendix. Input Control Signals (MR02–MR03) Reserved (MR07) These control bits are used to select whether data is input with external horizontal, vertical, and blanking sync signals or if the A “0” must be written to this bit. CLK SYNC PROGRAMMABLE INPUT TIMING TSYNC DV SET MR06 = ‘1’ ACTIVE VIDEO HORIZONTAL SYNC ANALOG OUTPUT 81 66 66 A B 243 1920 D C E Figure 12. Async Timing Mode—Programming Input Control Signals for SMPTE295M Compatibility DISPLAY DISPLAY VERTICAL BLANKING INTERVAL 747 748 749 750 1 2 3 4 5 6 7 8 25 26 27 744 745 HSYNC VSYNC DV Figure 13. DV Input Control Signal in Relation to Video Output Signal for SMPTE296M (720p) –12– REV. 0 ADV7197 MR07 MR06 MR05 MR04 INPUT STANDARD MR07 0 1 MR02 MR04 MR05 ZERO MUST BE WRITTEN TO THIS BIT MR03 INPUT CONTROL SIGNALS MR03 MR02 ZERO MUST BE WRITTEN TO THIS BIT 1080I 720P 0 0 1 1 HSYNC\VSYNC/DV EAV/SAV TSYNC/SYNC/DV RESERVED 0 1 0 1 OUTPUT STANDARD SELECTION DV POLARITY MR01 MR00 MR06 0 1 MR00 MR01 0 0 1 1 ACTIVE HIGH ACTIVE LOW 0 1 0 1 EIA-770.3 RESERVED FULL I/P RANGE RESERVED Figure 14. Mode Register 0 Table I must be followed when programming the control signals in Async Timing Mode. When this bit is set to “1,” pixel data is accepted at the input pins and the ADV7197 outputs to the standard set in “Output Standard Selection” (MR01–MR00). This bit also must be set to “1” to enable output of the test pattern signals. Table I. Truth Table Input Format (MR11) SYNC TSYNC DV 1 –> 0 0 0 or 1 It is possible to input data in 4:2:2 format or in 4:4:4 format. 0 0 –> 1 0 or 1 0 –> 1 0 or 1 0 1 1 0 or 1 0 or 1 0 –> 1 1 –> 0 50% Point of Falling Edge of Tri-Level Horizontal Sync Signal, a 25% Point of Rising Edge of Tri-Level Horizontal Sync Signal, b 50% Point of Falling Edge of Tri-Level Horizontal Sync Signal, c 50% Start of Active Video, d 50% End of Active Video, e Test Pattern Enable (MR12) Enables or disables the internal test pattern generator. Test Pattern Hatch/Frame (MR13) If this bit is set to “0,” a cross hatch test pattern is output from the ADV7197. The cross hatch test pattern can be used to test monitor convergence. If this bit is set to “1,” a uniform colored frame/field test pattern is output from the ADV7197. The color of the lines or the frame/field is by default white but can be programmed to be any color using the Color Y, Color Cr, Color Cb Registers. VBI Open (MR14) MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H) This bit enables or disables the facility of VBI data insertion during the Vertical Blanking Interval. For this purpose Lines 7–20 in 1080i and Lines 6–25 in 720p can be used for VBI data insertion. Figure 15 shows the various operations under the control of Mode Register 1. Reserved (MR15–MR17) MR1 BIT DESCRIPTION Pixel Data Enable (MR10) A “0” must be written to these bits. When this bit is set to “0,” the pixel data input to the ADV7197 is blanked such that a black screen is output from the DACs. MR17 MR16 MR15 MR14 MR17–MR15 ZERO MUST BE WRITTEN TO THESE BITS MR13 MR12 MR10 MR12 MR14 0 1 DISABLED ENABLED DISABLED ENABLED TEST PATTERN HATCH/FRAME MR13 0 1 0 1 INPUT FORMAT MR11 HATCH FIELD/FRAME Figure 15. Mode Register 1 REV. 0 PIXEL DATA ENABLE TEST PATTERN ENABLE VBI OPEN 0 1 MR10 MR11 –13– 0 1 4:4:4 YCrCb 4:2:2 YCrCb DISABLED ENABLED ADV7197 MODE REGISTER 2 MR1 (MR27–MR20) (Address (SR4–SR0) = 02H) MODE REGISTER 3 MR3 (MR37–MR30) (Address (SR4–SR0) = 03H) Figure 17 shows the various operations under the control of Mode Register 2. Figure 18 shows the various operations under the control of Mode Register 3. MR2 BIT DESCRIPTION Y Delay (MR20–MR22) MR3 BIT DESCRIPTION Reserved (MR31–MR32) With these bits it is possible to delay the Y signal with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. Figure 16 demonstrates this facility. A “0” must be written to these bits. DAC A Control (MR33) Setting this bit to “1” enables DAC A, otherwise this DAC is powered down. Color Delay (MR23–MR25) With theses bits it is possible to delay the color signals with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. Figure 16 demonstrates this facility. DAC B Control (MR34) Reserved (MR26–MR27) DAC C Control (MR35) Setting this bit to “1” enables DAC B, otherwise this DAC is powered down. A “0” must be written to these bits. Y DELAY Setting this bit to “1” enables DAC C, otherwise this DAC is powered down. Reserved (MR36–MR37) NO DELAY Y OUTPUT A “0” must be written to these bits. MAX DELAY NO DELAY PrPb DELAY PrPb OUTPUTS MAX DELAY Figure 16. Y and Color Delay MR27 MR26 MR25 MR24 MR27–MR26 ZERO MUST BE WRITTEN TO THESE BITS MR23 MR22 MR21 Y DELAY COLOR DELAY MR25 MR24 0 0 0 0 1 0 0 1 1 0 MR22 MR21 MR23 0 1 0 1 0 MR20 0 PCLK 1 PCLK 2 PCLK 3 PCLK 4 PCLK 0 0 0 0 1 0 0 1 1 0 MR20 0 1 0 1 0 0 PCLK 1 PCLK 2 PCLK 3 PCLK 4 PCLK Figure 17. Mode Register 2 MR37 MR36 MR35 MR34 MR33 MR34 0 1 POWER-DOWN NORMAL DAC C CONTROL MR35 0 1 MR31 MR30 MR32–MR30 DAC B CONTROL MR37–MR36 ZERO MUST BE WRITTEN TO THESE BITS MR32 ZERO MUST BE WRITTEN TO THESE BITS DAC A CONTROL MR33 POWER-DOWN NORMAL 0 1 POWER-DOWN NORMAL Figure 18. Mode Register 3 –14– REV. 0 ADV7197 MODE REGISTER 4 MR4 (MR47–MR40) (Address (SR4–SR0) = 04H) Color Output Swap (MR53) By default DAC B is configured as the Pr output and DAC C as the Pb output. In setting this bit to “1” the DAC outputs can be swapped around so that DAC B outputs Pb and DAC C outputs Pr. The table below demonstrates this in more detail. This control is also available in RGB mode. Figure 19 shows the various operations under the control of Mode Register 4. MR4 BIT DESCRIPTION Timing Reset (MR40) Reserved (MR54–MR57) Toggling MR40 from low to high and low again resets the internal horizontal and vertical timing counters. A “0” must be written to these bits. Table II. Relationship Between Color Input Pixel Port, MR53 and DAC B, DAC C Outputs MODE REGISTER 5 MR5 (MR57–MR50) (Address (SR4-SR0) = 05H) In 4:4:4 Input Mode Figure 20 shows the various operations under the control of Mode Register 5. MR5 BIT DESCRIPTION Reserved (MR50) This bit is reserved for the revision code. Color Data Input on Pins MR53 Analog Output Signal Cr9–0 Cb/Cr9–0 Cr9–0 Cb/Cr9–0 0 0 1 1 DAC B DAC C DAC C DAC B Color Data Input on Pins MR53 Analog Output Signal Cr9–0 Cb/Cr9–0 Cb/Cr9–0 0 or 1 0 1 Not Operational DAC C (Pb) DAC C (Pr) RGB Mode (MR51) When RGB mode is enabled (MR51 = “1”) the ADV7197 accepts unsigned binary RGB data at its input port. This control is also available in Async Timing Mode. In 4:2:2 Input Mode Sync on PrPb (MR52) By default the color component output signals Pr, Pb do not contain any horizontal sync pulses. They can be inserted when MR52 = “1.” This control is not available in RGB mode. MR47 MR46 MR45 MR44 MR43 MR42 MR40 MR41 TIMING RESET MR47–MR41 ZERO MUST BE WRITTEN TO THESE REGISTERS MR40 Figure 19. Mode Register 4 MR57 MR56 MR55 MR54 MR53 MR52 MR57–MR54 MR51 SYNC ON PrPb ZERO MUST BE WRITTEN TO THESE BITS MR50 MR52 0 1 RESERVED FOR REVISION CODE DISABLE ENABLE COLOR OUTPUT SWAP MR53 0 1 –15– RGB MODE MR51 DAC B = Pr DAC C = Pr Figure 20. Mode Register 5 REV. 0 MR50 0 1 DISABLE ENABLE ADV7197 COLOR Y CY (CY7–CY0) (Address (SR4–SR0) = 06H) CY7 CY6 CY5 CY4 DAC TERMINATION AND LAYOUT CONSIDERATIONS Voltage Reference CY3 CY2 CY1 The ADV7197 contains an on-board voltage reference. The VREF pin is normally terminated to VAA through a 0.1 µF capacitor when the internal VREF is used. Alternatively, the ADV7197 can be used with an external VREF (AD589). CY0 CY7–CY0 Resistor RSET is connected between the RSET pin and analog ground and is used to control the full scale output current and therefore the DAC voltage output levels. For full-scale output RSET must have a value of 2470 Ω. RLOAD has a value of 300 Ω. When an input range of 0–1023 is selected the value of RSET must be 2820 Ω. COLOR Y VALUE Figure 21. Color Y Register COLOR CR CCR (CCR7–CCR0) (Address (SR4–SR0) = 07H) CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 The ADV7197 has three analog outputs, corresponding to Y, Pr, Pb video signals. The DACs must be used with external buffer circuits in order to provide sufficient current to drive an output device. A suitable op amp would be the AD8057. CCR0 CCR7–CCR0 PC BOARD LAYOUT CONSIDERATIONS COLOR CR VALUE The ADV7197 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7197, it is imperative that great care be given to the PC board layout. Figure 22. Color Cr Register COLOR CB CCB (CCB7–CCB0) (Address (SR4–SR0) = 08H) CCB7 CCB6 CCB5 CCB4 CCB3 CCB2 CCB1 The layout should be optimized for lowest noise on the ADV7197 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and AGND and VDD and DGND pins should be kept as short as possible to minimized inductive ringing. CCB0 CCB7–CCB0 It is recommended that a four-layer printed circuit board is used. With power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. Placement of components should consider to separate noisy circuits, such as crystal clocks, high-speed logic circuitry and analog circuitry. COLOR CB VALUE Figure 23. Color Cb Register These three 8-bit-wide registers are used to program the output color of the internal test pattern generator, be it the lines of the cross hatch pattern or the uniform field test pattern. The standard used for the values for Y and the color difference signals to obtain white, black and the saturated primary and complementary colors conforms to the ITU-R BT 601-4 standard. The Table III shows sample color values to be programmed into the color registers. There should be a separate analog ground plane (AGND) and a separate digital ground plane (GND). Power planes should encompass a digital power plane (VDD) and a analog power plane (VAA). The analog power plane should contain the DACs and all associated circuitry, and the VREF circuitry. Sample Color Color Y Value Color Cr Value Color Cb Value The digital power plane should contain all logic circuitry. The analog and digital power planes should be individually connected to the common power plane at one single point through a suitable filtering device, such as a ferrite bead. White Black Red Green Blue Yellow Cyan Magenta 235 (EB) 16 (10) 81 (51) 145 (91) 41 (29) 210 (D2) 170 (AA) 106 (6A) 128 (80) 128 (80) 240 (F0) 34 (22) 110 (6E) 146 (92) 16 (10) 222 (DE) 128 (80) 128 (80) 90 (5A) 54 (36) 240 (F0) 16 (10) 166 (A6) 202 (CA) DAC output traces on a PCB should be treated as transmission lines. It is recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches. The DAC termination resistors should be placed as close as possible to the DAC outputs and should overlay the PCB’s ground plane. As well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry. Table III. Sample Color Values –16– REV. 0 ADV7197 Due to the high clock rates used, long clock lines to the ADV7197 should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane. Supply Decoupling Noise on the analog power plane can be further reduced by the use of decoupling capacitors. Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of group of VAA or VDD pins should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. Analog Signal Interconnect The ADV7197 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω. This termination resistance should be as close as possible to the ADV7197 to minimize reflections. Digital Signal Interconnect The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Any unused inputs should be tied to ground. POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP VAA 10nF 0.1F VDD VAA 10nF 0.1F 0.1F 24, 35 COMP VAA 1, 12 VDD DAC A Cb/Cr0–Cb/Cr9 Y OUTPUT 300 ADV7197 Cr0–Cr9 Pr(V) OUTPUT DAC B Y0–Y9 UNUSED INPUTS SHOULD BE GROUNDED 300 HSYNC/SYNC Pb(U) OUTPUT DAC C VSYNC/TSYNC 300 VDD DV VDD 100 5k VDD 5k SCL 4.7k 100 SDA RESET 4.7F 6.3V VREF 27MHz, 74.25MHz OR 74.1758MHz CLOCK RSET CLKIN 2.47k OR 2.82k VAA ALSB AGND 26, 33 GND 13, 52 4.7k Figure 24. Circuit Layout REV. 0 –17– MPU BUS ADV7197 To calculate the output full-scale current and voltage, the following equations should be used: Video Output Buffer and Optional Output Filter Output buffering is necessary in order to drive output devices, such as HDTV monitors. VOUT = IOUT × RLOAD Analog Devices produces a range of suitable op amps for this application. A suitable op amp would be the AD8057. More information on line driver buffering circuits is given in the relevant op amp data sheets. IOUT = (VREF × K)/RSET where: An optional analog reconstruction LPF might be required as an antialias filter if the ADV7197 is connected to a device that requires this filtering. K = 5.66 (for input ranges 64–940, 64–960, output standards EIA770.3) K = 6.46 (for input ranges 0–1023, output standards RS170/343A The Eval ADV7196/ADV7197EB evaluation board uses the ML6426 Microlinear IC, which provides buffering and low-pass filtering for HDTV applications. VREF = 1.235 V. The Eval ADV7196/ADV7197EB Rev. B and Rev. C evaluation boards use the AD8057 as a buffer and a 6th order LPF. The Application Note, AN-TBD, describes in detail these two designs and should be consulted when designing external filter and buffers for Analog Devices Video Encoders. +5V 0.1F 10F LPF 75 COAX AD8057 75 75 0.1F 10F –5V HDTV MONITOR 5V DAC A 0.1F ADV7197 DAC B 10F LPF 75 COAX AD8057 75 75 DAC C 0.1F 10F 0.1F 10F 5V +5V LPF 75 COAX AD8057 75 75 0.1F 10F –5V Figure 25. Output Buffer and Optional Filter –18– REV. 0 ADV7197 INPUT CODE EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE 940 INPUT CODE Y-OUTPUT LEVELS FOR FULL I/P SELECTIONS 1023 700mV ACTIVE VIDEO ACTIVE VIDEO 300mV 64 0mV 64 OUTPUT VOLTAGE 700mV 0mV –300mV –300mV INPUT CODE PrPb-OUTPUT LEVELS FOR FULL I/P SELECTIONS OUTPUT VOLTAGE EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE 960 1023 700mV 350mV 300mV ACTIVE VIDEO ACTIVE VIDEO 0mV 512 64 0mV –300mV –300mV –350mV 64 Figure 26. EIA 770.3 Standard Output Signals (1080i, 720p) Figure 27. Output Levels for Full I/P Selection REGISTER SETTINGS Register Settings on Power-Up REGISTER SETTINGS Internal Colorbars (Field), HDTV Mode Address 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Color Y Color Cr Color Cb Register Setting Address 00hex 00hex 00hex 39hex 00hex 00hex A0hex 80hex 80hex 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex Register Setting Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Color Y Color Cr Color Cb 00hex 0Dhex 00hex 39hex 00hex 00hex xxhex xxhex xxhex 0HDATUM SMPTE274M DIGITAL HORIZONTAL BLANKING ANALOG WAVEFORM INPUT PIXELS 4T 272T 4T 1920T EAV CODE ANCILLARY DATA (OPTIONAL) OR BLANKING CODE SAV CODE DIGITAL ACTIVE LINE 4 CLOCK SAMPLE NUMBER C F 0 0 F C Y r F 0 0 V b H* F 0 0 F F 0 0 V H* 2112 2116 2156 2199 C Y r 4 CLOCK 0 44 188 192 2111 FVH* = FVH AND PARITY BITS SAV/EAV: LINES 1–562: F = 0 SAV/EAV: LINES 563–1125: F = 1 SAV/EAV: LINES 1–20; 561–583; 1124–1125: V = 1 SAV/EAV: LINES 21–560; 584–1123: V = 0 Figure 28. EAV/SAV Input Data Timing Diagram—SMPTE274M (1080i) REV. 0 –19– ADV7197 DISPLAY VERTICAL BLANKING INTERVAL 749 750 1 2 3 5 4 7 6 8 25 26 744 27 745 C02155–1.5–4/01(0) 748 Figure 29. SMPTE296M (720p) DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 DISPLAY FIELD 2 VERTICAL BLANKING INTERVAL 562 563 564 565 566 567 568 569 570 583 584 585 1123 Figure 30. SMPTE274M (1080i) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (MQFP) (S-52) 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91) 0.094 (2.39) 0.084 (2.13) 0.037 (0.95) 0.026 (0.65) 52 1 40 39 PRINTED IN U.S.A. 561 PIN 1 SEATING PLANE 0.398 (10.11) 0.390 (9.91) 0.557 (14.15) 0.537 (13.65) 747 TOP VIEW (PINS DOWN) 0.012 (0.30) 0.006 (0.15) 0.008 (0.20) 0.006 (0.15) 13 14 0.082 (2.09) 0.078 (1.97) 0.0256 (0.65) BSC –20– 27 26 0.014 (0.35) 0.010 (0.25) REV. 0