TPCL4203
MOSFETs
Silicon N-Channel MOS (U-MOS)
TPCL4203
1. Applications
•
Dedicated to Single-Cell Lithium-Ion Secondary Battery Applications
Note:
The product(s) described herein should not be used for any other application.
2. Features
(1)
Small, thin package
(2)
Low source-source on-resistance: RSS(ON) = 27 mΩ (typ.) (VGS = 4.5 V)
(3)
Low leakage current: ISSS = 10 µA (max) (VSS = 24 V)
(4)
Enhancement mode: Vth = 0.5 to 1.2 V (VSS = 10 V, IS = 200 µA)
(5)
Common drain
3. Packaging and Internal Circuit
1: Source 1
2: Gate 1
3: Gate 2
4: Source 2
ChipLGA
unless otherwise specified)
25
4. Absolute Maximum Ratings (Note) (Ta = 25
Characteristics
Symbol
Rating
Unit
V
Source-source voltage
VSSS
24
Gate-source voltage
VGSS
±12
Source current (DC)
(Note 1)
IS
6
Source current (pulsed)
(Note 1)
ISP
24
A
Power dissipation
(t = 10 s)
(Note 2), (Note 4)
PD
0.50
W
Power dissipation
(t = 10 s)
(Note 3), (Note 4)
PD
1.65
W
Channel temperature
Tch
150
Storage temperature
Tstg
-55 to 150
Note:
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
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5. Thermal Characteristics
Characteristics
Symbol
Max
Unit
Channel-to-ambient thermal resistance
(t = 10 s)
(Note 2), (Note 4)
Rth(ch-a)
250
/W
Channel-to-ambient thermal resistance
(t = 10 s)
(Note 3), (Note 4)
Rth(ch-a)
75.8
/W
Note 1: Ensure that the channel temperature does not exceed 150.
Note 2: Device mounted on a glass-epoxy board (a), Figure 5.1
Note 3: Device mounted on a glass-epoxy board (b), Figure 5.2
Note 4: Equal voltage applied to FET1 and FET2.
Fig. 5.1 Device Mounted on a Glass-Epoxy Board (a)
Fig. 5.2 Device Mounted on a Glass-Epoxy Board (b)
Note:
This transistor is sensitive to electrostatic discharge and should be handled with care.
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6. Safety Precautions
This section lists important precautions which users of semiconductor devices (and anyone else) should observe
in order to avoid injury to human body and damage to property, and to ensure safe and correct use of our products.
Please be sure that you understand the meanings of the labels and graphic symbols described below before you
move on to the detailed descriptions of the precautions, and comply with the precautions stated.
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7. Electrical Characteristics
unless otherwise specified)
7.1. Static Characteristics (Ta = 25
25
Characteristics
Symbol
Gate leakage current
(Note 5)
Source cut-off current
Source-source breakdown
voltage
Gate threshold voltage
(Note 5)
Source-source on-resistance
(Note 6)
RSS(ON)
Test Condition
Min
Typ.
Max
Unit
±0.1
µA
IGSS
VGS = ±12 V, VDS = 0 V
(Note 5)
ISSS
VSS = 24 V, VGS = 0 V
10
(Note 5)
V(BR)SSS
IS = 10 mA, VGS = 0 V
24
V(BR)SSX
IS = 10 mA, VGS = -12 V
12
Vth
VSS = 10 V, IS = 200 µA
0.5
1.2
VGS = 2.5 V, IS = 3 A
30
42
55
VGS = 3.1 V, IS = 3 A
26
33
46
VGS = 4.0 V, IS = 3 A
23
29
38
VGS = 4.5 V, IS = 3 A
22
27
36
Min
Typ.
Max
Unit
685
pF
V
mΩ
unless otherwise specified)
7.2. Dynamic Characteristics (Ta = 25
25
Characteristics
Symbol
Ciss
Test Condition
Input capacitance
(Note 5)
VSS = 10 V, VGS = 0 V, f = 1 MHz
Reverse transfer capacitance
(Note 5)
Crss
100
Output capacitance
(Note 5)
Coss
145
Switching time (rise time)
(Note 5)
tr
85
Switching time (turn-on time)
(Note 5)
ton
120
Switching time (fall time)
(Note 5)
tf
210
Switching time (turn-off time)
(Note 5)
toff
370
See Figure 7.2.1.
ns
Fig. 7.2.1 Switching Time Test Circuit
unless otherwise specified)
25
7.3. Gate Charge Characteristics (Ta = 25
Characteristics
Symbol
Total gate charge (gatesource plus gate-drain)
(Note 5)
Qg
Gate-source charge 1
(Note 5)
Qgs1
Test Condition
VSS(PS) ≈ 19 V, VGS = 5 V, IS = 6 A
Min
Typ.
Max
Unit
10
nC
1.7
unless otherwise specified)
7.4. Source-Source Characteristics (Ta = 25
25
Characteristics
Diode forward voltage
Symbol
(Note 7)
VSSF
Test Condition
ISR = 3 A, VGS = 0 V
Min
Typ.
Max
Unit
-1.2
V
Note 5: FET1 is measured with the gate and source pins of FET2 shorted. FET2 is measured with the gate and source
pins of FET1 shorted.
Note 6: Measured with the indicated gate-to-source voltage (VGS) applied to both FET1 and FET2.
Note 7: FET1 is measured with 4.5 V applied between the gate and source pins of FET2. FET2 is measured with 4.5
V applied between the gate and source pins of FET1.
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8. Marking
Fig. 8.1 Marking
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9. Mounting Condition
This device should be soldered onto a pc board with up to two reflow passes at the recommended reflow conditions.
The second reflow process should be performed within two weeks after the first reflow process.
9.1. Using Infrared Reflow
(1)
It is recommended the top and bottom heating method with long or medium infrared rays. (See Figure
9.1.1.)
(2)
Figure 9.1.2 shows the recommended temperature profile for using eutectic solder. Figure 9.1.3 shows the
recommended temperature profile for using lead (Pb)-free solder. Complete the infrared ray reflow
process with a maximum package surface temperature of 260, within 30 to 50 seconds when a package
surface temperature is 230 or higher (See Figure 9.1.3).
Fig. 9.1.1 Heating the Top and Bottom with Long or Medium Infrared Rays
Fig. 9.1.2 Eutectic Recommended Temperature
Profile
Fig. 9.1.3 Lead (Pb)-Free Recommended
Temperature Profile
9.2. Using Hot Air Reflow
For an example of a recommended temperature profile, refer to Figures 9.1.2 and 9.1.3.
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9.3. Mechanical Stress
This device is very small and thin. Excessive mechanical stress may damage the package and/or chip. To avoid
damage to the device, the distortion factor should be kept below 2000 µε or within the shaded area in Figure
9.3.1. Keep in mind that the stress applied to the device varies, depending on the shape, material, trace patterns,
parts layout and other conditions of the pc board. Thus the integrity of the device should be tested on the actual
application board. In addition, the end product should provide adequate headroom above the top (marking) side
of the device so that no mechanical stress will be applied to it.
The distortion factor (ε) is given by:
ε = 6 h S/ (L × L), h: Board thickness, S = Bend, L = Support-to-support distance
Fig. 9.3.1 Support-to-Support Distance vs. Bending
9.4. Test Method
Test method (reference standard JEITA ED-4702A):
The test board is placed on supports with the device face-down. The supports are placed with a distance of 24
mm as shown in Figure 9.4.1 below. Stress is applied to the test board as shown in Figure 9.4.2.
Test board: FR-4 glass epoxy board measuring 30.8 mm × 5 mm × 0.6 mm
A rigid pc board with a thickness of 0.4 mm or more should be used for actual applications.
Fig. 9.4.1 Placement
Fig. 9.4.2 During Testing
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10. Characteristics Curves (Note)
Fig. 10.1 IS - VSS (Note 6)
Fig. 10.2 IS - VSS (Note 6)
Fig. 10.3 IS - VGS (Note 5)
Fig. 10.4 VSS - VGS (Note 6)
Fig. 10.5 RSS(ON) - IS (Note 6)
Fig. 10.6 RSS(ON) - Ta (Note 6)
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Fig. 10.7 ISR - VSS (Note 7)
Fig. 10.8 Capacitance - VSS (Note 5)
Fig. 10.9 Vth - Ta (Note 5)
Fig. 10.10 Dynamic Input/Output Characteristics
(Note 5)
Fig. 10.11 PD - Ta (Note 4)
(Guaranteed Maximum)
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Fig. 10.12 rth - tw (Note 4)
(Guaranteed Maximum)
Fig. 10.13 Safe Operating Area (Note 4)
(Guaranteed Maximum)
Note:
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
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Package Dimensions
Unit: mm
Weight: 0.00147 g (typ.)
Package Name(s)
TOSHIBA: 2-2W1S
Nickname: ChipLGA
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RESTRICTIONS ON PRODUCT USE
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information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the
precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application
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