TC74VHC161,163F/FT/FK
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VHC161F,TC74VHC161FT,TC74VHC161FK
TC74VHC163F,TC74VHC163FT,TC74VHC163FK
Synchronous Presettable 4-Bit Counter
TC74VHC161F/FT/FK
Binary, Asynchronous
Clear
TC74VHC163F/FT/FK Binary, Synchronous
Clear
The TC74VHC 161 and 163 are advanced high speed CMOS
SYNCHRONOUS PRESETTABLE 4 BIT BINARY COUNTERs
fabricated with silicon gate C2MOS technology.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The CK input is active on the rising edge. Both LOAD and
CLR inputs are active on low logic level.
Presetting of each IC’s is synchronous to the rising edge of CK.
The clear function of the TC74VHC163 is synchronous to CK,
while the TC74VHC161 are cleared asynchronously.
Two enable inputs (ENP and ENT) and CARRY OUTPUT are
provided to enable easy cascading of counters, which facilitates
easy implementation of n-bit counters without using external
gates.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
TC74VHC161F, TC74VHC163F
TC74VHC161FT, TC74VHC163FT
TC74VHC161FK, TC74VHC163FK
Features
•
High speed: fmax = 185 MHz (typ.) at VCC = 5 V
Weight
•
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
SOP16-P-300-1.27A
: 0.18 g (typ.)
•
High noise immunity: VNIH = VNIL = 28% VCC (min)
TSSOP16-P-0044-0.65A
: 0.06 g (typ.)
•
•
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼
− tpHL
VSSOP16-P-0030-0.50
: 0.02 g (typ.)
•
Wide operating voltage range: VCC (opr) = 2 to 5.5 V
•
Low noise: VOLP = 0.8 V (max)
•
Pin and function compatible with 74ALS161/163
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TC74VHC161,163F/FT/FK
Pin Assignment
CLR
1
16
VCC
CK
2
15
CARRY OUTPUT
A
3
14
QA
B
4
13
QB
C
5
12
QC
D
6
11
QD
ENP
7
10
ENT
GND
8
9
LOAD
(top view)
IEC Logic Symbol
CLR
LOAD
ENT
ENP
CK
A
B
C
D
(1)
(9)
(10)
(7)
(2)
(3)
(4)
(5)
(6)
TC74VHC161
CTRDIV 16
CT = 0
M1
M2
3CT = 15
G3
G4
CLR
LOAD
(15)
CARRY OUTPUT
ENT
ENP
CK
C5/2, 3, 4+
1, 5D
(14)
(13)
(12)
(11)
[1]
[2]
[4]
[8]
A
B
C
D
QA
QB
QC
QD
(1)
(9)
(10)
(7)
(2)
(3)
(4)
(5)
(6)
TC74VHC163
CTRDIV 16
5CT = 0
M1
M2
3CT = 15
G3
G4
(15)
CARRY OUTPUT
C5/2, 3, 4+
1, 5D
(14)
(13)
(12)
(11)
[1]
[2]
[4]
[8]
QA
QB
QC
QD
Truth Table (Note)
TC74VHC161
TC74VHC163
Inputs
Inputs
Outputs
CLR
LD
ENP
ENT
CK
CLR
LD
ENP
ENT
L
X
X
X
X
L
X
X
X
H
L
X
X
H
L
X
X
A
H
H
X
L
H
H
X
L
No Change
No Count
H
H
L
X
H
H
L
X
No Change
No Count
H
H
H
H
H
H
H
H
Count Up
Count
H
X
X
X
X
X
X
X
No Change
No Count
Note:
CK
Function
QA
QB
QC
QD
L
L
L
L
B
C
D
Reset to “0”
Preset Data
X: Don’t care
A, B, C, D: Logic level of data inputs
Carry: CARRY = ENT･QA･QB･QC･QD
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TC74VHC161,163F/FT/FK
Timing Chart
CLR
LOAD
A
Data
Inputs
DON’T CARE UNTIL LOAD GOES LOW
B
C
D
CK
ENP
ENT
QA
QB
Outputs
QC
QD
CARRY
12
13
ASYNC SYNC PRESET
CLEAR CLEAR
(161) (163)
14
15
0
COUNT
3
1
2
INHIBIT
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TC74VHC161,163F/FT/FK
System Diagram
1
CLR
7
ENP
E
10
ENT
E
9
LOAD
L
L
15 CARRY
OUT
3
A
(Note)
L
D R Q
L
E
CK
E
Q
QA
4
B
(Note)
L
L
E
D R Q
E
CK
Q
13
QB
5
C
(Note)
L
L
E
D R Q
E
CK
Q
12
QC
6
D
(Note)
L
L
E
D R Q
E
CK
2
CK
Note:
14
Q
11
QD
Truth table of internal F/F
TC74VHC161
TC74VHC163
D
CK
R
Q
Q
D
X
X
H
L
H
L
L
H
L
H
L
X
L
R
Q
Q
X
H
L
H
H
L
L
L
H
L
H
L
H
L
X
X
No Change
CK
No Change
X: Don’t care
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TC74VHC161,163F/FT/FK
Absolute Maximum Ratings (Note)
Characteristics
Symbol
Rating
Unit
Supply voltage range
VCC
−0.5 to 7.0
V
DC input voltage
VIN
−0.5 to 7.0
V
VOUT
−0.5 to VCC + 0.5
V
Input diode current
IIK
−20
mA
Output diode current
IOK
±20
mA
DC output current
IOUT
±25
mA
DC VCC/ground current
ICC
±50
mA
Power dissipation
PD
180
mW
Storage temperature
Tstg
−65 to 150
°C
DC output voltage
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Operating Range (Note)
Characteristics
Symbol
Rating
Unit
Supply voltage
VCC
2.0 to 5.5
V
Input voltage
VIN
0 to 5.5
V
VOUT
0 to VCC
V
Operating temperature
Topr
−40 to 85
°C
Input rise and fall time
dt/dv
Output voltage
Note:
0 to 100 (VCC = 3.3 ± 0.3 V)
0 to 20 (VCC = 5 ± 0.5 V)
ns/V
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
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TC74VHC161,163F/FT/FK
Electrical Characteristics
DC Characteristics
Test Condition
Characteristics
Symbol
VCC
(V)
2.0
High-level input
voltage
VIH
3.0
to
5.5
―
Min
1.50
Typ.
Max
―
―
High-level output
voltage
Low-level output
voltage
VIL
VOH
VOL
VIN
= VIH or
VIL
1.50
―
―
―
―
―
VCC ×
0.3
―
VCC ×
0.3
2.0
1.9
2.0
―
1.9
―
IOH = −50 μA
3.0
2.9
3.0
―
2.9
―
4.5
4.4
4.5
―
4.4
―
IOH = −4 mA
3.0
2.58
―
―
2.48
―
IOH = −8 mA
4.5
3.94
―
―
3.80
―
2.0
―
0.0
0.1
―
0.1
3.0
―
0.0
0.1
―
0.1
4.5
―
0.0
0.1
―
0.1
IOL = 4 mA
3.0
―
―
0.36
―
0.44
IOL = 8 mA
4.5
―
―
0.36
―
0.44
3.0
to
5.5
IOL = 50 μA
―
0.50
VCC ×
0.7
―
Unit
Max
―
―
VIN
= VIH or
VIL
Min
VCC ×
0.7
2.0
Low-level input
voltage
Ta =
−40 to 85°C
Ta = 25°C
―
V
0.50
V
V
V
Input leakage
current
IIN
VIN = 5.5 or GND
0 to
5.5
―
―
±0.1
―
±1.0
μA
Quiescent supply
current
ICC
VIN = VCC or GND
5.5
―
―
4.0
―
40.0
μA
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TC74VHC161,163F/FT/FK
Timing Requirements (input: tr = tf = 3 ns)
Characteristics
Symbol
Minimum pulse width
tw (L)
(CK)
tw (H)
Minimum pulse width
( CLR )
(Note1)
Minimum set-up time
(A, B, C, D)
Minimum set-up time
( LOAD )
Minimum set-up time
(ENT, ENP)
Minimum set-up time
( CLR )
(Note 2)
Minimum hold time
Minimum hold time
( CLR )
(Note 2)
Minimum removal time
( CLR )
(Note 1)
Ta =
25°C
Ta =
−40 to
85°C
VCC (V)
Limit
Limit
3.3 ± 0.3
5.0
5.0
5.0 ± 0.5
5.0
5.0
3.3 ± 0.3
5.0
5.0
5.0 ± 0.5
5.0
5.0
3.3 ± 0.3
5.5
6.5
5.0 ± 0.5
4.5
4.5
3.3 ± 0.3
8.0
9.5
5.0 ± 0.5
5.0
6.0
3.3 ± 0.3
7.5
9.0
5.0 ± 0.5
5.0
6.0
3.3 ± 0.3
4.0
4.0
5.0 ± 0.5
3.5
3.5
3.3 ± 0.3
1.0
1.0
5.0 ± 0.5
1.0
1.0
3.3 ± 0.3
1.0
1.0
5.0 ± 0.5
1.5
1.5
3.3 ± 0.3
2.5
2.5
5.0 ± 0.5
1.5
1.5
Test Condition
Figure 1
tw (L)
Figure 4
ts
Figure 2
ts
Figure 2
ts
Figure 3
ts
Figure 5
th
Figure 2, Figure 3
th
Figure 5
trem
Figure 4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: For TC74VHC161 only
Note 2: For TC74VHC163 only
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TC74VHC161,163F/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Test Condition
Symbol
VCC (V)
Propagation delay
time
tpLH
(CK-Q)
tpHL
Propagation delay
time
(CK-CARRY,
count-mode)
tpLH
tpHL
Propagation delay
time
(CK-CARRY,
preset-mode)
tpLH
tpHL
Propagation delay
time
tpLH
(ENT-CARRY)
tpHL
Propagation delay
time
( CLR -Q)
3.3 ± 0.3
Figure 1,
Figure 2
5.0 ± 0.5
3.3 ± 0.3
Figure 1
5.0 ± 0.5
3.3 ± 0.3
Figure 2
5.0 ± 0.5
3.3 ± 0.3
Figure 6
5.0 ± 0.5
3.3 ± 0.3
tpHL
Figure 4
(Note 2)
5.0 ± 0.5
Propagation delay
time
3.3 ± 0.3
tpHL
( CLR -CARRY)
Figure 4
5.0 ± 0.5
(Note 2)
3.3 ± 0.3
Maximum clock
frequency
fmax
―
5.0 ± 0.5
Input capacitance
CIN
Power dissipation
capacitance
CPD
Ta =
−40 to 85°C
Ta = 25°C
Unit
CL (pF)
Min
Typ.
Max
Min
Max
15
―
8.3
12.8
1.0
15.0
50
―
10.8
16.3
1.0
18.5
15
―
4.9
8.1
1.0
9.5
50
―
6.4
10.1
1.0
11.5
15
―
8.7
13.6
1.0
16.0
50
―
11.2
17.1
1.0
19.5
15
―
4.9
8.1
1.0
9.5
50
―
6.4
10.1
1.0
11.5
15
―
11.0
17.2
1.0
20.0
50
―
13.5
20.7
1.0
23.5
15
―
6.2
10.3
1.0
12.0
50
―
7.7
12.3
1.0
14.0
15
―
7.5
12.3
1.0
14.5
50
―
10.5
15.8
1.0
18.0
15
―
4.9
8.1
1.0
9.5
50
―
6.4
10.1
1.0
11.5
15
―
8.9
13.6
1.0
16.0
50
―
11.2
17.1
1.0
19.5
15
―
5.5
9.0
1.0
10.5
50
―
7.0
11.0
1.0
12.5
15
―
8.4
13.2
1.0
15.5
50
―
10.9
16.7
1.0
19.0
15
―
5.0
8.6
1.0
10.0
50
―
6.5
10.6
1.0
12.0
15
80
130
―
70
―
50
55
85
―
50
―
15
135
185
―
115
―
50
95
125
―
85
―
―
4
10
―
10
pF
―
23
―
―
―
pF
―
(Note 1)
ns
ns
ns
ns
ns
ns
MHz
Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD･VCC･fIN + ICC
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ΔICC which is
obtained from the following formula:
C
C
C
⎛C
C ⎞
ΔICC = fCK ⋅ VCC ⎜⎜ QA + QB + QC + QD + CO ⎟⎟
4
8
16
16 ⎠
⎝ 2
CQA to CQD and CCO are the capacitances at QA to QD and CARRY OUT, respectively.
fCK is the input frequency of the CK.
Note 2: For TC74VHC161 only
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TC74VHC161,163F/FT/FK
Switching Characteristics Test Waveform
VCC
50％
CLR
twL
twH
CK
50％
GND
twL
VCC
VCC
50％
GND
50％
CK
Q,
CARRY
Q,
CARRY
VOL
tpHL
Figure 1
VOH
50％
50％
tpLH
GND
trem
VOH
Count Mode
Figure 4
50％
tpHL
VOL
Clear Mode (TC74VHC161)
VCC
LOAD
50％
ts
50％
th
ts
GND
th
VCC
A to D
50％
ts
50％
CLR
th
ts
50％
GND
th
VCC
VCC
CK
50％
50％
CK
tpLH, tpHL
GND
VOH
Q,
CARRY
VOL
ENP
ENT
VOH
Q,
CARRY
50％
Figure 2
50％
GND
Preset Mode
Figure 5
VOL
Clear Mode (TC74VHC163)
VCC
50％
ts
50％
th
ts
GND
th
VCC
CK
50％
VCC
ENT
50％
50％
50％
GND
GND
VOH
VOH
50％
CARRY
50％
Q
VOL
Figure 3
Count Enable Mode
tpLH
VOL
tpHL
Figure 6 Cascade Mode
(fix maximum count)
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TC74VHC161,163F/FT/FK
Noise Characteristics (input: tr = tf = 3 ns)
Characteristics
Test Condition
Symbol
Ta = 25°C
VCC (V)
Typ.
Max
Unit
Quiet output maximum dynamic VOL
VOLP
CL = 50 pF
5.0
0.4
0.8
V
Quiet output minimum dynamic VOL
VOLV
CL = 50 pF
5.0
−0.4
−0.8
V
Minimum high level dynamic input voltage
VIHD
CL = 50 pF
5.0
―
3.5
V
Maximum low level dynamic input voltage
VILD
CL = 50 pF
5.0
―
1.5
V
Input Equivalent Circuit
INPUT
Typical Application
Parallel Carry N-Bit Counter
H: COUNT
L: DISABLE
INPUTS
LD A
B
C
INPUTS
D
ENP
H: COUNT
L: DISABLE
ENT
LD A
B
C
INPUTS
D
ENP
CARRY
ENT
LD A
B
C
D
ENP
CARRY
ENT
CARRY
CK
CK
CK
CLR QA QB QC QD
CLR QA QB QC QD
CLR QA QB QC QD
OUTPUTS
OUTPUTS
NEXT
STAGE
OUTPUTS
CLR
CK
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TC74VHC161,163F/FT/FK
Package Dimensions
Weight: 0.18 g (typ.)
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TC74VHC161,163F/FT/FK
Package Dimensions
Weight: 0.06 g (typ.)
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TC74VHC161,163F/FT/FK
Package Dimensions
Weight: 0.02 g (typ.)
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TC74VHC161,163F/FT/FK
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
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