DISCONTINUED MAR 2009 TB62705CPG/CFG/CFNG TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TB62705CPG, TB62705CFG, TB62705CFNG 8-BIT SHIFT REGISTER, LATCHES & CONSTANT-CURRENT DRIVERS The TB62705CPG / CFG / CFNG are specifically designed for LED and LED DISPLAY constant-current drivers. These constant-current output circuits can support the set-up of an external resistor (IOUT = 5~90mA). This IC is a monolithic integrated circuit designed to be used together with Bi-CMOS process. The devices consist of an 8-bit shift register, latch, AND-GATE and constant-current drivers. This devices are a product for the Pb free(Sn-Ag). FEATURES Constant-current Output : current with one resistor for 5 to 90mA. TB62705CPG TB62705CFG Maximum Clock Frequency : fCLK = 15 (MHz) (Cascade Connecte Operate, Topr = 25°C) 5V C−MOS Compatible Input Package : DIP16−P−300−2.54A (TB62705CPG) SSOP16−P−225−1.00A (TB62705CFG) SSOP16−P−225−0.65B (TB62705CFNG) TB62705CFNG Constant Output Current Matching: OUTPUT-GND VOLTAGE CURRENT MATCHING OUTPUT CURRENT ≥ 0.4 V ±6.0% 5~40 mA ≥ 0.7 V ±6.0% 5~90 mA PIN CONNECTION (Top view) Company Headquarters 3 Northway Lane North Latham, New York 12110 Toll Free: 800.984.5337 Fax: 518.785.4725 Weight DIP16−P−300−2.54A : 1.11 g (typ.) SSOP16−P−225−1.00A : 0.14 g (typ.) SSOP16−P−225−0.65B : 0.07 g (typ.) GND 1 16 VDD SERIAL-IN 2 15 R-EXT CLOCK 3 14 SERIAL-OUT LATCH 4 13 ENABLE OUTn 5 12 OUTn OUTn 6 11 OUTn OUTn 7 10 OUTn OUTn 8 9 OUTn Web: www.marktechopto.com | Email: [email protected] TB62705CPG/CFG/CFNG BLOCK DIAGRAM OUTn OUTn OUTn TIMING DIAGRAM 5V 0V 5V 0V 5V 0V 5V 0V CLOCK SERIAL-IN LATCH ENABLE OUT0 Off On Off On Off OUT1 OUT3 On Off 5V 0V OUT7 SERIAL-OUT Note: Latches are level-sensitive, not rising edge-sensitive, and are not synchronized with the CLOCK signal. The data will pass through the latch circuit if the latch input is set at “H” level, and will be retained if the input is set at “L”. 2 2005-10-06 TB62705CPG/CFG/CFNG PIN DESCRIPTION PIN No. PIN NAME FUNCTION 1 GND 2 SERIAL−IN 3 CLOCK Clock input terminal for data shift to up-edge. 4 LATCH Data strobe input terminal. Latches pass LATCH data with “H” level input and retain data with “L” level input. 5~12 OUTn 13 ENABLE 14 SERIAL−OUT 15 R−EXT 16 VDD GND terminal for control logic Input pin for shift register serial data Output terminals Input terminal for output enable. All outputs ( OUTn ) go off with ENABLE data input at "H" level and go on with data input at "L" level. Output terminal for serial data for the next SERIAL-IN terminal. Input terminal for connecting a resistor to regulate all output currents. 5-V supply pin of the IC TRUTH TABLE CLOCK LATCH ENABLE SERIAL−IN OUTn SERIAL−OUT UP H L Dn Dn ··· Dn−5 ··· Dn−7 Dn−7 UP L L Dn+1 No change Dn−6 UP H L Dn+2 Dn+2 ··· Dn−3 ··· Dn−5 Dn−5 DOWN X L Dn+3 Dn+2 ··· Dn−3 ··· Dn−5 Dn−5 DOWN X H Dn+3 Off Dn−5 Note: OUTn = on if Dn = H level, and OUTn = off if Dn = L level. An external resistor is connected with R−EXT and GND. Be sure to administer the correct power supply voltage. INPUT/OUTPUT EQUIVALENT CIRCUITS 1. ENABLE terminal 2. LATCH terminal 3. CLOCK, SERIAL−IN terminal 4. SERIAL−OUT terminal 3 2005-10-06 TB62705CPG/CFG/CFNG MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage VDD 0~7.0 V Input Voltage VIN −0.4~VDD + 0.4 V Output Current IOUT 90 mA Output Voltage VCE −0.5~17.0 V Clock Frequency fCK 15 MHz 720 mA GND Terminal Current Power Dissipation Thermal Resistance IGND 1.47 (CPG−type : FREE AIR, Ta = 25°C) PD W 0.78 (CFG / CFNG−type : ON PCB, Ta = 25°C) Rth (j−a) 85 (CPG−type : FREE AIR, Ta = 25°C) 160 (CFG / CFNG−type : ON PCB, Ta = 25°C) °C / W Operating Temperature Topr −40~85 °C Storage Temperature Tstg −55~150 °C Note: CPG type: For an ambient temperature above 25°C, the derating is 11.8 mW/°C. CFG and CFNG type: For an ambient temperature above 25°C, the derating is 6.3 mW/°C. RECOMMENDED OPERATING CONDITION (Ta = −40~85°C unless otherwise stated) CHARACTERISTIC SYMBOL CONDITION MIN TYP. MAX UNIT Supply Voltage VDD ― 4.5 5.0 5.5 V Output Voltage VOUT ― ― ― 15.0 V OUTn , DC 1 circuit 5 ― 88 Output Current IOH SERIAL−OUT ― ― 1.0 IOL SERIAL−OUT ― ― −1.0 IO VIH ― 0.7 VDD ― VDD +0.3 VIL ― −0.3 ― 0.3 VDD Input Voltage mA V LATCH Pulse Width tw LAT 100 ― ― ns CLOCK Pulse Width tw CLK 50 ― ― ns ENABLE Pulse Width tw EN 4500 ― ― ns VDD = 4.5~5.5 V Set-up Time for DATA tsetup (D) 60 ― ― ns Hold Time for DATA thold (D) 20 ― ― ns Set-up Time for LATCH tsetup (L) 100 ― ― ns Hold Time for LATCH thold (L) Clock Frequency Power Dissipation fCK PD 60 ― ― ns 10.0 ― ― MHz Ta = 85°C (CPG−type FREE AIR) ― ― 0.82 Ta = 85°C (CFG / CFNG−type ON PCB) ― ― 0.40 Cascade operation 4 W 2005-10-06 TB62705CPG/CFG/CFNG ELECTRICAL CHARACTERISTICS (VDD = 5.0 V, Ta = 25°C unless otherwise stated) SYMBOL TEST CIR− CUIT CONDITION MIN TYP. MAX "H" Level VIH ― ― 0.7 VDD ― VDD "L" Level VIL ― ― GND ― 0.3 VDD CHARACTERISTIC Input Voltage Output Leakage Current IOH ― VOH = 15.0 V ― ― 10 VOL ― IOL = 1.0 mA ― ― 0.4 VOH ― IOH = −1.0 mA 4.6 ― ― IOL1 ― VCE = 0.7 V IOL2 ― VCE = 0.4 V ∆IOL1 ― IO = 40 mA, VCE = 0.4 V IOL3 ― VCE = 1.0 V IOL4 ― VCE = 0.7 V ∆IOL2 ― IO = 75 mA, VCE = 0.7 V Supply Voltage Regulation % / VDD Pull−Up Resistor RIN (up) Output Voltage S−OUT Output Current 1 Current Skew Output Current 2 Current Skew Pull−Down Resistor "OFF" Supply Current "ON" UNIT V µA V REXT = 470 Ω (Include skew) 34.1 40.0 45.9 33.7 39.5 45.3 REXT = 470 Ω ― ±1.5 ±6.0 REXT = 250 Ω (Include skew) 64.2 75.5 86.8 63.8 75.0 86.2 REXT = 250 Ω ― ±1.5 ±6.0 % ― REXT = 470 Ω, Ta = −40~85°C ― 1.5 5.0 %/V ― ― 150 300 600 kΩ ― kΩ RIN (down) ― 100 200 400 IDD (off) 1 ― REXT = OPEN, OUT0 ~ 7 = off ― 0.6 1.2 IDD (off) 2 ― REXT = 470 Ω, OUT0 ~ 7 = off 3.5 5.8 8.0 IDD (off) 3 ― REXT = 250 Ω, OUT0 ~ 7 = off 6.5 10.7 15.0 IDD (on) 1 ― REXT = 470 Ω, OUT0 ~ 7 = on 7.0 12.0 18.0 IDD (on) 2 ― REXT = 250 Ω, OUT0 ~ 7 = on 10.0 22.0 32.0 5 mA % mA mA 2005-10-06 TB62705CPG/CFG/CFNG SWITCHING CHARACTERISTICS (Ta = 25°C unless otherwise stated) CHARACTERISTIC SYMBOL TEST CIR− CUIT CONDITION SIN− OUTn Propagation Delay Time (“L” to “H”) Propagation Delay Time (“H” to “L”) LATCH − OUTn Set−up Time for LATCH Hold Time for LATCH TYP. MAX ― 1200 1500 ― 1200 1500 ― 1200 1500 CLK−SOUT ― 30 70 SIN − OUTn ― 700 1000 ― 700 1000 ― 700 1000 ― 30 70 ― 20 30 ― 10 25 ― 25 50 ― 25 50 ― 0 30 ― 0 30 ― ― 10 ENABLE − OUTn LATCH − OUTn ENABLE − OUTn tpLH tpHL ― ― CLK−SOUT Pulse Width MIN CK tw CLK ― LATCH tw LAT ― tsetup ― thold ― tr ― L−H H−L L−H H−L Maximum CLOCK Rise Time VDD = 5.0 V VCE = 0.4 V VIH = VDD VIL = GND REXT = 470 Ω IOUT = 40 mA VL = 3.0 V RL = 65 Ω CL = 10.5 pF UNIT ns ns ns ns ns µs Maximum CLOCK Fall Time tf ― ― ― 10 µs Output Rise Time tor ― 300 600 1000 ns Output Fall Time tof ― 150 300 600 ns 6 2005-10-06 TB62705CPG/CFG/CFNG TEST CIRCUIT DC characteristics OUTn OUTn AC characteristics OUTn OUTn Precaution on Use Utmost care is necessary in the design of the output line, VCC (VDD) and GND line since the IC may be damaged due to short-circuits between outputs, air contamination faults, or faults caused by improper grounding. 7 2005-10-06 TB62705CPG/CFG/CFNG TIMING WAVEFORM 1. CLOCK−SERIAL OUT, OUTn OUTn (current) 2. CLOCK−LATCH 3. ENABLE − OUTn OUTn 8 2005-10-06 TB62705CPG/CFG/CFNG Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CPG) Iout-Duty Cycle(TB62705CPG) Iout-Duty Cycle(TB62705CPG) 9 2005-10-06 TB62705CPG/CFG/CFNG LED DRIVER TB6270X SERIES APPLICATION NOTE 1:CFG/CFNG ON PCB 2:CFG/CFNG FREE AIR 3:CPG FREE AIR 10 2005-10-06 TB62705CPG/CFG/CFNG [1] Output current (IOUT) IOUT is set by the external resistor (R−EXT), as shown in Fig. 1. [2] Total supply voltage (VLED) This device can operate on 0.4~0.7 V (VO). When a higher voltage is input to the device, the excess voltage is consumed inside the device, which leads to power dissipation. To minimize power dissipation and loss, we recommend that the total supply voltage be set as follows: VLED (total supply voltage) = VCE (Tr Vsat) + Vf (LED forward voltage) + VO (IC supply voltage). When the total supply is too high in the light of the power dissipation of this device, an additional resistor (R) can be used to decrease the supply voltage (VO). PATTERN LAYOUT OUTn OUTn OUTn OUTn [3] Pattern layout This device has only one ground pin, i.e., the combined signal ground pin and power ground pin. If the ground pattern layout contains a large amount of inductance and impedance, and the voltage between the ground and LATCH or CLOCK terminals exceeds 2.5 V due to switching noise, the device may not operate correctly. Be sure to pay attention to pattern layout to minimize inductance. 11 2005-10-06 TB62705CPG/CFG/CFNG PACKAGE DIMENSIONS Weight: 1.11 g (Typ.) 12 2005-10-06 TB62705CPG/CFG/CFNG PACKAGE DIMENSIONS Weight: 0.14 g (Typ.) 13 2005-10-06 TB62705CPG/CFG/CFNG PACKAGE DIMENSIONS Weight: 0.07 g (Typ.) 14 2005-10-06 TB62705CPG/CFG/CFNG 15 2005-10-06