TOSHIBA TMP90C041

TMP90C041
2. Pin Assignment and Functions
The assignment of input/output pins, their names and functions
are described below.
2.1 Pin Assignment
Figure 2.1 (1) shows pin assignment of the TMP90C041N.
Figure 2.1-(1). Pin Assignment
(Shrink Dual Inline Package)
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TMP90C041
Figure 2.1 (2) shows pin assignment of the TMP90C041F.
Figure 2.1 (2). Pin Assignment (Flat Package)
2.2 Pin Names and Functions
The names of input/output pins and their functions are summa-
rized in Table 2.2.
Table 2.2 Pin Names and Functions (1/2)
Pin Name
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No. of pins
I/O 3 states
D0 ~ D7
8
3 states
Data bus: Also functions as 8-bit bidirectional data bus for external memory
A0 ~ A7
8
Output
Address bus: The lower 8 bits address bus for external memory
A8 ~ A15
8
Output
P30
/RxD
1
Input
P31
/RxD
1
Input
Function
Address bus: The upper 8 bits address bus for external memory
Port 30: 1-bit input port
Receiver Serial Data
Port 31: 1-bit input port
Receiver Serial Data
Port 32: 1-bit input port
P32
/TxD
/RTS
/SCLK
1
P33
/TxD
1
Output
Transmitter Serial Data
Request to send Serial Data
Serial clock output
Output
Port 33: 1-bit output port
Transmitter Serial Data
Port 34: 1-bit input port
P34
/CTS
1
Input
RD
1
Output
Read: Generates strobe signal for reading external memory
WR
1
Output
Write: Generates strobe signal for writing into external memory
P37
/WAIT
1
Input
Clear to send Serial Data
Port 37: 1-bit input port
Wait: Input pin for connecting slow speed memory or peripheral LSI
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Table 2.2 Pin Names and Functions (2/2)
Pin Name
No. of Pins
I/O 3 states
P40 ~ P43
/A16 ~ A19
4
Output
P50 ~ P55
/AN0 ~ AN5
6
Input
VREF
1
–
AGND
1
P60 ~ P63
/M00 ~ M03
/TO1
P70 ~ P73
/M10 ~ M13
/TO3
Function
Port 4: 4-bit output port that allows selection of Port/Address Bus on bit basis
4
Port 5: 6-bit input port
Analog input: 6 analog input to A/D converter
Input of reference voltage to A/D converter
–
Ground pin for A/D converter
I/O
Port 6: 4-bit I/O port that allows I/O selection on bit basis
Output
Output
I/O
4
Address bus: Also functions as address bus for external memory
(4 bits of bank address)
Output
Output
Stepping motor control port 0
Timer output 1: Output of Timer 0 or 1
Port 7: 4-bit I/O port that allows I/O selection on bit basis
Stepping motor control port 1
Timer output 3: Output of Timer 2 or 3
Port 80: 1-bit input port
P80
/INTO
1
Input
Interrupt request pin 0: Interrupt request pin (Level/rising edge is
programmable)
Port 81: 1-bit input port
P81
/INT1
/TI4
1
Input
Interrupt request pin 1: Interrupt request pin (Rising/falling edge is
programmable)
Timer input 4: Counter/capture trigger signal for Timer 4
Port 82: 1-bit input port
P82
/INT2
/TI5
1
P83
/TO3/T04
1
Output
NMI
1
Input
CLK
1
Output
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is
Pulled up internally during resetting.
EA
1
Input
External access: Connects with GND pin in the TMP90C041 with no internal
ROM.
RESET
1
Input
Reset: Initializes the TMP90C041. (Built-in pull-up resistor)
X1/X2
2
Input/
Output
Pin for quartz crystal or ceramic resonator
VCC
1
–
Power supply (+5V)
VSS (GND)
1
–
Ground (0V)
Input
Interrupt request pin 2: rising edge interrupt request pin
Timer input 5: capture trigger signal for Timer 4
Port 83: 1-bit output port
Timer output 3/4: Output of Timer 2, 3 or 4
Non-maskable interrupt request pin: Falling edge interrupt request pin
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TMP90C041
3. Operation
The following explains the TMP90C041 functions and basic
operations.
The CPU functions and internal I/O functions of the
TMP90C041 are the same as the TMP90C840A.
Refer to the “TMP90C840A” section concerning functions
which are not explained in the following.
3.2 Memory Map
The TMP90C041 supports a program memory of up to 64K
bytes and a data memory of maximum 1M bytes.
The program memory may be assigned to the address
space from 00000H to 0FFFFH, while the data memory can
be allocated to any address from 00000H to FFFFFH.
(1)
3.1 CPU
The TMP90C041 has an internal high-performance 8-bit CPU.
Refer to the book TLCS Series CPU Core Architecture
concerning CPU operation.
Internal I/O
The TMP90C041 provides a 48-byte address space
as an internal I/O area, whose addresses range from
FFC0H to FFEFH. This I/O area can be accessed by
the CPU using a short opcode in the “direct addressing
mode”.
Figure 3.1 is a memory map indicating the areas
accessible by the CPU in the respective addressing
mode.
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TMP90C041
Figure 3.2. Memory Map
4. Electrical Characteristics
TMP90C041N/TMP90C041F
4.1 Absolute Maximum Ratings
Symbol
Parameter
VCC
Supply voltage
VIN
Input voltage
Unit
-0.5 ~ + 7
V
-0.5 ~ VCC + 0.5
V
F 500
Power dissipation (Ta = 70°C)
PD
Rating
mW
N 600
260
°C
TSTG
Storage temperature
-65 ~ 150
°C
TOPR
Operating temperature
-20 ~ 70
°C
TSOLDER
Soldering temperature (10s)
4.2 DC Characteristics
TA = -20 ~ 70°C VCC = 5V ± 10%
Typical Values are for TA = 25°C and VCC = 5V.
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIL
Input Low Voltage (D0 ~ D7)
-0.3
0.2VCC - 0.1
V
–
VIL1
P3, P5, P6, P7, P8
-0.3
0.3VCC
V
–
VIL2
RESET, INT0, NMI
-0.3
0.25VCC
V
–
VIL4
X1
-0.3
0.2VCC
V
–
VIH
Input Low Voltage (D0 ~ D7)
0.2VCC + 1.1
VCC + 0.3
V
–
VIH1
P3, P5, P6, P7, P8
0.7VCC
VCC + 0.3
V
–
VIH2
RESET, INT0, NMI
0.75VCC
VCC + 0.3
V
–
VIH4
X1
0.8VCC
VCC + 0.3
V
VOL
Output Low Voltage
–
0.45
V
IOL = 1.6mA
VOH
VOH1
VOH2
Output High Voltage
2.4
0.75VCC
0.9VCC
–
V
V
V
IOH = -400µA
IOH = -100µA
IOH = -20µA
IDAR
Darlington Drive Current
(8 I/O pins)
-1.0
-3.5
mA
VEXT = 1.5V
REXT = 1.1kΩ
–
ILI
Input Leakage Current
0.02 (Typ)
±5
µA
0.0 ≤ Vin ≤ VCC
ILO
Output Leakage Current
0.05 (Typ)
± 10
µA
0.2 ≤ Vin ≤ VCC - 0.2
20 (Typ)
1.5 (Typ)
9 (Typ)
40
5
15
mA
mA
mA
tosc = 12.5MHz
ICC
Operating Current (RUN)
Idle 1
Idle 2
0.2 (Typ)
50
10
µA
µA
0.2 ≤ Vin ≤ VCC - 0.2
STOP (TA = -20 ~ 70°C)
STOP (TA = 0 ~ 50°C)
RRST
RESET Pull Up Register
50
150
KΩ
CIO
Pin Capacitance
–
10
pF
VTH
Schmitt width RESET, NMI, INT0
0.4
1.0 (Typ)
V
–
testfreq = 1MHz
–
Note: IDAR is guaranteed for a total of up to 8 optional ports.
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TMP90C041
4.3 AC Characteristics
TA = -20 ~ 70°C VCC = 5V ± 10%
CL = 50pF
Variable
Symbol
tOSC
10MHz Clock
12.5MHz Clock
Parameter
OSC. Period = x
Unit
Min
Max
Min
Max
Min
Max
80
1000
100
-
80
–
ns
tCYC
CLK Period
4x
4x
400
–
320
–
ns
tWL
CLK Low width
2x - 40
–
160
–
120
–
ns
tWH
CLK High width
2x - 40
–
160
–
120
–
ns
tAC
Address Setup to RD, WR
x - 45
–
55
–
35
–
ns
tRR
RD Low width
2.5x - 40
–
210
–
160
–
ns
tCA
Address Hold Time After RD, WR
0.5x - 30
–
20
–
10
–
ns
tAD
Address to Valid Data In
-
3.5x - 95
–
255
–
185
ns
tRD
RD to Valid Data In
-
2.5x - 80
–
170
–
120
ns
tHR
Input Data Hold After RD
0
–
0
–
0
–
ns
tWW
WR Low width
tDW
Data Setup to WR
tWD
Data Hold After WR
tCWA
RD, WR to Valid WAIT
tAWA
2.5x - 40
–
210
–
160
–
ns
2x - 50
–
150
–
110
–
ns
30
90
30
90
30
90
ns
–
1.5x - 100
–
50
–
20
ns
Address to Valid WAIT
–
2.5x - 130
–
120
–
70
ns
tWAS
WAIT Setup to CLK
70
–
70
–
70
–
ns
tWAH
WAIT Hold After CLK
0
–
0
–
0
–
ns
tRV
RD/WR Recovery Time
1.5x - 35
–
115
–
85
–
ns
tCPW
CLK to Port Data Output
–
x + 200
–
300
–
280
ns
tPRC
Port Data Setup to CLK
200
–
200
–
200
–
ns
tCPR
Port Data Hold After CLK
100
–
100
–
100
–
ns
tCHCL
RD/WR Hold After CLK
tCLC
RD/WR Setup to CLK
x-60
–
40
–
20
–
ns
1.5x - 25
–
100
–
70
–
ns
tCLHA
Address Hold After CLK
1.5x - 80
tACL
Address Setup to CLK
2.5x - 80
–
70
–
40
–
ns
–
170
–
120
–
ns
tCLD
Data Setup to CLK
x - 50
–
50
–
30
–
ns
• AC output level High 2.2V/Low 0.8V
• AC input level High 2.4V/Low 0.45V (D0 – D7)
High 0.8VCC/Low 0.2VCC (excluding D0 – D7)
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TMP90C041
4.4 A/D Conversion Characteristics
TA = -20 ~ 70°C VCC = 5V ± 10%
Symbol
Parameter
Min
Typ
Max
VREF
Analog reference voltage
VCC - 1.5
VCC
VCC
AGND
Analog reference voltage
VSS
VSS
VSS
VAIN
Allowable analog input voltage
VSS
–
VCC
IREF
Supply current for analog reference voltage
–
0.5
1.0
Error
Total error
(TA = 25°C, VCC = VREF = 5.0V)
–
–
1.0
Total error
–
–
2.5
Unit
V
mA
LSB
4.5 Zero-Cross Characteristics
TA = -20 ~ 70°C VCC = 5V ± 10%
Symbol
Parameter
VZX
Zero-cross detection input
AZX
Zero-cross accuracy
FZX
Zero-cross detection input frequency
Condition
Min
Max
Unit
AC coupling C = 0.1µF
1
1.8
VAC p - p
50/60Hz sine wave
–
135
mV
–
0.04
1
kHz
4.6 Serial Channel Timing-I/O Interface Mode
TA = –20 ~ 70°C VCC = 5V ± 10%
CL = 50pF
Variable
Symbol
10MHz Clock
12.5MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
tSCY
Serial Port Clock Cycle Time
8x
–
800
–
640
–
ns
tOSS
Output Data Setup SCLK Rising Edge
6x - 150
–
450
–
330
–
ns
tOHS
Output Data Hold After SCLK Rising Edge
2x - 120
–
80
–
40
–
ns
tHSR
Input Data Hold After SCLK Rising Edge
0
–
0
–
0
–
ns
tSRD
SCLK Rising Edge to Input DATA Valid
–
6x - 150
–
450
–
330
ns
4.7 16-bit Event Counter
TA = –20 ~ 70°C VCC = 5V ± 10%
Variable
Symbol
10MHz Clock
12.5MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
tVCK
TI4 clock cycle
8x + 100
–
900
–
740
–
ns
tVCKL
TI4 Low clock pulse width
4x + 40
–
440
–
360
–
ns
tVCKH
TI4 High clock pulse width
4x + 40
–
440
–
360
–
ns
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TMP90C041
4.8 Interrupt Operation
TA = -20 ~ 70°C VCC = 5V ± 10%
Variable
Symbol
10MHz Clock
12.5MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
4x
–
400
–
320
–
ns
4x
–
400
–
320
–
ns
8x + 100
–
900
–
740
–
ns
8x + 100
–
900
–
740
–
ns
NMI, INT0 Low level pulse width
tINTAL
NMI, INT0 High level pulse width
tINTAH
INT1, INT2 Low level pulse width
tINTBL
INT1, INT2 High level pulse width
tINTBH
(Reference) Definition of IDAR
4.9 I/O Interface Mode Timing Chart
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4.10 Timing Chart
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TMP90C041
5. Differences Between TMP90C841A and
TMP90C041
Specifications of TMP90C841A and TMP90C041 are the
same except below.
TMP90C841A system, not using internal RAM and
Name
internal I/O functions as shown below, can be substituted by
TMP90C041 system. To substitute the TMP90C841A system
using the internal RAM by the TMP90C041 system, it is necessary to attach the external RAM to the address corresponded
to the internal address.
TMP90C841A
TMP90C041
RAM
256 bytes of internal RAM are provided. (0FEC0H ~ 0FFBFH)
External memory area.
A0 ~ A15
High-Impedance state during reset
Driving state during reset.
P0 (0FFC1H)
P1 (0FFC1H)
P2 (0FFC4H)
Provided
(same chip as TMP90C840A)
R/W function is not provided.
P01CR (0FFC2H)
Provided
EXT, P1C, P0C is not provided.
P2CR (0FFC5H)
Provided
P2XC register is not provided
* Note: Connect EA pin with GND pin.
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