TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91CY22IFG Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0 to 4, INTRTC) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91CY22I CMOS 16-Bit Microcontrollers TMP91CY22IFG 1. Outline and Features TMP91CY22I is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91CY22I comes in a 100-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) • Instruction mnemonics are upward-compatible with TLCS-90/900 • 16 Mbytes of linear address space • General-purpose registers and register banks • 16-bit multiplication and division instructions; bit transfer and arithmetic instructions • Micro DMA: 4-channels (593 ns/2 bytes at 27 MHz) (2) Minimum instruction execution time: 148 ns (at 27 MHz) (3) Built-in RAM: 16 Kbytes Built-in ROM: 256 Kbytes RESTRICTIONS ON PRODUCT USE 030619EBP • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 91CY22I-1 2005-06-21 TMP91CY22I (4) External memory expansion • Expandable up to 16 Mbytes (shared program/data area) • Can simultaneously support 8-/16-bit width external data bus … Dynamic data bus sizing (5) 8-bit timers: 8 channels (6) 16-bit timer/event counter: 2 channels (7) General-purpose serial interface: 2 channels UART/ Synchronous mode: 2 channels IrDA ver1.0 (115.2 kbps) supported (8) Serial bus interface: 1 channel • I2C bus mode/clock synchronous Select mode (9) 10-bit AD converter: 8 channels (10) Watchdog timer (11) Special timer for CLOCK (12) Chip Select/Wait controller: 4 channels (13) Interrupts: 45 interrupts • 9 CPU interrupts: Software interrupt instruction and illegal instruction • 26 internal interrupts: • 10 external interrupts: Seven selectable priority levels (14) Input/Output ports: 81 pins (15) Standby function Three HALT modes: IDLE2 (programmable), IDLE1, STOP (16) Triple-clock controller • Clock Doubler (DFM) • Clock Gear (fc to fc/16) • SLOW mode (fs = 32.768 kHz) (17) Operating voltage • VCC = 2.7 V to 3.6 V (fc max = 27 MHz) • VCC = 1.8 V to 3.6 V (fc max = 10 MHz) (18) Package • 100-pin QFP: P-LQFP100-1414-0.50F 91CY22I-2 2005-06-21 TMP91CY22I A D T R G (P 53 ) A N 0 to A N 7 (P 50 to P 57) AVCC, AVSS V RE FH, V RE FL T XD 0 (P 9 0) R XD 0 (P 9 1) 10 -B it 8C H AD C on ve rter S IO /U A R T /IrD A (S IO 0) S C LK 0/ C T S 0 (P 92 ) T XD 1 (P 93) R XD 1 (P 94) S C LK 1/ C T S 1 (P 95 ) XW A XB C XDE XHL XIX XIY XIZ XS P W B D H A C E L IX IY IZ SP 32 bits SR F PC S eria l B us In terfac e (S B I) T A 0 IN (P 70) 8-B it T im er (T M R A 0 ) S pec ial tim er for C LO C K T A 1O U T (P 71) 8-B it T im er (T M R A 1 ) 8-B it T im er (T M R A 2 ) 8-B it T im er (T M R A 3 ) T A 5O U T (P 74) 8-B it T im er (T M R A 5 ) 8 -B it Tim er (T M R A 6 ) T A 7O U T (P 75) L-O S C R ESET P ort 2 P ort 3 8-B it T im er (T M R A 7 ) (P 00 to P 0 7) A D 0 to A D 7 (P 10 to P 17 ) A D 8/A 8 to A D 15/A 15 (P 20 to P 27 ) A 0 /A 1 6 to A 7/A 23 R D (P 30) W R (P 31) H W R (P 32) B U S R Q (P 3 4) B U S A K (P 3 5) R / W (P 36) P37 P ort 6 (P 64 ) S C O U T , P 65, P 6 6 P o rt A P A 4 to P A 7 C o n tro lle r (4-B L O C K ) Inte rru pt C o n tro lle r 25 6-K B R O M EMU0 EMU1 XT 1 (P 9 6) XT 2 (P 9 7) AM0 AM1 ALE C S /W A IT 16 -K B R A M 8-B it T im er (T M R A 4 ) C lo c k G e a r C loc k d o u b le r P ort 1 S C K (P 6 0) S O /S D A (P 6 1) S I / S C L (P 6 2) T A 4 IN (P 73) H -O S C P ort 0 S IO /U A R T (S IO 1) W atc h dog T im e r (W D T ) T A 3O U T (P 72) D V C C [3] D V S S [3] X1 X2 C P U (T L C S -9 0 0 /L 1 ) 16 -B it T im er (T M R B 0 ) 16 -B it T im er (T M R B 1 ) ( (P 40 to P 43 ) C S 0 to W A IT CS3 (P 33) NMI IN T 0 (P 6 4) IN T 1 to 4 (P A 0 to 3 ) T B 0 IN 0 /IN T 5 (P 8 0) T B 0 IN 1 /IN T 6 (P 8 1) T B 0 O U T 0 (P 82) T B 0 O U T 1 (P 83) T B 1 IN 0 /IN T 7 (P 8 4) T B 1 IN 1 /IN T 8 (P 8 5) T B 1 O U T 0 (P 86) T B 1 O U T 1 (P 87) ): Initial func tion afte r re s et Figure 1.1 TMP91CY22I Block Diagram 91CY22I-3 2005-06-21 TMP91CY22I 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91CY22I, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91CY22I. 88 P65 DVCC 89 87 P64/SCOUT P66 90 86 P63/INT0 DVSS 91 85 P62/SI/SCL P50/AN0 92 84 P61/SO/SDA P51/AN1 93 83 P60/SCK P52/AN2 94 82 P43/CS3 P53/AN3/ADTRG 95 81 P42/CS2 P54/AN4 96 80 P41/CS1 P55/AN5 97 79 P40/CS0 P56/AN6 98 78 P37 P57/AN7 99 VREFH 100 77 P36/R/W 76 P35/BUSAK VREFL 1 75 P34/BUSRQ AVSS 2 74 P33/WAIT AVCC 3 73 P32/HWR P70/TA0IN 4 72 P31/WR P71/TA1OUT 5 71 P30/RD P72/TA3OUT 6 P73/TA4IN 7 70 P27/A7/A23 69 P26/A6/A22 P74/TA5OUT 8 68 P25/A5/A21 P75/TA7OUT 9 67 P24/A4/A20 P80/TB0IN0/INT5 10 P81/TB0IN1/INT6 11 66 P23/A3/A19 65 P22/A2/A18 P82/TB0OUT0 12 P83/TB0OUT1 13 P84/TB1IN0/INT7 14 P85/TB1IN1/INT8 15 P86/TB1OUT0 16 61 P21/A1/A17 60 P20/A0/A16 P87/TB1OUT1 17 59 P17/AD15/A15 P90/TXD0 18 58 P16/AD14/A14 P91/RXD0 19 57 P15/AD13/A13 P92/SCLK0/CTS0 20 56 P14/AD12/A12 P93/TXD1 21 55 P13/AD11/A11 P94/RX1 22 54 P12/AD10/A10 P95/SCLK1/CTS1 23 AM0 24 53 P11/AD9/A9 52 P10/AD8/A8 DVCC 25 51 P07/AD7 X2 26 50 P06/AD6 DVSS 27 49 P05/AD5 X1 28 48 P04/AD4 AM1 29 47 P03/AD3 RESET P96/XT1 30 31 46 P02/AD2 P97/XT2 32 44 P00/AD0 EMU0 33 43 ALE EMU1 34 PA0/INT1 35 42 PA7 41 PA6 PA1/INT2 36 40 PA5 PA2/INT3 37 39 PA4 LQFP100 64 DVCC 63 NMI Top View 62 DVSS 45 P01/AD1 38 PA3/INT4 Figure 2.1.1 Pin assignment diagram (100-pin LQFP) 91CY22I-4 2005-06-21 TMP91CY22I 2.2 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions. Table 2.2.1 Pin names and functions (1/4) Pin Name Number of Pins I/O Functions P00 to P07 AD0 to AD7 8 I/O Tri-state Port 0: I/O port that allows I/O to be selected at the bit level Address and data (lower): Bits 0 to 7 of address and data bus P10 to P17 AD8 to AD15 A8 to A15 8 I/O Tri-state Output Port 1: I/O port that allows I/O to be selected at the bit level Address and data (upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of address bus P20 to P27 8 I/O A0 to A7 A16 to A23 P30 Port 2: I/O port that allows I/O to be selected at the bit level Output Output Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus 1 Output Output Port 30: Output port Read: Strobe signal for reading external memory RD is outputted by setting P3 <P30> = 0 and P3FC < P30F> = 1, when reading 1 Output Output Port 31: Output port Write: Strobe signal for writing data to pins AD0 to AD7 1 I/O Output Port 32: I/O port (with pull-up resistor) High Write: Strobe signal for writing data to pins AD8 to AD15 1 I/O Input Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait ((1 + N) wait mode) 1 I/O Input Port 34: I/O port (with pull-up resistor) Bus Request: Signal used to request that set AD0∼15, A0∼23, RD , WR , HWR , 1 I/O Output Port 35: I/O port (with pull-up resistor) Bus Acknowledge: Signal used to acknowledge that AD0∼15, A0∼23, RD , WR , HWR , R / W , CS0 ∼ CS3 pins are set to High impedance by receiving BUSRQ . (For 1 I/O Output Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle. RD internal area. P31 WR P32 HWR P33 WAIT P34 BUSRQ R/W P35 BUSAK , CS0 ∼ CS3 pins to High impedance. (For external DMAC) external DMAC) P36 R/W P37 1 I/O P40 1 I/O Output Port 40: I/O port (with pull-up resistor) Chip Select 0: Outputs 0 when address is within specified address area 1 I/O Output Port 41: I/O port (with pull-up resistor) Chip Select 1: Outputs 0 if address is within specified address area 1 I/O Output Port 42: I/O port (with pull-up resistor) Chip Select 2: Outputs 0 if address is within specified address area 1 I/O Output Port 43: I/O port (with pull-up resistor) Chip Select 3: Outputs 0 if address is within specified address area CS0 P41 CS1 P42 CS2 P43 CS3 Port 37: I/O port (with pull-up resistor) 91CY22I-5 2005-06-21 TMP91CY22I Table 2.2.1 Pin names and functions (2/4) Pin Name P50 to P57 AN0 to AN7 Number of Pins 8 ADTRG P60 SCK P61 SO SDA P62 SI SCL 1 1 1 I/O Input Input Input I/O I/O I/O Output I/O Functions Port 5: Pin used to input port Analog input: Pin used to input to AD converter AD Trigger: Signal used to request start of AD converter (Shared with P53) Port 60: I/O port Serial bus interface clock in SIO Mode Port 61: I/O port Serial bus interface output data in SIO Mode Serial bus interface data in I2C bus Mode. (programmable open-drain) I/O Input I/O Port 62: I/O port Serial bus interface input data in SIO Mode Serial bus interface clock in I2C bus Mode. (programmable open-drain) Port 63: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge P63 INT0 1 I/O Input P64 SCOUT 1 I/O Output P65 1 I/O Port 65: I/O port P66 1 I/O Port 66: I/O port P70 TA0IN 1 I/O Input P71 TA1OUT 1 I/O Output Port 71: I/O port 8-bit timer 1 output:Timer A1 Output P72 TA3OUT 1 I/O Output Port 72: I/O port 8-bit timer 3 output: Timer A3 Output P73 TA4IN 1 I/O Input P74 TA5OUT 1 I/O Output Port 74: I/O port 8-bit timer 5 output:Timer A5 Output P75 TA7OUT 1 I/O Output Port 75: I/O port 8-bit timer 7 output:Timer A7 Output P80 TB0IN0 INT5 1 I/O Input Input Port 80: I/O port 16-bit timer 0 input0:Timer B0 count/capture trigger Input 0 Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge. P81 TB0IN1 INT6 1 I/O Input Input Port 81: I/O port 16-bit timer 0 input1: Timer B0 count/capture trigger Input 1 Interrupt Request Pin 6: Interrupt request on rising edge P82 TB0OUT0 1 I/O Output Port 82: I/O port 16-bit timer 0 output 0: Timer B0 Output 0 P83 TB0OUT1 1 I/O Output Port 83: I/O port 16-bit timer 0 output 1: Timer B0 Output 1 P84 TB1IN0 INT7 1 I/O Input Input Port 84: I/O port 16-bit timer 1 input0: Timer B1 count/capture trigger Input 0 Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge. P85 TB1IN1 INT8 1 I/O Input Input Port 85: I/O port 16-bit timer 1 input 1: Timer B1 count/capture trigger Input 1 Interrupt Request Pin 8: Interrupt request on rising edge P86 TB1OUT0 1 I/O Output Port 86: I/O port 16-bit timer 1 output 0: Timer B1 Output 0 P87 TB1OUT1 1 I/O Output Port 87: I/O port 16-bit timer 1 output 1: Timer B1 Output 1 Port 64: I/O port System Clock Output: Outputs fFPH or fs clock. Port 70: I/O port 8-bit timer 0 input: Timer A0 Input Port 73: I/O port 8-bit timer 4 input:Timer A4 Input 91CY22I-6 2005-06-21 TMP91CY22I Table 2.2.1 Pin names and functions (3/4) Pin Name Number of Pins I/O Functions P90 TXD0 1 I/O Output P91 RXD0 1 I/O Input P92 SCLK0 1 I/O Port 92: I/O port I/O Serial Clock I/O 0 Input CTS0 P93 1 TXD1 P94 Output 1 RXD1 P95 1 1 Port 91: I/O port Serial Receive Data 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 (programmable open-drain) Port 94: I/O port Serial Receive Data 1 I/O Port 95: I/O port I/O Serial Clock I/O 1 Input CTS1 XT1 I/O Input SCLK1 P96 I/O Port 90: I/O port Serial Send Data 0 (programmable open-drain) I/O Input Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port (open-drain output) Low-frequency oscillator connection pin 91CY22I-7 2005-06-21 TMP91CY22I Table 2.2.1 Pin names and functions (4/4) Pin Name P97 Number of Pins 1 XT2 I/O I/O Output PA0 to PA3 4 INT1 to INT4 I/O Input Functions Port 97: I/O port (open-drain output) Low-frequency oscillator connection pin Ports A0 to A3: I/O ports Interrupt Request Pins 1 to 4: Interrupt request pins with programmable rising edge / falling edge. PA4 to PA7 4 I/O ALE 1 Output Ports A4 to A7: I/O ports NMI 1 Input Non-Maskable Interrupt Request Pin: Interrupt request pin with programmable falling AM0 to AM1 2 Input Operation mode: Fixed to AM1 = “1”, AM0 = “1”. EMU0/EMU1 1 Output RESET 1 Input VREFH 1 Input Pin for reference voltage input to AD converter (H) VREFL 1 Input Pin for reference voltage input to AD converter (L) Address Latch Enable (Can be disabled to reduce noise.) edge or both edge. Set to Open pins Reset: initializes TMP91CY22. (with pull-up resistor) AVCC 1 Power supply pin for AD converter AVSS 1 Power GND pin for AD converter (0 V) X1/X2 2 DVCC 3 Power supply pins (All DVCC pins should be connected with the power supply pin.) DVSS 3 GND pins (0 V) (All DVSS pins should be connected with the GND (0V) pin.) Note: I/O High frequency oscillator connection pins An external DMA controller cannot access the device’s built-in memory or built-in I/O devices using the BUSRQ and BUSAK signal. 91CY22I-8 2005-06-21 TMP91CY22I 3. Operation This device is a version of expanding its internal mask ROM size to 256 Kbytes and RAM size to 16 Kbytes. The configuration and the functionality of this device are the same as those of the TMP91CW12A. For the functions of this device that are not described here, refer to the TMP91CW12A data sheet. 3.1 Memory Map Figure 3.1.1 is a memory map of the TMP91CY22I. 000000H Internal I/O (4 Kbytes) Direct area (n) 000100H 001000H 64 Kbyte area (nn) Internal RAM (16 Kbytes) 005000H 010000H External memory 16 Mbyte area (R) (−R) (R+) (R + R8/16) (R + d8/16) (nnn) FC0000H Internal ROM (256 Kbytes) FFFF00H FFFFFFH Vector Table (256 bytes) ( = Internal area) Figure 3.1.1 Memory Map 91CY22I-9 2005-06-21 TMP91CY22I 4. 4.1 Electrical Characteristics Maximum Ratings Parameter Symbol Rating Unit Power Supply Voltage Vcc −0.5 to 4.0 V Input Voltage VIN −0.5 to Vcc + 0.5 V Output Current IOL 2 Output Current IOH −2 mA Output Current (total) ΣIOL 80 mA Output Current (total) ΣIOH −80 mA Power Dissipation (Ta = 85°C) PD 600 mW Soldering Temperature (10 s) TSOLDER 260 °C Storage Temperature TSTG −65 to 150 °C Operating Temperature TOPR −40 to 85 °C Note: mA The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. Point of note about solderability of lead free products (attach “G” to package name) Test parameter Test condition Note Solderability (1) Pass: solderability rate until forming ≥ 95% Use of Sn-63Pb solder Bath Solder bath temperature =230°C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature =245°C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (use of lead free) 91CY22I-10 2005-06-21 TMP91CY22I 4.2 DC Characteristics (1/2) Parameter Power Supply Voltage (AVcc = DVcc) (AVss = DVss = 0 V) P00 to P17 (AD0 to 15) P20 to PA7 (except P63) Input Low Voltage RESET , NMI , P63 (INT0) AM0, 1 X1 VCC VIL VIL1 VIL2 VIL3 VIL4 P00 to P17 (AD0 to AD15) P20 to PA7 (except P63) RESET , NMI , P63 (INT0) Input High Voltage Symbol AM0, 1 X1 VIH VIH1 VIH2 VIH3 VIH4 Output Low Voltage VOL Output High Voltage VOH Note: Condition Min fc = 4 to 27 MHz fs = 30 to 2.7 fc = 2 to 10 MHz 34 kHz 1.8 Typ. (Note) Max Unit 3.6 V Vcc ≥ 2.7 V 0.6 Vcc < 2.7 V 0.2Vcc Vcc ≥ 2.7 V 0.3Vcc Vcc < 2.7 V 0.2Vcc Vcc ≥ 2.7 V −0.3 Vcc < 2.7 V Vcc ≥ 2.7 V 0.25Vcc 0.15Vcc 0.3 Vcc < 2.7 V 0.3 Vcc ≥ 2.7 V 0.2Vcc Vcc < 2.7 V 0.1Vcc Vcc ≥ 2.7 V 2.0 Vcc < 2.7 V 0.7Vcc Vcc ≥ 2.7 V 0.7Vcc Vcc < 2.7 V 0.8Vcc Vcc ≥ 2.7 V 0.75Vcc Vcc < 2.7 V 0.85Vcc Vcc ≥ 2.7 V Vcc − 0.3 Vcc < 2.7 V Vcc − 0.3 Vcc ≥ 2.7 V 0.8Vcc V Vcc + 0.3 Vcc < 2.7 V IOL = 1.6 mA Vcc ≥ 2.7 V 0.45 IOL = 0.4 mA Vcc < 2.7 V 0.15Vcc IOH = −400 µA Vcc ≥ 2.7 V 2.4 IOH = −200µA Vcc < 2.7 V 0.8Vcc 0.9Vcc V Typical values are for when Ta = 25°C and Vcc = 3.0 V unless otherwise noted. 91CY22I-11 2005-06-21 TMP91CY22I 4.2 DC Characteristics (2/2) Parameter Symbol Condition Min Typ. (Note 1) Max Input Leakage Current ILI 0.0 ≤ VIN ≤ Vcc 0.02 ±5 Output Leakage Current ILO 0.2 ≤ VIN ≤ Vcc − 0.2 0.05 ±10 Power Down Voltage (at STOP, RAM back-up) VSTOP V IL2 = 0.2 Vcc, V IH2 = 0.8 Vcc 1.8 RESET Pull-up Resistor RRST Vcc = 3 V ± 10% 100 400 Vcc = 2 V ± 10% 200 1000 Pin Capacitance Schmitt Width RESET , NMI , INT0 CIO VTH Programmable Pull-up Resistor RKH NORMAL (Note 2) Icc IDLE2 fc = 1 MHz 10 Vcc ≥ 2.7 V 0.4 1.0 Vcc < 2.7 V 0.3 0.8 Vcc = 3 V ± 10% 100 400 Vcc = 2 V ± 10% 200 1000 Vcc = 3 V ± 10% fc = 27 MHz IDLE1 NORMAL (Note 2) IDLE2 IDLE1 Vcc = 2 V ± 10 % fc = 10 MHz (Typ.: Vcc = 2.0 V) IDLE2 Vcc = 3 V ± 10 % fs = 32.768 kHz IDLE1 Ta ≤ 70°C SLOW (Note 2) Ta ≤ 85°C IDLE1 Vcc = 2 V ± 10 % fs = 32.768 KHz (Typ.: Vcc = 2.0 V) STOP Vcc = 1.8 to 3.3V SLOW (Note 2) IDLE2 3.6 Note 1: Typical values are for when Ta = 25°C and Vcc = 3.0 V unless otherwise noted. Note 2: Icc measurement conditions (NORMAL, SLOW): 10.0 µA V kΩ pF V kΩ 13.0 2.5 3.5 1.0 1.8 1.7 2.5 0.6 0.9 0.25 0.4 11.6 30 5.2 19 3.0 Unit 8 mA mA µA 15 7.7 20 3.5 13 2.0 10 0.1 10 µA µA All functions are operating; output pins are open and input pins are fixed. 91CY22I-12 2005-06-21 TMP91CY22I 4.3 AC Characteristics (1) Vcc = 3.0 V ± 10% No. Parameter Symbol Variable fFPH = 27 MHz Max Unit Min Max Min 37.0 31250 37.0 ns 1 fFPH Period ( = x) tFPH 2 A0 to A15 Vaild → ALE Fall tAL 0.5x − 14 4 ns 3 ALE Fall → A0 to A15 Hold tLA 0.5x − 16 2 ns 4 ALE High Width tLL x − 20 17 ns 5 ALE Fall → RD / WR Fall tLC 0.5x − 14 4 ns 6 RD Rise → ALE Rise tCLR 0.5x − 10 8 ns 7 WR Rise → ALE Rise tCLW x − 10 27 ns 8 A0 to A15 Valid → RD / WR Fall tACL x − 23 14 ns 9 A0 to A23 Valid → RD / WR Fall tACH 1.5x − 26 29 ns 10 RD Rise → A0 to A23 Hold tCAR 0.5x − 13 5 ns 11 WR Rise → A0 to A23 Hold tCAW x − 13 24 12 A0 to A15 Valid → D0 to D15 Input tADL 3.0x − 38 73 ns 13 A0 to A23 Valid → D0 to D15 Input tADH 3.5x − 41 88 ns 14 RD Fall → D0 to D15 Input tRD 44 ns 15 RD Low Width tRR 2.0x − 15 59 ns 16 RD Rise → D0 to A15 Hold tHR 0 0 ns 2.0x − 30 ns 17 RD Rise → A0 to A15 Output tRAE x − 15 22 ns 18 WR Low Width tWW 1.5x − 15 40 ns 19 D0 to D15 Valid → WR Rise tDW 1.5x − 35 20 ns 20 WR Rise → D0 to D15 Hold tWD x − 25 12 ns 1+n wait Mode 1+n wait Mode 1+n wait Mode tAWH 3.5x − 60 69 ns tAWL 3.0x − 50 61 ns 21 A0 to A23 Valid → WAIT Input 22 A0 to A15 Valid → WAIT Input 23 RD / WR Fall → WAIT Hold 24 A0 to A23 Valid → Port Input tAPH 25 A0 to A23 Valid → Port Hold tAPH2 26 A0 to A23 Valid → Port Valid tAP 2.0x + 0 tCW 74 3.5x − 89 3.5x ns 40 ns 209 ns 129 3.5x + 80 ns AC Measuring Conditions • Output Level: High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF • Input Level: High = 0.9 Vcc, Low = 0.1 Vcc Note: “x” used in an expression shows a frequency for the clock fFPH selected by SYSCR1<SYSCK>. The value of “x” changes according to whether a clock gear or a low-speed oscillator is selected. An example value is calculated for fc, with gear=1/fc (SYSCR1<SYSCK,GEAR2 to 0> = 0000). 91CY22I-13 2005-06-21 TMP91CY22I (2) Vcc = 2.0 V ± 10% No. Parameter Symbol Variable fFPH =10M Hz Min Max Min 100 31250 Max Unit 1 fFPH Period ( = x) tFPH 100 ns 2 A0 to A15 → ALE Fall tAL 0.5 x − 28 22 ns 3 ALE Fall → A0 to A15 Hold tLA 0.5 x − 35 15 ns 4 ALE High Width tLL x − 40 60 ns 5 ALE Fall → RD / WR Fall tLC 0.5x − 28 22 ns 6 RD Rise → ALE Rise tCLR 0.5x − 20 30 ns 7 WR Rise → ALE Rise tACW x − 20 80 ns 8 A0 to A15 Valid → RD / WR Fall tACL x − 75 25 ns 9 A0 to A23 Valid → RD / WR Fall TACH 1.5x −70 80 ns 10 RD Rise → A0 to A23 Hold tCAR 0.5x − 30 20 ns 11 WR Rise → A0 to A23 Hold TCAW x − 30 70 ns 12 A0 to A15 Valid → D0 to D15 Input tADL 13 A0 to A23 Valid → D0 to D15 Input 14 RD Fall → D0 to D15 Input 15 RD Low Width tRR 16 RD Rise → D0 to D15 Hold tHR 0 0 ns 17 RD Rise → A0 to A15 Output tRAE x − 30 70 ns 18 WR Low Width tWW 1.5 x − 30 120 ns 19 D0 to D15 Valid → WR Rise tDW 1.5 x − 70 80 ns 20 WR Rise →D0 to D15 Hold tWD x − 50 50 ns 21 A0 to A23 Valid → WAIT Input 22 A0 to A15 Valid → WAIT Input 1+n wait mode 1+n wait mode 23 RD / WR Fall → WAIT Hold 1+n wait mode 24 A0 to A23 Valid → Port Input tAPH 25 A0 to A23 Valid → Port Hold tAPH2 26 A0 to A23 Valid → Port Valid tAP 3.0x − 76 224 ns tADH 3.5x − 82 268 ns TRD 2.0x − 60 140 ns 2.0x − 30 170 3.5x − 120 tAWH 3.0x − 100 tAWL 2.0x + 0 tCW ns 230 ns 200 ns 180 ns 520 ns 200 3.5x − 170 3.5x ns 350 3.5x + 170 ns AC Measuring Conditions • Output Level: High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF • Input Level: High = 0.9 Vcc, Low = 0.1 Vcc Note: “x” used in an expression shows a frequency for the clock fFPH selected by SYSCR1<SYSCK>. The value of “x” changes according to whether a clock gear or a low-speed oscillator is selected. An example value is calculated for fc, with gear=1/fc (SYSCR1<SYSCK,GEAR2 to 0> = 0000). 91CY22I-14 2005-06-21 TMP91CY22I (3) Read Cycle tFPH fFPH A0 to A23 CS0 to CS3 R/W tAWH tAWL tCW WAIT tAP tAPH2 Port input (Note) tADH RD tACH tAC tLC AD0 to AD15 A0 to A15 tAL ALE Note: tCAR tRR tRD tADL tRAE tHR D0 to D15 tLA tCLR tLL Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91CY22I-15 2005-06-21 TMP91CY22I (4) Write Cycle fFPH A0 to A23 CS0 to CS3 R/W WAIT tAP Port Output (Note) tCAW WR, HWR tWW tDW AD0 to AD15 A0 to A15 tWD D0 to D15 tCLW ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91CY22I-16 2005-06-21 TMP91CY22I 4.4 AD Conversion Characteristics AVcc = Vcc, AVss = Vss parameter Symbol Analog Reference Voltage (+) VREFH Analog Reference Voltage (−) VREFL Condition Min (not including quantizing errors) − Max Vcc = 3 V ± 10% Vcc − 0.2 V Vcc Vcc Vcc = 2 V ± 10% Vcc Vcc Vcc Vcc = 3 V ± 10% Vss Vss Vss + 0.2 V Vss Vss Vcc = 2 V ± 10% Analog Input Voltage Range VAIN Analog Current for Analog Reference Vcc = 3 V ± 10% Voltage IREF <VREFON> = 1 Vcc = 2 V ± 10% (VREFL = 0V) Vcc = 1.8 V to 3.3 V <VREFON> = 0 Error Typ. VREFL Vss 0.94 1.20 0.65 0.90 mA 0.02 5.0 ± 1.0 ± 4.0 Vcc = 2 V ± 10% ± 1.0 ± 4.0 1 LSB = (VREFH − VREFL)/1024 [V] Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value for ICC includes the current which flows through the AVCC pin. 91CY22I-17 V VREFH Vcc = 3 V ± 10% Note 1: Unit µA LSB 2005-06-21 TMP91CY22I 4.5 Serial Channel Timing (I/O Internal Mode) (1) SCLK Input Mode Parameter Variable Symbol Min SCLK Period tSCY 10 MHz Max 16X tSCY/2 − 4x −110 Output Data → SCLK Rising tOSS /Falling Edge* (Vcc=3V±10%) → Output Data Hold SCLK Rising/Falling Edge* → Input Data Hold SCLK Rising/Falling Edge* 1.6 0.59 290 38 220 ⎯ Unit Max µs tSCY/2 + 2X + 0 1000 370 ns tHSR 3x+10 310 121 ns tSCY − 0 Valid Data Input t →SCLK Rising/Falling Edge* RDS *) SCLK Rinsing/Falling Edge: Min tOHS tSRD → Valid Data Input Max ns tSCY/2 − 4x −180 (Vcc=2V±10%) SCLK Rising/Falling Edge* Min 27 MHz 1600 0 0 592 0 ns ns The rising edge is used in SCLK Rising Mode. The falling edge is used in SCLK Falling Mode. Note: Value of 27 MHz and 10MHz at tSCY = 16X. (2) SCLK Output Mode Parameter SCLK Period Variable Symbol tSCY 10 MHz 27 MHz Min Max Min Max Min Max 16X 8192X 1.6 819 0.59 303 Unit µs Output Data tOSS → SCLK Rising/Falling Edge* tSCY/2 − 40 760 256 ns SCLK Rising/Falling Edge* tOHS tSCY/2 − 40 760 256 ns tHSR 0 0 0 ns → Output Data Hold SCLK Rising/Falling Edge* → Input Data Hold SCLK Rising Rising/Falling Edge* → Valid Data Input tSCY − 1X − 180 tSRD Valid Data Input tRDS → SCLK Rising/Falling Edge* 1X + 180 1320 375 280 217 ns ns tSCY SCLK Output Mode/ Input Mode SCLK (Input Mode) tOSS tOHS OUTPUT DATA TXD 0 INPUT DATA RXD 0 1 tSRD Valid 91CY22I-18 tRDS 1 Valid 2 3 tHSR 2 3 Valid Valid 2005-06-21 TMP91CY22I 4.6 Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1) Parameter Variable Symbol Min 4.7 10 MHz Max Min 27 MHz Max Min Unit Max Clock period tVCK 8X + 100 900 396 ns Clock Low level width tVCKL 4X + 40 440 188 ns Clock High level width tVCKH 4X + 40 440 188 ns 10 MHz 27 MHz Interrupt and Capture (1) NMI , INT0 to INT4 Interrupts Parameter Variable Symbol Min Max Min Max Min Unit Max NMI , INT0 to INT4 Low level width tINTAL 4X + 40 440 188 ns NMI , INT0 to INT4 High level width tINTAH 4X + 40 440 188 ns (2) INT5 to INT8 Interrupts, Capture The INT5 to INT8 input width depends on the system clock and prescaler clock settings. tINTBL tINTBH System Clock Prescaler Clock (INT5 to INT8 Low level Width) (INT5 to INT8 High Level Width) Unit Selected Selected Variable fFPH = 10 MHz Variable fFPH = 27 MHz <SYSCK> <PRCK1:0> 0 (fc) 1 (fs) Note: 4.8 Min Min Min 8X + 100 396 8X + 100 396 ns 10 (fc/16) 128Xc + 0.1 4.8 128Xc + 0.1 4.8 00 (fFPH) 8X + 0.1 244.3 8X + 0.1 244.3 µs Xc = Period of Clock fc SCOUT Pin AC Characteristics Parameter Low level width High level width Note: Min 00 (fFPH) Symbol tSCH tSCL Variable Min 10 MHz Max Min Max 27 MHz Min Max Condition Unit 0.5T − 13 37 5 Vcc ≥ 2.7 V 0.5T − 25 25 − Vcc < 2.7 V 0.5T − 13 37 5 Vcc ≥ 2.7 V 0.5T − 25 25 − Vcc < 2.7 V ns ns T = Period of SCOUT Measrement Condition • Output Level: High 0.7 Vcc/Low 0.3 Vcc, CL = 10pF tSCH tSCL SCOUT 91CY22I-19 2005-06-21 TMP91CY22I 4.9 Bus Request/Bus Acknowledge BUSRQ (Note 1) BUSAK tCBAL tBAA (Note 2) tABA AD0 to AD15 A0 to A23, RD , WR (Note 2) CS0 to CS3 , R / W HWR ALE Variable Paramter Symbol Min Output Buffer Off to BUSAK Low BUSAK High to Output Buffer On Note 1: tABA tBAA Max fFPH = 10 MHz Min Max fFPH = 27 MHz Min Condition Unit Max 0 80 0 80 0 80 Vcc ≥ 2.7 V 0 300 0 300 0 300 Vcc < 2.7 V 0 80 0 80 0 80 Vcc ≥ 2.7 V 0 300 0 300 0 300 Vcc < 2.7 V ns ns Even if the BUSRQ Signal goes Low, the bus will not be released while the WAIT signal is Low. The bus will only be released when BUSRQ goes Low while WAIT is High. Note 2: This line shows only that the output buffer is in the Off state. It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal. 91CY22I-20 2005-06-21 TMP91CY22I 4.10 Recommended Oscillation Circuit TMP91CY22I has been evaluated by murata manufacturing Co., Ltd. Please refer to murata manufacturing Co., Ltd. Note: Total loads value of oscillator is sum of external loads (C1 and C2) and floating loads of actual assemble board. There is a possibility of miss-operating. When designing board, it should design minimum length pattern around oscillator. And we recommend that oscillator evaluation try on your actual using board. (1) Examples of resonator connection X1 XT1 X2 XT2 Rd Rd C1 C2 C1 Figure 4.10.1 High-frequency Oscillator Connection C2 Figure 4.10.2 Low-frequency Oscillator Connection (2) Recommended ceramic resonators for TMP91CY22I: Murata Manufacturing Co., Ltd. Ta = −40 to 85°C Parameter of MCU Frequency [MHZ] 2.00 4.00 TMP91CY22I 6.00 10.00 Running Condition Elements Oscillation Item of Oscillator C1 C2 [pF] [pF] CSTCC2M00G56-R0 (47) (47) CSTCR4M00G55-R0 (39) (39) CSTLS4M00G56-B0 (47) (47) CSTCR6M75G55-R0 (39) (39) CSTLS6M75G56-B0 (47) (47) CSTLS10M0G53-B0 (15) (15) Rd [Ω] Voltage of Power [V] Tc[°C] 1.8 ∼ 2.2 0 2.7 ∼ 3.3 -20 ∼ +80 1.8 ∼ 2.2 • In CST*** type oscillator, capacitance C1, C2 is built-in. • The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL; http://www.murata.co.jp 91CY22I-21 2005-06-21 TMP91CY22I 5. Package Dimensions P-LQFP100-1414-0.50F Unit: mm 91CY22I-22 2005-06-21