TC74VHCT9273P/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT9273P,TC74VHCT9273FT,TC74VHCT9273FK Octal D-Type Flip Flop with Clear The TC74VHCT9273 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLR input is held “L”, the Q outputs are at a low logic level independent of the other inputs. The CLR input and CK input have hysteresis between the positive-going and negative-going thresholds. Thus the TC74VHCT9273 is capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity. It is easy to wire on the board because Input terminals are at the opposite side of Output terminals. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. TC74VHCT9273P TC74VHCT9273FT TC74VHCT9273FK Features • High speed: fmax = 185 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • Compatible with TTL inputs : VIL = 0.5 V (max) VIH = 2.1 V (min) • Weight DIP20-P-300-2.54A TSSOP20-P-0044-0.65A VSSOP20-P-0030-0.50 • Power down protection is provided on all inputs. Balanced propagation delays: tpLH ∼ − tpHL • Function compatible with 74VHC273 • Input terminals are at the opposite side of Output terminals 1 : 1.30 g ( typ.) : 0.08 g ( typ.) : 0.03 g ( typ.) 2009-07-01 TC74VHCT9273P/FT/FK Pin Assignment CLR IEC Logic Symbol 1 20 VCC D1 2 19 Q1 D2 3 18 Q2 D3 4 17 Q3 D4 5 16 Q4 D5 6 15 Q5 D6 7 14 Q6 D7 8 13 Q7 D8 9 12 Q8 GND 10 11 CK CLR CK D1 D2 D3 D4 D5 D6 D7 D8 (1) (11) R C1 (2) (3) (4) (5) (6) (7) 1D (19) (18) (17) (16) (15) (14) (8) (9) Q1 Q2 Q3 Q4 Q5 Q6 (13) (12) Q7 Q8 (top view) Truth Table Inputs Output Function CLR D CK Q L X X L Clear H L L ― H H H ― H X Qn No Change X: Don’t care System Diagram CLR 1 D1 2 D2 3 D R CK CK D3 4 D R Q CK D R Q D5 D4 5 CK D R Q D6 6 CK D R Q D7 CK D R Q D8 8 7 CK 9 D R Q CK D R Q CK Q 11 19 Q1 18 Q2 17 16 Q4 Q3 2 15 Q5 13 14 Q6 12 Q7 Q8 2009-07-01 TC74VHCT9273P/FT/FK Absolute Maximum Ratings (Note1) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7.0 V DC input voltage VIN −0.5 to 7.0 V VOUT −0.5 to VCC + 0.5 V Input diode current IIK −20 mA Output diode current IOK ±20 mA DC output current IOUT ±25 mA DC VCC/ground current ICC ±75 mA Power dissipation PD 500 (DIP) (Note 2)/180(TSSOP/VSSOP) mW Storage temperature Tstg −65 to 150 °C DC output voltage Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be applied until 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 4.5 to 5.5 V Input voltage VIN 0 to 5.5 V VOUT 0 to VCC V Topr −40 to 85 °C Output voltage Operating temperature Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 3 2009-07-01 TC74VHCT9273P/FT/FK Electrical Characteristics DC Characteristics Test Condition Characteristics High-level input voltage VIH Low-level input voltage Hysteresis voltage (CK、 CLR ) High-level output voltage Max Min Max 4.5 ― ― 1.90 ― 1.90 5.5 ― ― 2.10 ― 2.10 4.5 0.50 ― ― 0.50 ― 5.5 0.60 ― ― 0.60 ― 4.5 0.40 ― 1.40 0.40 1.40 5.5 0.40 ― 1.50 0.40 1.50 IOH = −50 μA 4.5 4.4 4.5 ― 4.4 ― IOH = −8 mA 4.5 3.94 ― ― 3.80 ― IOL = 50 μA 4.5 ― 0.0 0.1 ― 0.1 IOL = 8 mA 4.5 ― ― 0.36 ― 0.44 VH ― VOL Input leakage current Typ. ― VIN = VIH Unit Min VIL VIN = VIL Ta = −40 to 85°C VCC (V) ― VOH Low-level output voltage Quiescent supply current Ta = 25°C Symbol V V V IIN VIN = 5.5 V or GND 0~ 5.5 ― ― ±0.1 ― ±1.0 μA ICC VIN = VCC or GND 5.5 ― ― 2.0 ― 20.0 μA 5.5 ― ― 1.35 ― 1.50 mA Ta = 25°C Ta = −40 to 85°C ICCT Per input: VIN = 3.4 V Other input: VCC or GND Timing Requirements (input: tr = tf = 3 ns) Characteristics Test Condition Symbol Unit VCC (V) Typ. Limit Limit ― 5.0 ± 0.5 ― 5.0 5.0 ns tw (L) ― 5.0 ± 0.5 ― 5.0 5.0 ns Minimum set-up time ts ― 5.0 ± 0.5 ― 4.5 4.5 ns Minimum hold time th ― 5.0 ± 0.5 ― 1.0 1.0 ns trem ― 5.0 ± 0.5 ― 2.0 2.0 ns Minimum pulse width (CK) Minimum pulse width ( CLR ) Minimum removal time ( CLR ) tw (L) tw (H) 4 2009-07-01 TC74VHCT9273P/FT/FK AC Characteristics (input: tr = tf = 3 ns) Characteristics Test Condition Symbol VCC (V) Propagation delay time (CK-Q) tpLH tpHL ― 5.0 ± 0.5 Propagation delay time ( CLR -Q) tpHL ― 5.0 ± 0.5 Maximum clock frequency fmax ― 5.0 ± 0.5 (Note 1) 5.0 ± 0.5 Output to output skew tosLH tosHL Input capacitance CIN Power dissipation capacitance CPD Ta = −40 to 85°C Ta = 25°C Unit CL (pF) Min Typ. Max Min Max 15 ― 4.7 8.9 1.0 10.2 50 ― 7.6 14.1 1.0 16.1 15 ― 7.5 14.4 1.0 16.4 50 ― 10.4 19.6 1.0 22.3 15 110 185 ― 95 ― 50 70 100 ― 60 ― 50 ― ― 1.0 ― 1.0 ns ― 4 10 ― 10 pF ― 13 ― ― ― pF ― (Note 2) ns ns MHz Note 1: Parameter guaranteed by design. tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn| Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN + ICC/8 (per bit) And the total CPD when n pcs.of flip flop operate can be gained by the following equation: CPD (total) = 9 + 4·n 5 2009-07-01 TC74VHCT9273P/FT/FK Package Dimensions Weight: 1.30 g (typ.) 6 2009-07-01 TC74VHCT9273P/FT/FK Package Dimensions Weight: 0.08 g (typ.) 7 2009-07-01 TC74VHCT9273P/FT/FK Package Dimensions Weight: 0.03 g (typ.) 8 2009-07-01 TC74VHCT9273P/FT/FK RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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