T6C25 TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6C25 COLUMN AND ROW DRIVER FOR A DOT MATRIX LCD The T6C25 is a 160-channel-output column and row driver for an STN dot matrix LCD. The T6C25 features a 42-V LCD drive voltage and an 8-MHz maximum operating frequency. The T6C25 is able to drive LCD panels with a duty ratio of up to 1 / 480. FEATURES l Display duty application : to 1 / 480 l LCD drive signal : 160 l Data transfer : Column : 4 / 8-bit bidirectional Row : Single / Dual bidirectional l Operating frequency : 8 MHz l LCD drive voltage : 14 to 42 V l Power supply voltage : 2.7 to 5.5 V l Operating temperature : −20 to 75°C l LCD drive output resistance : 1.3 kΩ (max) (20 V, 1 / 13 bias) l Display-off function : When / DSPOF is L, all LCD drive outputs (O1 to O160) remain at the V5 level. l Low power consumption : Cascade connection and auto enable transfer functions are available. l EI / LP input : EI / LP Input enables LSI operation. Connect EIO 1 / 2 from the 1st LSI to L. 000707EBE1 · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 2000-12-05 1/11 T6C25 BLOCK DIAGRAM 2000-12-05 2/11 T6C25 PIN ASSIGNMENT * : The above diagram shows the pin configuration of the LSI Chip, not that of the tape carrier package. 2000-12-05 3/11 T6C25 PIN FUNCTIONS PIN NAME I/O O1 to O160 Output EIO1, EIO4 I/O FUNCTIONS Output for LCD drive signal (Column mode) Input for data signal Input DIR Input (Direction) Input for data flow direction select, / DSPOF Input (Display Off) / DSPOF = L : Display-off mode, (O1 to O160) remain at the V5 level. / DSPOF = H : Display-on mode, (O1 to O160) are operational. DUAL Input Input V0 to V5 Input / output for enable signal DIR selects In or Out. Connect EIO (IN) of 1st LSI to L. For a cascade connection, connect EIO (OUT) to EIO (IN) of next LSI. DI1 to DI8 DF LEVEL (Row mode) Fix to H or L (Column mode) Input for data bit select (Row mode) Fix to H or L (Column mode) Fix to H or L VDD to VSS (Row mode) Input for dual / single select (Column mode) Display data is latched on falling edges of LP. LP ― When EIO (IN) = L, setting SCP ·LP = H enables the 1st LSI. (Row mode) Input for shift clock pulse FR Input (Frame) Input for frame signal (Column mode) Input for shift clock pulse SCP Input TEST Input (TEST) Fix to L S/C Input Input for mode select : H = Column mode, L = Row mode VDD ― Power supply for internal logic (+5.0 V) VSS ― Power supply for internal logic (0 V) V5L·R ― Power supply for LCD drive circuit V3 / 4L·R ― Power supply for LCD drive circuit V2 / 1L·R ― Power supply for LCD drive circuit V0L·R ― Power supply for LCD drive circuit VCCL·R ― Power supply for LCD drive circuit (Row mode) Fix to H or L ― 2000-12-05 4/11 T6C25 RELATION BETWEEN FR, DATA INPUT AND OUTPUT LEVEL FR DATA INPUT (DI1 to DI8) / DSPOF OUTPUT LEVEL (CULUMN MODE) OUTPUT LEVEL (ROW MODE) L L H V3 V4 L H H V5 V0 H L H V2 V1 H H H V0 V5 * * L V5 V5 *: Don’t Care DATA INPUT FORMAT Column mode DIR DF BIT MODE H ENABLE PIN EIO1 EIO2 OUT L 4-BIT L IN H H OUT OUT IN IN OUT 8-BIT L *1 : IN (*1) DI1 INPUT DATA LINE AND OUTPUT BUFFERS DI2 DI3 DI4 DI5 DI6 DI7 DI8 O157 ― ― ― ― O2 O1 ― ― ― ― O3 O4 ― ― ― ― L O160 O159 O158 F O4 O3 L O1 O2 F O157 O158 O159 O160 ― ― ― ― L O160 O159 O158 O157 O156 O155 O154 O153 F O8 O7 O6 O5 O4 O3 O2 O1 L O1 O2 O3 O4 O5 O6 O7 O8 F O153 O154 O155 O156 O157 O158 O159 O160 L: Last Data F: First Data Row Mode DATA INPUT TERMINALS EIO2 EIO3 DUAL DIR DATA FLOW L L O160 → O1 OUT ― ― IN L H O1 → O160 IN ― ― OUT H L O160 → O81 O80 → O1 OUT IN OUT IN H H O1 → O80 O81 → O160 IN OUT IN OUT EIO1 DIN 2000-12-05 5/11 TIMING DIAGRAM (Column mode) 6/11 T6C25 2000-12-05 T6C25 TIMING DIAGRAM (Row mode) 2000-12-05 7/11 T6C25 ABSOLUTE MAXIMUM RATINGS (Ensure that the following conditions are maintained, VCC≥V0≥V2≥V3≥V5≥VSS) ITEM SYMBOL PIN NAME RATING UNIT Supply Voltage (1) VDD VDD −0.3 to 7.0 V Supply Voltage (2) VCC VCCL / R − 0.3 to 45.0 V Supply Voltage (3) V0, V2 V0L / R, V2L / R −0.3 to VCC + 0.3 V Supply Voltage (4) V3, V5 V3L / R, V5L / R −0.3 to 7.0 V Input Voltage VIN (*2) −0.3 to VDD + 0.3 V Operating Temperature Topr ― − 20 to 75 °C Storage Temperature Tstg ― − 40 to 125 °C *2 : SCP, FR, LP, DIR, DF, DUAL, S / C, EIO1 to 4, DI1 to 8, / DSPOF, TEST ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (Unless otherwise noted, VSS = 0V, VDD = 2.7 to 5.5V, Ta = −20 to 75°C) SYMBOL TEST CIRCUIT TEST CONDITION MIN TYP. MAX Supply Voltage 1 VDD ― ― 2.7 5.0 5.5 VDD Supply Voltage 2 VCC ― ― 14 ― 42 VCCL / R H Level VIH ― 0.8 VDD ― VDD L Level VIL ― 0 ― 0.2 VDD H Level VOH ― IOH = −0.4 mA VDD −0.5 ― VDD L Level VOL ― IOL = 0.4 mA 0 ― 1.3 H Level ROH ― VOUT = V0 − 0.5 V (*3) ― 0.6 1.3 M Level ROM ― VOUT = V2 ± 0.5 V (*3) ― 0.6 1.3 ― VOUT = V3 ± 0.5 V (*3) ― 0.6 1.3 L Level ROL ― VOUT = V5 + 0.5 V (*3) ― 0.6 1.3 ― VDD = 5.5 V VCC = 42 V fFR = 40 Hz fscp = 8.0 MHz Input Data : every bit inverted VIH = 5.5 V, VIL = 0 V ― ― 3.0 ITEM Input Voltage Output Voltage Output Resistance Current Consumption (*4) IDD (*2) UNIT V PIN NAME SCP, FR, LP, DIR, DF, DUAL S / C, EIO1 to 4, DI1 to 8, / DSPOF, TEST, EIO1, to 4 kΩ O1 to O160 mA VDD *3 : VCC = 20 V, 1 / 13 bias *4 : Current consumption while the internal data receiver is operating. 2000-12-05 8/11 T6C25 AC ELECTRICAL CHARACTERISTICS (Column Mode) TEST CONDITIONS (1) (VSS = 0 V, VDD = 4.5 to 5.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C) ITEM SYMBOL TEST CONDITION MIN MAX UNIT tC ― 125 ― ns tCWH, tCWL ― 50 ― ns Data Set-up Time tDSU ― 50 ― ns Data Hold Time tDHD ― 50 ― ns SCP Rise / Fall Time tr, tf ― ― (*5) ns LP Rise Time tLRP ― 50 ― ns LP Fall Time tLFP ― 50 ― ns LP Pulse Width tLW ― 45 ― ns SCP-to-LP Delay Time tSL ― 40 ― ns LP-to-SCP Delay Time tLS ― 40 ― ns EIO-In Fall Time tEIFP ― 40 ― ns EIO-In Pulse Width tEIW ― 40 ― ns SCP-to-EIO Delay Time tSE ― 20 ― ns tEOD (*6) ― 80 ns Clock Cycle SCP Pulse Width EIO-Out Delay Time *5 : tr, tf≤ (tC − tCWH − tCWL) / 2 and tr, tf≤50 ns *6 : CL = 30 pF 2000-12-05 9/11 T6C25 TEST CONDITIONS (2) (VSS = 0 V, VDD = 2.7 to 4.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C) ITEM SYMBOL TEST CONDITION MIN MAX UNIT tC ― 500 ― ns SCP Pulse Width tCWH, tCWL ― 240 ― ns Data Set-up Time tDSU ― 240 ― ns Data Hold Time tDHD ― 240 ― ns SCP Rise / Fall Time tr, tf ― ― (*5) ns LP Rise Time tLRP ― 240 ― ns LP Fall Time tLFP ― 240 ― ns LP Pulse Width tLW ― 240 ― ns SCP-to-LP Delay Time tSL ― 50 ― ns Clock Cycle LP-to-SCP Delay Time tLS ― 100 ― ns EIO-In Fall Time tEIFP ― 240 ― ns EIO-In Pulse Width tEIW ― 240 ― ns SCP-to-EIO Delay Time tSE ― 50 ― ns tEOD (*6) ― 260 ns EIO-Out Delay Time *5 : tr, tf≤ (tC − tCWH − tCWL) / 2 and tr, tf≤50 ns *6 : CL = 30 pF 2000-12-05 10/11 T6C25 AC ELECTRICAL CHARACTERISTICS (Row mode) TEST CONDITIONS (1) (VSS = 0 V, VDD = 4.5 to 5.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C) ITEM SYMBOL TEST CONDITION MIN MAX UNIT LP Pulse Width H tCWH LP 30 ― ns LP Pulse Width L tCWL LP 195 ― ns SCP Rise / Fall Time tr , tf LP, FR, EIO1 to 4 ― 20 ns Data Set-up Time tDSU EIO1 to 4 80 ― ns Data Hold Time tDHD EIO1 to 4 0 ― ns EIO-Out Delay Time A (*7) tpdA EIO1 to 4 5 ― ns EIO-Out Delay Time B (*7) tpdB EIO1 to 4 ― 150 ns TEST CONDITIONS (2) (VSS = 0 V, VDD = 2.7 to 5.5 V, VCC = 14 to 42 V, Ta = −20 to 75°C) ITEM SYMBOL TEST CONDITION MIN MAX UNIT LP Pulse Width H tCWH LP 100 ― ns LP Pulse Width L tCWL LP 400 ― ns SCP Rise / Fall Time tr , tf LP, FR, EIO1 to 4 ― 20 ns Data Set-up Time tDSU EIO1 to 4 130 ― ns Data Hold Time tDHD EIO1 to 4 0 ― ns EIO-Out Delay Time A (*7) tpdA EIO1 to 4 5 ― ns EIO-Out Delay Time B (*7) tpdB EIO1 to 4 ― 400 ns *7 : CL = 30 pF Note : Insert the bypass capacitor (0.1µF) between VDD and VSS to decrease power supply noise. Place the bypass capacitor as close to the LSI as possible. 2000-12-05 11/11