TC74HC652AP TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC652AP Octal Bus Transceiver/Register (3-state) The TC74HC652A is high speed CMOS OCTAL BUS TRANSCEIVER/REGISTER fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device is bus transceiver with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the internal registers. When the enable input GAB and GBA are held high, the A1 thru A8 become inputs and the B1 thru B8 become outputs. When Weight : 1.50 g (typ.) the GAB and GBA are held low, the A1 thru A8 become output and the B1 thru B8 become inputs. When GAB is low and GBA is high, the outputs functions of the A and B Busses are disabled. The select inputs (SAB, SBA) can multiplex sort and real-time (transparent mode) data. Data on the A Bus or B Bus can be clocked into the registers on the positive going transition of either CAB or CBA clock inputs, respectively. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features (Note 1) (Note 2) • High speed: fmax = 73 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 15 LSTTL loads • • Symmetrical output impedance: |IOH| = IOL = 6 mA (min) ∼ tpHL Balanced propagation delays: tpLH − • Wide operating voltage range: VCC (opr) = 2 to 6 V • Pin and function compatible with 74LS652 Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result. Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull down resistors. 1 2007-10-01 TC74HC652AP Pin Assignment IEC Logic Symbol 2 2007-10-01 TC74HC652AP Truth Table GAB L GBA H CAB CBA X X (Note) (Note) X X (Note) (Note) X L L (Note) X X (Note) (Note) X (Note) X X (Note) (Note) X H (Note) H X X (Note) (Note) X (Note) H L X X (Note) (Note) SAB SBA X X X X X L X L X H X H L X L X H X H X H H A B Inputs Inputs Z Z X X Outputs Inputs L L H H L L H H Qn X L L H H Inputs Outputs L L H H L L H H X Qn L L H H Outputs Outputs Qn Qn Function The output functions of A and B busses are disabled. Both A and B busses are used as inputs to the internal flip-flops. Data on the Bus will be stored on the rising edge of the clock. The data on the B bus are displayed on the A bus. The data on the B bus are displayed on the A bus, and are stored into the B storage flip-flops on the rising edge of CBA. The data in the B storage flip-flops are displayed on the A bus. The data on the B bus are stored into the B storage flip-flops on the rising edge of CBA, and the stored data propagate directly onto the A bus. The data on the A bus are displayed on the B bus. The data on the A bus are displayed on the B bus, and are stored into the A storage flip-flops on the rising edge of CAB. The data in the A storage flip-flops are displayed on the B bus. The data on the A bus are stored into the A storage flip-flops on the rising edge of CAB, and the stored data propagate directly onto the B bus. The data in the A storage flip-flops are displayed on the B bus, and the data in the B storage flip-flops are displayed onthe A. X: Don’t care Qn: The data stored into the internal flip-flops by most recent low to high transition of the clock inputs. Z: High impedance Note: The clocks are not internally gated with either output enable or select inputs. Therefore, data on the A and/or B busses may be clocked into the storage flip-flops at any time. 3 2007-10-01 TC74HC652AP Timing Chart System Diagram 4 2007-10-01 TC74HC652AP Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7 V DC input voltage VIN −0.5 to VCC + 0.5 V VOUT −0.5 to VCC + 0.5 V Input diode current IIK ±20 mA Output diode current IOK ±20 mA DC output current IOUT ±35 mA DC VCC/ground current ICC ±75 mA Power dissipation PD 500 Storage temperature Tstg −65 to 150 DC output voltage (Note 2) mW °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be applied until 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2 to 6 V Input voltage VIN 0 to VCC V VOUT 0 to VCC V Operating temperature Topr −40 to 85 °C Input rise and fall time tr, tf Output voltage 0 to 1000 (VCC = 2.0 V) 0 to 500 (VCC = 4.5 V) ns 0 to 400 (VCC = 6.0 V) Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 5 2007-10-01 TC74HC652AP Electrical Characteristics DC Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Symbol VOH VOL Min Typ. Max Min Max 2.0 1.50 ⎯ ⎯ 1.50 ⎯ 4.5 3.15 ⎯ ⎯ 3.15 ⎯ 6.0 4.20 ⎯ ⎯ 4.20 ⎯ 2.0 ⎯ ⎯ 0.50 ⎯ 0.50 4.5 ⎯ ⎯ 1.35 ⎯ 1.35 6.0 ⎯ ⎯ 1.80 ⎯ 1.80 2.0 1.9 2.0 ⎯ 1.9 ⎯ 4.5 4.4 4.5 ⎯ 4.4 ⎯ 6.0 5.9 6.0 ⎯ 5.9 ⎯ IOH = −6 mA 4.5 4.18 4.31 ⎯ 4.13 ⎯ IOH = −7.8 mA 6.0 5.68 5.80 ⎯ 5.63 ⎯ 2.0 ⎯ 0.0 0.1 ⎯ 0.1 4.5 ⎯ 0.0 0.1 ⎯ 0.1 6.0 ⎯ 0.0 0.1 ⎯ 0.1 IOL = 6 mA 4.5 ⎯ 0.17 0.26 ⎯ 0.33 IOL = 7.8 mA 6.0 ⎯ 0.18 0.26 ⎯ 0.33 6.0 ⎯ ⎯ ±0.5 ⎯ ±5.0 μA ⎯ VIL VIN = VIH or VIL VIN = VIH or VIL Unit VCC (V) ⎯ VIH Ta = −40 to 85°C Ta = 25°C Test Condition Characteristics IOH = −20 μA IOL = 20 μA VIN = VIH or VIL V V V V 3-state output off-state current IOZ Input leakage current IIN VIN = VCC or GND 6.0 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 6.0 ⎯ ⎯ 4.0 ⎯ 40.0 μA Ta = −40 to 85°C Unit VOUT = VCC or GND Timing Requirements (input: tr = tf = 6 ns) Characteristics Symbol Minimum pulse width tW (L) (CK) tW (H) Minimum set-up time Minimum hold time Clock frequency Ta = 25°C Test Condition ⎯ ⎯ ts ⎯ th ⎯ f 6 VCC (V) Typ. Limit Limit 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 50 65 4.5 ⎯ 10 13 6.0 ⎯ 9 11 2.0 ⎯ 5 5 4.5 ⎯ 5 5 6.0 ⎯ 5 5 2.0 ⎯ 6 5 4.5 ⎯ 31 25 6.0 ⎯ 36 29 ns ns ns MHz 2007-10-01 TC74HC652AP AC Characteristics (input: tr = tf = 6 ns) Output transition time Symbol CL (pF) tTLH ⎯ tTHL 50 50 Propagation delay time tpLH (BUS-bus) tpHL ⎯ 150 50 Propagation delay time tpLH (CAB, CBA-bus) tpHL ⎯ 150 50 Propagation delay time tpLH (SAB, SBA-bus) tpHL ⎯ 150 50 Propagation enable time tpZL (GAB, GBA -bus) tpZH RL = 1 kΩ 150 Output disable time tpLZ (GAB, GBA -bus) tpHZ RL = 1 kΩ Ta = −40 to 85°C Ta = 25°C Test Condition Characteristics 50 VCC (V) Min Typ. Max Min Max 2.0 ⎯ 25 60 ⎯ 75 4.5 ⎯ 7 12 ⎯ 15 6.0 ⎯ 6 10 ⎯ 13 2.0 ⎯ 74 150 ⎯ 190 4.5 ⎯ 21 30 ⎯ 38 6.0 ⎯ 18 26 ⎯ 32 2.0 ⎯ 91 190 ⎯ 240 4.5 ⎯ 26 38 ⎯ 48 6.0 ⎯ 22 32 ⎯ 41 2.0 ⎯ 98 210 ⎯ 265 4.5 ⎯ 28 42 ⎯ 53 6.0 ⎯ 24 36 ⎯ 45 2.0 ⎯ 116 250 ⎯ 315 4.5 ⎯ 33 50 ⎯ 63 6.0 ⎯ 28 43 ⎯ 54 2.0 ⎯ 81 170 ⎯ 215 4.5 ⎯ 23 34 ⎯ 43 6.0 ⎯ 20 29 ⎯ 37 2.0 ⎯ 98 210 ⎯ 265 4.5 ⎯ 28 42 ⎯ 53 6.0 ⎯ 24 36 ⎯ 45 2.0 ⎯ 74 175 ⎯ 220 4.5 ⎯ 21 35 ⎯ 44 6.0 ⎯ 18 30 ⎯ 37 2.0 ⎯ 91 215 ⎯ 270 4.5 ⎯ 26 43 ⎯ 54 6.0 ⎯ 22 37 ⎯ 46 2.0 ⎯ 50 175 ⎯ 220 4.5 ⎯ 21 35 ⎯ 44 6.0 ⎯ 18 30 ⎯ 37 2.0 6 19 ⎯ 5 ⎯ 4.5 31 67 ⎯ 25 ⎯ 6.0 Unit ns ns ns ns ns ns Maximum clock frequency fmax 36 79 ⎯ 29 ⎯ Input capacitance CIN ⎯ ⎯ 5 10 ⎯ 10 pF COUT ⎯ ⎯ 13 ⎯ ⎯ ⎯ pF ⎯ ⎯ 39 ⎯ ⎯ ⎯ pF Output capacitance Power dissipation capacitance Note: CPD (Note) ⎯ 50 MHz CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC/8 (per bit) 7 2007-10-01 TC74HC652AP Package Dimensions Weight: 1.50 g (typ.) 8 2007-10-01 TC74HC652AP RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. 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