NCP1587, NCP1587A Low Voltage Synchronous Buck Controller The NCP1587 and NCP1587A are low cost PWM controllers designed to operate from a 5 V or 12 V supply. These devices are capable of producing an output voltage as low as 0.8 V. These 8−pin devices provide an optimal level of integration to reduce size and cost of the power supply. The NCP1587/A provide a 1 A gate driver design and an internally set 275 kHz (NCP1587) and 200 kHz (NCP1587A) oscillator. In addition to the 1 A gate drive capability, other efficiency enhancing features of the gate driver include adaptive non−overlap circuitry. The devices also incorporate an externally compensated error amplifier and a capacitor programmable soft−start function. Protection features include programmable short circuit protection and under voltage lockout (UVLO). The NCP1587/A comes in an 8−pin SOIC package. http://onsemi.com MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 8 1 1 1587x = Specific Device Code (x = A for NCP1587A, blank for NCP1587) A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Device Features • • • • • • • • • • • • Input Voltage Range from 4.5 to 13.2 V 275 kHz (NCP1587) and 200 kHz (NCP1587A) Internal Oscillator Boost Pin Operates to 30 V Voltage Mode PWM Control 0.8 V ±1.0 % Internal Reference Voltage Adjustable Output Voltage Capacitor Programmable Soft−Start Internal 1 A Gate Drivers 80% Max Duty Cycle Input Under Voltage Lockout Programmable Current Limit This is a Pb−Free Device Applications • • • • • 1587x ALYW G PIN CONNECTIONS BST 1 8 PHASE TG 2 7 COMP/DIS GND 3 6 FB BG 4 5 VCC (Top View) ORDERING INFORMATION Graphics Cards Desktop Computers Servers / Networking DSP & FPGA Power Supply DC−DC Regulator Modules Package Shipping† NCP1587DR2G SOIC−8 (Pb−Free) 2500/Tape & Reel NCP1587ADR2G SOIC−8 (Pb−Free) 2500/Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2009 February, 2009 − Rev. 2 1 Publication Order Number: NCP1587/D NCP1587, NCP1587A 12 V 3.3 V VCC BST FB COMP/DIS TG VOUT PHASE BG GND Figure 1. Typical Application Diagram POR UVLO 5 VCC 1 BST 2 TG 8 PHASE VOCTH FAULT FB 6 + LATCH GM + - 0.8 V (VREF) SCP FAULT R S PWM OUT Q + - Clock 2V + - Ramp COMP/DIS 7 + - OSC VCC 4 OSC FAULT Figure 2. Detailed Block Diagram http://onsemi.com 2 3 BG Rset GND NCP1587, NCP1587A PIN FUNCTION DESCRIPTION Pin No. Symbol Description 1 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the PHASE pin. Typical values for CBST range from 0.1 mF to 1 mF. Ensure that CBST is placed near the IC. 2 TG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET. 3 GND 4 BG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET. 5 VCC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor to GND. Ensure that this decoupling capacitor is placed near the IC. 6 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly to Vout. 7 COMP/DIS 8 PHASE IC ground reference. All control circuits are referenced to this pin. Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. The compensation capacitor also acts as a soft−start capacitor. Pull this pin low for disable. Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. ABSOLUTE MAXIMUM RATINGS Pin Name Symbol VMAX VMIN Main Supply Voltage Input VCC 15 V −0.3 V Bootstrap Supply Voltage Input BST 35 V wrt/PGND 40 V < 50 ns wrt/PGND 15 V wrt/SW −0.3 V −0.3 V −0.3 V PHASE 35 V 40 V < 50 ns −5.0 V −10 V for < 200 ns High−Side Driver Output (Top Gate) TG 30 V wrt/GND 15 V wrt/PHASE −0.3 V wrt/PHASE −2 V < 200 ns wrt/PHASE Low−Side Driver Output (Bottom Gate) BG 15 V −0.3 V −5.0 V for < 200 ns Feedback FB 5.5 V −0.3 V COMP/DIS 5.5 V −0.3 V Switching Node (Bootstrap Supply Return) COMP/DISABLE MAXIMUM RATINGS Symbol Value Unit Thermal Resistance, Junction−to−Ambient Rating RqJA 165 °C/W Thermal Resistance, Junction−to−Case RqJC 45 °C/W NCP1587A Operating Junction Temperature Range TJ 0 to 125 °C NCP1587A Operating Ambient Temperature Range TA 0 to 70 °C Storage Temperature Range Tstg −55 to +150 °C 260 °C 3 − Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free Moisture Sensitivity Level MSL Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 NCP1587, NCP1587A ELECTRICAL CHARACTERISTICS (0_C < TA < 70_C; 4.5 V < VCC < 13.2 V, 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V, 0 V < PHASE < 21 V, CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.) Conditions Min Typ Max Unit Input Voltage Range − 4.5 − 13.2 V Boost Voltage Range − 4.5 − 26.5 V Quiescent Supply Current VFB = 1.0 V, No Switching, VCC = 13.2 V 1.0 − 8.0 mA Boost Quiescent Current VFB = 1.0 V, No Switching, VCC = 13.2 V 0.1 − 1.0 mA UVLO Threshold VCC Rising Edge 3.8 − 4.2 V UVLO Hysteresis − − 350 − mV TA = 0 to 70°C 792 800 808 mV TA = 0 to 70°C 250 180 275 200 300 220 kHz 0.8 1.1 1.4 V Characteristic Supply Current Under Voltage Lockout Switching Regulator VFB Feedback Voltage, Control Loop in Regulation Oscillator Frequency NCP1587 NCP1587A Ramp−Amplitude Voltage Minimum Duty Cycle 0 − − % Maximum Duty Cycle 70 75 80 % Transconductance 3.0 − 4.4 mmho Open Loop DC Gain 55 70 − DB 80 80 120 120 − − mA − 0.1 1.0 mA Error Amplifier (GM) Output Source Current Output Sink Current VFB < 0.8 V VFB > 0.8 V Input Bias Current Soft−Start SS Source Current VFB < 0.8 V − 11 − mA Switch Over Threshold VFB = 0.8 V − 100 − % of Vref Upper Gate Source − 1.0 − A Upper Gate Sink − 1.0 − A − 1.0 − A − 2.0 − A − 40 90 ns Gate Drivers Lower Gate Source VCC = 12 V, VTG = VBG = 2.0 V Lower Gate Sink TG Falling to BG Rising Delay VCC = 12 V, TG < 2.0 V, BG > 2.0 V BG Falling to TG Rising Delay VCC = 12 V, BG < 2.0 V, TG > 2.0 V Enable Threshold − 35 90 ns 0.3 0.4 0.5 V − 10 − mA Over−Current Protection OCSET Current Source Sourced from BG pin, before SS OC Switch−Over Threshold − 700 − mV Fixed OC Threshold − −375 − mV http://onsemi.com 4 NCP1587, NCP1587A 5.0 203 4.7 202 FSW, FREQUENCY (Khz) ICC (mA) TYPICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) 4.4 4.1 3.8 0 10 20 30 40 50 60 VCC = 12 V 199 VCC = 5 V 198 70 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) Figure 3. ICC vs. Temperature Figure 4. Oscillator Frequency (FSW) vs. Temperature 70 375 14 SCP THRESHOLD (mV) 13 12 11 10 9 8 200 TJ, JUNCTION TEMPERATURE (°C) 0 10 20 30 40 50 60 365 355 345 335 325 70 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Soft Start Sourcing Current vs. Temperature Figure 6. SCP Threshold vs. Temperature 808 806 Vref, REFERENCE (mV) SOFT START SOURCING CURRENT (mA) 3.5 201 804 802 800 798 796 794 792 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) Figure 7. Reference Voltage (Vref) vs. Temperature http://onsemi.com 5 70 70 NCP1587, NCP1587A DETAILED OPERATING DESCRIPTION General External Enable/Disable The NCP1587 and NCP1587A are PWM controllers intended for DC−DC conversion from 5.0 V & 12 V buses. The devices have a 1 A internal gate driver circuit designed to drive N−channel MOSFETs in a synchronous−rectifier buck topology. The output voltage of the converter can be precisely regulated down to 800 mV ±1.0% when the VFB pin is tied to VOUT. The switching frequency, is internally set to 275 kHz (NCP1587) and 200 kHz (NCP1587A). A high gain operational transconductance error amplifier (OTA) is used. When the Comp pin voltage falls or is pulled externally below the 400 mV threshold, it disables the PWM Logic and the gate drive outputs. In this disabled mode, the operational transconductance amplifier (EOTA) output source current is reduced and limited to the Soft−Start mode of 10 mA. Normal Shutdown Behavior Normal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal SS is discharged, and all GATE pins go low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. Duty Cycle and Maximum Pulse Width Limits In steady state DC operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. The devices can achieve an 80% duty cycle. There is a built in off−time which ensures that the bootstrap supply is charged every cycle. Both parts can allow a 12 V to 0.8 V conversion at 275 kHz (NCP1587) and 200 kHz (NCP1587A). External Soft−Start The NCP1587/A features an external soft−start function, which reduces inrush current and overshoot of the output voltage. Soft−start is achieved by using the internal current source of 10 mA (typ), which charges the external integrator capacitor of the transconductance amplifier. Figure 8 is a typical soft−start sequence. This sequence begins once VCC surpasses its UVLO threshold and OCP programming is complete. During soft−start, as the Comp Pin rises through 400 mV, the PWM Logic and gate drives are enabled. When the feedback voltage crosses 800 mV, the EOTA will be given control to switch to its higher regulation mode output current of 120 mA. Input Voltage Range (VCC and BST) The input voltage range for both VCC and BST is 4.5 V to 13.2 V with respect to GND and PHASE, respectively. Although BST is rated at 13.2 V with respect to PHASE, it can also tolerate 26.4 V with respect to GND. 4.2 V VCC 0.9 V Comp 0.8 V Vfb 550 mV BG 50 mV OCP Program ming TG Vout POR UVLO SS NORMAL Figure 8. Soft−Start Implementation http://onsemi.com 6 NCP1587, NCP1587A UVLO go through a Power On Reset (POR) cycle to reset the OCP fault. Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VCC is too low to support the internal rails and power the converter. For the NCP1587/A, the UVLO is set to permit operation when converting from a 5.0 input voltage. Drivers The NCP1587 and NCP1587A include gate drivers to switch external N−channel MOSFETs. This allows the devices to address high−power as well as low−power conversion requirements. The gate drivers also include adaptive non−overlap circuitry. The non−overlap circuitry increase efficiency, which minimizes power dissipation, by minimizing the body diode conduction time. A detailed block diagram of the non−overlap and gate drive circuitry used in the chip is shown in Figure 9. Overcurrent Threshold Setting NCP1587/A can easily program an Overcurrent Threshold ranging from 50 mV to 550 mV, simply by adding a resistor (RSET) between BG and GND. During a short period of time following VCC rising over UVLO threshold, an internal 10 mA current (IOCSET) is sourced from BG pin, determining a voltage drop across ROCSET. This voltage drop will be sampled and internally held by the device as Overcurrent Threshold. The OC setting procedure overall time length is about 6 ms. Connecting a ROCSET resistor between BG and GND, the programmed threshold will be: I @ ROCSET IOCth + OCSET RDS(on) FAULT 1 BST 2 TG 8 PHASE (eq. 1) RSET values range from 5 kW to 55 kW. In case ROCSET is not connected, the device switches the OCP threshold to a fixed 375 mV value: an internal safety clamp on BG is triggered as soon as BG voltage reaches 700 mV, enabling the 375 mV fixed threshold and ending OC setting phase. The current trip threshold tolerance is ±25 mV. The accuracy of the set point is best at the highest set point (550 mV). The accuracy will decrease as the set point decreases. + 2V + - VCC 4 BG Rset Current Limit Protection In case of a short circuit or overload, the low−side (LS) FET will conduct large currents. The controller will shut down the regulator in this situation for protection against overcurrent. The low−side RDS(on) sense is implemented at the end of each of the LS−FET turn−on duration to sense the over current trip point. While the LS driver is on, the Phase voltage is compared to the internally generated OCP trip voltage. If the phase voltage is lower than OCP trip voltage, an overcurrent condition occurs and a counter is initiated. When the counter completes, the PWM logic and both HS−FET and LS−FET are turned off. The controller has to 3 FAULT GND Figure 9. Block Diagram Careful selection and layout of external components is required, to realize the full benefit of the onboard drivers. The capacitors between VCC and GND and between BST and SWN must be placed as close as possible to the IC. The current paths for the TG and BG connections must be optimized. A ground plane should be placed on the closest layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit. http://onsemi.com 7 NCP1587, NCP1587A APPLICATION SECTION Input Capacitor Selection The above calculation includes the delay from comp rising to when output voltage starts becomes valid. To calculate the time of output voltage rising to when it reaches regulation; DV is the difference between the comp voltage reaching regulation and 0.9 V. The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is: Iin RMS + I OUT ǸD (1 * D) , Output Capacitor Selection The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initial drops due to the current variation inside the capacitor and the ESR. ((neglecting the effect of the effective series inductance (ESL)): where D is the duty cycle, IinRMS is the input RMS current, & IOUT is the load current. The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation: P CIN + ESR CIN Iin RMS 2 , where PCIN is the power loss in the input capacitors & ESRCIN is the effective series resistance of the input capacitance. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must by surge protected. Otherwise, capacitor failure could occur. DV OUT−ESR + DI OUT where VOUT-ESR is the voltage deviation of VOUT due to the effects of ESR and the ESRCOUT is the total effective series resistance of the output capacitors. A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation: Calculating Input Start-up Current To calculate the input start up current, the following equation can be used. I inrush + C OUT t SS V OUT , where Iinrush is the input current during start-up, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft start interval. If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used. DV OUT−DISCHARGE + 2 DI OUT 2 L OUT , C OUT (V IN D * V OUT) where VOUT-DISCHARGE is the voltage deviation of VOUT due to the effects of discharge, LOUT is the output inductor value & VIN is the input voltage. It should be noted that ΔVOUT-DISCHARGE and ΔVOUT-ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Calculating Soft Start Time To calculate the soft start time, the following equation can be used. t ss + ESR COUT (C p ) C c) * DV I ss Inductor Selection Both mechanical and electrical considerations influence the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space-constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by: Where Cc is the compensation as well as the soft start capacitor, Cp is the additional capacitor that forms the second pole. Iss is the soft start current DV is the comp voltage from zero to until it reaches regulation: ((d * ramp) + 0.9) DV 900 mV SlewRate LOUT + V IN * V OUT L OUT This equation implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This results in larger values of output capacitance to maintain Vcomp Vout http://onsemi.com 8 NCP1587, NCP1587A tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak-to-peak ripple current for NCP1587 is given by the following equation: Figure 10 shows a typical Type II transconductance error amplifier (EOTA). The compensation network consists of the internal error amplifier and the impedance networks ZIN (R1, R2) and external ZFB (Rc, Cc and Cp). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response (but always lower than FSW/8) and the highest gain in DC conditions to minimize the load regulation. A stable control loop has a gain crossing with -20 dB/decade slope and a phase margin greater than 45°. Include worst-case component variations when determining phase margin. Loop stability is defined by the compensation network around the EOTA, the output capacitor, output inductor and the output divider. Figure 11 shows the open loop and closed loop gain plots. V OUT(1 * D) , L OUT 275 kHz Ipk * pk LOUT + where Ipk-pkLOUT is the peak to peak current of the output. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade-off between dynamic response and ripple current. Feedback and Compensation The NCP1587 allows the output of the DC-DC converter to be adjusted from 0.8 V to 5.0 V via an external resistor divider network. The controller will try to maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to VOUT, the controller will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin. Compensation Network Frequency: The inductor and capacitor form a double pole at the frequency F LC + VOUT ǸL o Co The ESR of the output capacitor creates a “zero” at the frequency, R1 F ESR + FB 2p 1 ESR Co The zero of the compensation network is formed as, R2 FZ + ǒ 2p 1 R cC c The pole of the compensation network is calculated as, The relationship between the resistor divider network above and the output voltage is shown in the following equation: R2 + R1 1 2p Fp + Ǔ 2p V REF V OUT * V REF 1 Rc Cp Resistor R1 is selected based on a design tradeoff between efficiency and output voltage accuracy. For high values of R1 there is less current consumption in the feedback network, However the trade off is output voltage accuracy due to the bias current in the error amplifier. The output voltage error of this bias current can be estimated using the following equation (neglecting resistor tolerance): Error% + 0.1 mA R 1 V REF 100% Once R1 has been determined, R2 can be calculated. Figure 11. Gain Plot of the Error Amplifier R1 Thermal Considerations EA The power dissipation of the NCP1587 varies with the MOSFETs used, VCC, and the boost voltage (VBST). The average MOSFET gate current typically dominates the control IC power dissipation. The IC power dissipation is determined by the formula: Gm Cc Rc Cp Vref + R2 − P IC + (I CC Figure 10. Type II Transconductance Error Amplifier Where: http://onsemi.com 9 V CC) ) P TG ) P BG NCP1587, NCP1587A PIC = control IC power dissipation, ICC = IC measured supply current, VCC = IC supply voltage, PTG = top gate driver losses, PBG = bottom gate driver losses. The upper (switching) MOSFET gate driver losses are: P TG + Q TG f SW V BST Where: QTG = total upper MOSFET gate charge at VBST, fSW = the switching frequency, VBST = the BST pin voltage. The lower (synchronous) MOSFET gate driver losses are: P BG + Q BG f SW Figure 12. Components to be Considered for Layout Specifications DESIGN EXAMPLE I: Type II Compensation (Electrolytic Cap. with large ESR) Switching Frequency FSW = 275 KHz Output Capacitance RESR = 45 mW/Each Output Capacitance Cout = 2×1800 mF Output Inductance Lout = 1 mH Input Voltage Vin = 12 V Output Voltage Vout = 1.6 V Choose the loop gain crossover frequency; V CC Where: QBG = total lower MOSFET gate charge at VCC. The junction temperature of the control IC can then be calculated as: T J + T A ) P IC q JA F co + 1 5 Where: TJ = the junction temperature of the IC, TA = the ambient temperature, θJA = the junction−to−ambient thermal resistance of the IC package. The package thermal resistance can be obtained from the specifications section of this data sheet and a calculation can be made to determine the IC junction temperature. However, it should be noted that the physical layout of the board, the proximity of other heat sources such as MOSFETs and inductors, and the amount of metal connected to the IC, impact the temperature of the device. Use these calculations as a guide, but measurements should be taken in the actual application. F sw + 55 KHz The corner frequency of the output filter is calculated below; F LC + 1 2 Ǹ1 mH p + 2.65 KHz 3600 mF Check that the ESR zero frequency is not too high; F ESR + F ESR + 2 p 1 R ESR 2 p 45 mW 2 CO t F co 10 1 (1800 mF 2) + 2 KHz If ESR zero is larger than Fco/10, Type III compensation is necessary. Choose CC for the crossover frequency and the soft start Layout Considerations C C + 100 nF As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. The figure below shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in the figure below should be located as close together as possible. Please note that the capacitors CIN and COUT each represent numerous physical capacitors. It is desirable to locate the NCP1587 within 1 inch of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the NCP1587 must be sized to handle up to 2 A peak current. The compensation capacitor (CC) is related to the loop gain magnitude, zero position and the soft start. By adjusting the value of this compensation capacitor, the crossover frequency and the soft start time can be adjusted. Zero of the compensation network is calculated as follows; F Z + F LC + 2.65 KHz RC + + 2 p 2 p 1 Fz CC 1 2.65 kHz 100 nF + 600.6 W Pole of the compensation network is calculated as follows; F p + F sw + 275 KHz 1 Cp + 2 p Fp RC 1 + 2 p 275 kHz 600.6 + 963.6 pF The recommended compensation values are; RC = 604, CC = 100 nF, CP = 1000 pF http://onsemi.com 10 NCP1587, NCP1587A Blue curve: Gain-Frequency Red curve: Gain-Frequency (Phase margin = 61.417 degree, Gain margin = 9.347 dB) Figure 13. Closed-loop Voltage Loop-gain of the NCP1587 DESIGN EXAMPLE II: Type III Compensation (Oscon Cap. with small ESR; Do not place RC, CC, CP) Switching Frequency Fsw = 275 KHz Output Capacitance RESR = 7 mW/Each Output Capacitance Cout = 2×560 mF Output Inductance Lout = 1 mH Input Voltage Vin = 12 V Output Voltage Vout = 1.6 V Choose the loop gain crossover frequency; F co + 1 5 R C1 + + F sw + 55 KHz 2 1 Ǹ1 mH p 1120 mF F ESR + F ESR + 2 F z2 + F LC + 4.7 KHz 2 C20 + p CO p 1 7 mW 560 mF 2 R3 + 10 kW + 4.7 KHz Check the ESR zero frequency; 1 R ESR 2 RC1 should be much larger than 2/gm in order to get the stable system with transconductance amplifier. Ù choose RC1 = 12.1 kW 2nd zero; Choose R3 for the crossover frequency. R3 should be much larger than 2/gm for the stable system. The corner frequency of the output filter is calculated below; F LC + F LC + 470 Hz 10 1 p F z1 C C1 1 + 11.3 kW p 470 Hz 30 nF F Z1 + 2 p 2 p + + 40.6 KHz 1 F z2 R3 1 + 3.4 nF 4.7 KHz 10 kW Choose C20 = 3.3 nF Poles of the compensation network are calculated as follows; 1st pole; Choose R4 to cancel the output capacitor ESR zero. Choose CC1 for the soft start C C1 + 33 nF The compensation capacitor (CC1) is related to the loop gain magnitude, one zero position and the soft start. By adjusting the value of this compensation capacitor, the crossover frequency and the soft start time can be adjusted. Zeros of the compensation network are calculated as follows; 1st zero; F P1 + F ESR + 40.6 KHz R4 + + http://onsemi.com 11 2 2 p 1 F P1 p 1 40.6 kHz C20 3.3 n + 1.2 kW NCP1587, NCP1587A After choose R4 value, adjust R4 to get enough phase margin Ù R4 = 665 W 2nd pole; Choose CP1 to eliminate the noise; Choose CP1 = 47 pF The recommended compensation values are; R2 = 10 kW, R3 = 10 kW, R4 = 665 W, RC1 = 12.1 kW, CC1 = 33 nF, CP1= 47 pF, C20 = 3.3 nF F P2 + F sw + 275 KHz C P1 + + 2 p 2 p 1 F P2 R C1 1 + 48.23 pF 275 kHz 12 kW Blue curve: Gain-Frequency Red curve: Gain-Frequency (Phase margin = 80.285 degree, Gain margin = 19.362 dB) Figure 14. Closed-loop Voltage Loop-gain of the NCP1587 http://onsemi.com 12 TP96 TP95 MH1 GND VCC GND TP2 MH2 MH3 VCC Vbst Figure 15. Demo Board PCB Layout http://onsemi.com MH4 Rc 604 TP106 R3 1.02K FB Cp 100pF TP105 R2 1.02K CC 0.1uF TP98 TP97 COMP 1 TP94 R4 DNP C20 DNP FB Cp1 DNP COMP TP93 7 TG BST U1 10 R1 2 TG Note : gating length s 1 BST R5 5.11 R639 NI TP108 TP110 TP112 TP111 BG R6 0 R7 0 TP107 TP109 length sho DNP + C5 Vin DPAK Q6 NTD4806 DPAK Q2 NTD4815 C19 10uF DUAL PLACEMENT SITE DPAK Q5 NTD4806 DPAK Q1 NTD4815 C22 10uF IPAK Q8 NTD4806 IPAK Q4 NTD4815 DUAL PLACEMENT SITE IPAK Q7 NTD4806 IPAK Q3 NTD4815 G C23 10uF DUAL PLACEMENT SITE 1500uF + C4 DUAL PLACEMENT SITE TP113 TP20 C18 10uF GND Vin C11 0.1uF TP101 TG TP99 CR1 BAS116LT1 8 SWITCH_NODE PHASE Note : gating NCP1587 COMP C8 1uF C9 1uF 6 FBBG 4 BG Cc1 DNP Rc1 DNP R90 1 3 TP1 5 VCC GND 3 G SO8−FL SO8−FL Q12 DNP G Q10 DNP C21 DNP R8 DNP L11uH L2DNP 1800uF +C12 SWITCH_NODE SO8−FL DUAL PLACEMENT SITE Q11 DNP G SO8−FL Q9 DNP DUAL PLACEMENT SITE C25 10uF D S D D S D S 13 S Vbst 1800uF +C13 TP104 TP100 DNP + C15 DNP + C24 C16 10uF C17 10uF VOUT GND GND TP9 OUTPU TP7 TP103 TP102 VOUT NCP1587, NCP1587A NCP1587, NCP1587A Bill of Materials Item Number Part Reference Value Quantity MFG 1 C4 1500 mF 1 PANASONIC 2 C5 DNP 1 - 3 C8,C9 1 mF 2 TAIYO YUDEN 4 C11 0.1 mF 1 AVX 5 C12,C13 1800 mF 2 PANASONIC 6 C15,C24 DNP 2 - 7 C16,C17,C18,C19,C22,C23,C25 10 mF 7 PANASONIC 8 C20,CC1,CP1 DNP 3 - 9 C21 DNP 1 - 10 CC 0.1 mF 1 TDK 11 CR1 BAS116LT1 1 ON SEMICONDUCTOR 12 CP 100 pF 1 PANASONIC 13 J9 20PIN 2ROW 1 MOLEX 14 J23 5PIN 1 PASTERNACK ENTERPRISES 15 L1 1 mH 1 PANASONIC 16 L2 DNP 1 - 17 Q1,Q2 NTD4815 2 ON SEMICONDUCTOR 18 Q3,Q4 NTD4815 2 ON SEMICONDUCTOR 19 Q5,Q6 NTD4806 2 ON SEMICONDUCTOR 20 Q7,Q8 NTD4806 2 ON SEMICONDUCTOR 21 Q9,Q10,Q11,Q12 DNP 4 - 22 Q17,Q18,Q19,Q20,Q21,Q22,Q23,Q24,Q25,Q26, Q27,Q28,Q29,Q30,Q31,Q32,Q33,Q34,Q35,Q36, Q37,Q38,Q39,Q40 NTHS5404T1 24 ON SEMICONDUCTOR 23 R1 10 1 PANASONIC 24 R2,R3 1.02 K 2 DALE 25 R4,RC1 DNP 2 - 26 R5 5.11 1 DALE 0 3 PANASONIC 27 R6,R7 28 R8, R639 DNP 1 - 29 R9 0 1 DALE 30 R551,R552,R553,R569,R570,R571,R584,R585, R586,R599,R600,R601,R608,R609,R610,R617, R618,R619,R626,R627,R628,R635,R636,R637 100 K 24 DALE 31 R602,R603,R604,R605,R606,R607,R611,R612, R613,R614,R615,R616,R620,R621,R622,R623, R624,R625,R629,R630,R631,R632,R633,R634 0.56 24 PANASONIC 32 R638 49.9 1 DALE 33 RC 604 1 DALE 34 TP97,TP98,TP99,TP100,TP101,TP102,TP103, TP104,TP105,TP106,TP107,TP108,TP109, TP110,TP111,TP112 TP 16 KEYSTONE 35 U1 NCP1587 1 ON SEMICONDUCTOR http://onsemi.com 14 NCP1587, NCP1587A Figure 16. Gate Waveforms 20 A Load Sustaining Figure 17. Over Current Protection (12.4 A DC Trip) Figure 18. Start-up Sequence Figure 19. Transient Response 0-10 A Load Step Efficiency (%) NCP1587 Efficiency 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 0 2 4 6 8 10 12 Load Current (A) Figure 20. Efficiency vs. Load Current http://onsemi.com 15 14 16 NCP1587, NCP1587A PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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