HIP6011 Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor September 1997 Features Description • Drives N-Channel MOSFET The HIP6011 provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive an N-Channel MOSFET in a standard buck topology. The HIP6011 integrates all of the control, output adjustment, monitoring and protection functions into a single package. • Operates From +5V or +12V Input • Simple Single-Loop Control Design - Voltage-Mode PWM Control • Fast Transient Response The output voltage of the converter can be precisely regulated to as low as 1.27V, with a maximum tolerance of ±1.5% over temperature and line voltage variations. - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio • Excellent Output Voltage Regulation The HIP6011 provides simple, single feedback loop, voltagemode control with fast transient response. It includes a 200kHz free-running triangle-wave oscillator that is adjustable from below 50kHz to over 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/µs slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. - 1.27V Internal Reference - ±1.5% Over Line Voltage and Temperature • Over-Voltage and Over-Current Fault Monitors - Does Not Require Extra Current Sensing Element - Uses MOSFET’s rDS(ON) • Small Converter Size The HIP6011 protects against over-current conditions by inhibiting PWM operation. The HIP6011 monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. Built-in over-voltage protection triggers an external SCR to crowbar the input supply. - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to Over 1MHz Applications Ordering Information • Power Supply for Pentium™, Pentium-Pro™, PowerPC™ and Alpha™ Microprocessors PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. • High-Power 5V to 3.xV DC-DC Regulators HIP6011 • Low-Voltage Distributed Power Supplies 0 to 70 14 Ld SOIC M14.15 Pinout HIP6011 (SOIC) TOP VIEW VSEN 1 14 RT OCSET 2 13 OVP SS 3 12 VCC COMP 4 11 NC FB 5 10 BOOT EN 6 9 UGATE GND 7 8 PHASE Alpha™ is a trademark of Digital Equipment Corporation. Pentium™ is a trademark of Intel Corporation. Pentium™ Pro is a trademark of Intel Corporation. PowerPC™ is a trademark of IBM. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 4409 HIP6011 Typical Application +12V +5V OR +12V VCC OCSET MONITOR AND PROTECTION SS EN BOOT OVP RT OSC UGATE HIP6011 +VO PHASE REF FB - + + - COMP VSEN GND Block Diagram VCC OVP VSEN 115% OVERVOLTAGE POWER-ON RESET (POR) EN + - 10µA SOFTSTART + - OCSET OVERCURRENT 200µA SS BOOT UGATE 4V PHASE REFERENCE FB PWM COMPARATOR 1.27V REF + + - - ERROR AMP GATE INHIBIT CONTROL LOGIC PWM COMP GND RT OSCILLATOR All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 2 HIP6011 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . . +15.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Recommended Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . .0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . . .0oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT Nominal Supply ICC Shutdown Supply EN = VCC; UGATE and LGATE open 5 EN = 0V 50 mA 100 µA 10.4 V POWER-ON RESET Rising VCC Threshold VOCSET = 4.5VDC Falling VCC Threshold VOCSET = 4.5VDC 8.2 Enable - Input threshold Voltage VOCSET = 4.5VDC 0.8 Rising VOCSET Threshold V 2.0 1.26 V V OSCILLATOR Free Running Frequency RT = OPEN, VCC = 12V 180 Total Variation 6kΩ < RT to GND < 200kΩ -20 Ramp Amplitude ∆VOSC RT = OPEN 200 220 kHz +20 % 1.9 VP-P 1.251 1.270 1.289 V 88 dB 15 MHz 6 V/µs 500 mA REFERENCE Reference Voltage VREF ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate GBW SR COMP = 10pF GATE DRIVERS Upper Gate Source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V Upper Gate Sink RUGATE ILGATE = 0.3A 350 5.5 10 Ω 115 120 % 200 230 µA PROTECTION Over-Voltage Trip (VSEN/VREF) OCSET Current Source IOCSET OVP Sourcing Current IOVP Soft Start Current VOCSET = 4.5VDC 170 VSEN = 5.5V; VOVP = 0V 60 ISS mA 10 3 µA HIP6011 Typical Performance Curves 40 CGATE = 3300pF 30 25 ICC (mA) RESISTANCE (kΩ) 35 RT PULLUP TO +12V 1000 RT PULLDOWN TO VSS 100 10 20 CGATE = 1000pF 15 10 CGATE = 10pF 5 10 100 0 100 1000 SWITCHING FREQUENCY (kHz) FIGURE 1. RT RESISTANCE vs FREQUENCY 1 14 RT OCSET 2 13 OVP SS 3 12 VCC COMP 4 11 NC FB 5 10 BOOT EN 6 9 UGATE GND 7 8 PHASE 300 400 500 600 700 800 SWITCHING FREQUENCY (kHz) 900 1000 FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY Functional Pin Description VSEN 200 GND (Pin 7) Signal ground for the IC. All voltage levels are measured with respect to this pin. PHASE (Pin 8) Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. UGATE (Pin 9) Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. VSEN (Pin 1) This pin is connected to the converters output voltage. The OVP comparator circuit uses this signal for overvoltage protection. BOOT (Pin 10) This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. OCSET (Pin 2) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET , an internal 200µA current source (IOCS), and the upper MOSFET on-resistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation: VCC (Pin 12) Provide a 12V bias supply for the chip to this pin. OVP (Pin 13) This pin drives an external SCR in the event of an overvoltage condition. I OCS • ROCSET I PEAK = -------------------------------------------r DS ( ON ) RT (Pin 14) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: An over-current trip cycles the soft-start function. SS (Pin 3) Connect a capacitor from this pin to ground. This capacitor, along with an internal 10µA current source, sets the soft-start interval of the converter. 7 4 • 10 F S ≈ 200kHz – --------------------RT ( kΩ ) COMP (Pin 4) and FB (Pin 5) COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. (RT to 12V) Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation: 7 4 • 10 F S ≈ 200kHz – --------------------RT ( kΩ ) EN (Pin 6) This pin is the open-collector enable pin. Pull this pin below 1V to disable the converter. In shutdown, the soft start pin is discharged and the UGATE and LGATE pins are held low. 4 (RT to 12V) HIP6011 Functional Description Over-Current Protection Initialization The over-current function protects the converter from a shorted output by using the upper MOSFET’s on-resistance, rDS(ON) to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. SOFT-START The HIP6011 automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages and the enable (EN) pin. The POR monitors the bias voltage at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see over-current protection). With the EN pin held to VCC, the POR function initiates soft start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold before POR initiates operation. 4V 2V OUTPUT INDUCTOR 0V The Power-On Reset (POR) function inhibits operation with the chip disabled (EN pin low). With both input supplies above their POR thresholds, transitioning the EN pin high initiates a soft start interval. 15A 10A 5A 0A Soft Start The POR function initiates the soft start sequence. An internal 10µA current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 3 shows the soft start interval with CSS = 0.1µF. Initially the clamp on the error amplifier (COMP pin) controls the converter’s output voltage. At t1 in Figure 3, the SS voltage reaches the valley of the oscillator’s triangle wave. The oscillator’s triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2. With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 3. At t3 the SS voltage exceeds the DACOUT voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. TIME (20ms/DIV) FIGURE 4. OVER-CURRENT OPERATION The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level. An internal 200µA (typical) current sink develops a voltage across ROCSET that is reference to VIN . When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET , the over-current function initiates a soft-start sequence. The soft-start function discharges CSS with a 10µA current sink and inhibits PWM operation. The soft-start function recharges CSS , and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS , the soft start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 4 shows this operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 4 is 2.5W. SOFT-START (1V/DIV) The over-current function will trip at a peak inductor current (IPEAK) determined by: I OCSET • ROCSET I PEAK = --------------------------------------------------r DS ( ON ) OUTPUT VOLTAGE (1V/DIV) 0V where IOCSET is the internal OCSET current source (200µA - typical). The OC trip point varies mainly due to the MOSFET’s rDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 0V t1 t2 t3 TIME (5ms/DIV) FIGURE 3. SOFT START INTERVAL 1) The maximum rDS(ON) at the highest junction temperature. 5 HIP6011 2) The minimum IOCSET from the specification table. 3) Determine IPEAK for I PEAK > Iout ( max ) + ( ∆I ) ⁄ 2 , where ∆I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. +VIN BOOT D1 VOUT HIP6011 SS VCC +12V CO D2 CVCC CSS Application Guidelines GND Layout Considerations FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). VIN DRIVER OSC VIN PWM COMPARATOR HIP6011 LO - ∆VOSC LO Q1 VE/A LOAD CO CO ESR (PARASITIC) ZFB CIN VOUT PHASE + VOUT PHASE D2 LOAD PHASE A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. UGATE Q1 LO CBOOT ZIN + ERROR AMP REFERENCE DETAILED COMPENSATION COMPONENTS RETURN ZFB VOUT C2 FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS C1 Figure 5 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 6 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the HIP6011 within 3 inches of the MOSFET, Q1. The circuit traces for the MOSFET’s gate and source connections from the HIP6011 must be sized to handle up to 1A peak current. ZIN C3 R2 R3 R1 COMP FB + HIP6011 REF FIGURE 7. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC . Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, Css close to the SS pin because the internal current source is only 10µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the Boot and PHASE pins. Modulator Break Frequency Equations 1 LC = --------------------------------------2π • L O • C O 6 1 F ESR = -------------------------------------------2π • ( ESR • C O ) HIP6011 The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. The compensation network consists of the error amplifier (internal to the HIP6011) and the impedance networks ZIN and ZFB . The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use these guidelines for locating the poles and zeros of the compensation network: 1) 2) 3) 4) 5) 6) 7) Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Pick Gain (R2/R1) for Desired Converter Bandwidth Place 1STZero Below Filter’s Double Pole (~75% FLC) Place 2ND Zero at Filter’s Double Pole Place 1ST Pole at the ESR Zero Place 2ND Pole at Half the Switching Frequency Check Gain against Error Amplifier’s Open-Loop Gain Estimate Phase Margin - Repeat if Necessary Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. Compensation Break Frequency Equations 1 F Z1 = --------------------------------2π • R2 • C1 1 F P1 = -----------------------------------------------------C1 • C2 2π • R2 • ---------------------- C1 + C2 1 F Z2 = ----------------------------------------------------2π • ( R1 + R3 ) • C3 1 F P2 = --------------------------------2π • R3 • C3 High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium-Pro be composed of at least forty (40) 1.0µF ceramic capacitors in the 1206 surface-mount package. Figure 8 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak do to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 8 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. 100 FZ1 FZ2 FP1 Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. FP2 80 GAIN (dB) 60 OPEN LOOP ERROR AMP GAIN 40 Output Inductor Selection 20 20LOG(R2/R1) The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: 20LOG(VIN /DVOSC) 0 -20 COMPENSATION GAIN MODULATOR GAIN -40 FLC -60 10 100 CLOSED LOOP GAIN FESR 1K 10K 100K FREQUENCY (HZ) 1M V IN - VO UT VO UT ∆I = -------------------------------- • ---------------Fs × L O V IN 10M ∆V O UT = ∆I x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN 7 HIP6011 Switching losses also contribute to the overall MOSFET power loss (see the equations below). These equations assume linear voltage-current transitions and are approximations. The gate-charge losses are dissipated by the HIP6011 and don't heat the MOSFET. However, large gate-charge increases the switching interval, tSW , which increases the upper MOSFET switching losses. Ensure that the MOSFET is within its maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6011 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: tRISE = L x ITRAN VIN - VO tFALL = PCOND = IO2 x rDS(ON) x D 1 PSW = 2 IO x VIN x tSW x FS Where: D is the duty cycle = VO / VIN , tSW is the switching interval, and FS is the switching frequency. L x ITRAN VO where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Standard-gate MOSFETs are normally recommended for use with the HIP6011. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFET’s absolute gate-to-source voltage rating determine whether logic-level MOSFETs are appropriate. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the anode of Schottky diode D2. DBOOT +12V + VCC HIP6011 VD +5V OR +12V - BOOT CBOOT Q1 UGATE The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. PHASE NOTE: VG-S ≈ VCC - VD D2 - + GND FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. Figure 9 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC . The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. A logic-level MOSFET can only be used for Q1 if the MOSFET’s absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC . MOSFET Selection/Considerations The HIP6011 requires an N-channel power MOSFET. It should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. Figure 10 shows the upper gate drive supplied by a direct connection to VCC. This option should only be used in converter systems where the main input voltage is +5VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level MOSFET is a good choice for Q1 under these conditions. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for the MOSFET. 8 HIP6011 +12V The power dissipation in the schottky rectifier is approximated by: +5V OR LESS VCC PCOND = IO x Vf x (1 - D) BOOT HIP6011 Where: D is the duty cycle = VO /VIN, and Vf is the schottky forward voltage drop Q1 UGATE NOTE: VG-S ≈ VCC - 5V PHASE In addition to power dissipation, package selection and heatsink requirements are the main design tradeoffs in choosing the schottky rectifier. Since the three factors are interrelated, the selection process is an iterative procedure. The maximum junction temperature of the rectifier must remain below the manufacturer’s specified value, typically 125oC. By using the package thermal resistance specification and the schottky power dissipation equation (shown above), the junction temperature of the rectifier can be estimated. Be sure to use the available airflow and ambient temperature to determine the junction temperature rise. - + D2 GND FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION Schottky Selection Rectifier D2 conducts when the upper MOSFET Q1 is off. The diode should be a Schottky type for low power losses. HIP6011 DC-DC Converter Application Circuit The Figure below shows an application circuit of a DC-DC Converter for a microprocessor application. 12VCC VIN C17-C18 2x 1µF 1206 Q2 2N6394 C1-C5 3x 680µF RTN R8 10K C12 1µF 1206 R7 10K ENABLE EN 6 SS 3 C19 VCC OVP 12 13 3.01K Q1 R1 SPARE 33pF R5 0.01µF 15K C16 R3 1K SPARE VOUT - - CR3 4 C15 L2 8 PHASE + + C14 C20 0.1µF 9 UGATE U1 HIP6011 REF R2 1K PHASE TP2 10 BOOT OSC FB 5 R6 2 OCSET MONITOR AND PROTECTION RT 14 C13 0.1µF CR1 4148 1000pF 1 VSEN 7 COMP C6-C11 4x 1000µF RTN GND R8 COMP TP1 1K R7 1K R4 SPARE Component Selection Notes: C1-3 - 3 Each 680µF 25W VDC, Sanyo MV-GX or Equivalent CR1 - 1N4148 or Equivalent C6-9 - 4 Each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent CR3 - 15A, 35V Schottky, Motorola MBR1535CT or Equivalent L1 - Core: Micrometals T60-52; Winding: 14Turns of 17AWG Q1 - Intersil MOSFET; RFP25N05 9