ROHM NC7WZ07P6X

NC7WZ07
TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
Features
Description





Ultra-High Speed: tPZL 2.3 ns (Typical)


Proprietary Noise/EMI Reduction Circuitry
The NC7WZ07 is a dual buffer with open-drain outputs
from Fairchild’s Ultra-High Speed (UHS) series of
TinyLogic®. The device is fabricated with advanced
CMOS technology to achieve ultra-high speed with high
output drive, while maintaining low static power
dissipation over a broad VCC operating range. The
device is specified to operate over a very broad VCC
operating range. The device is specified to operate over
the 1.65 V to 5.5 V VCC range. The inputs and outputs
are high impedance when VCC is 0 V. Inputs tolerate
voltages up to 7 V independent of VCC operating voltage.
High IOL Output Drive: ±24 mA at 3 V VCC
Broad VCC Operating Range: 1.65 V to 5.50 V
Power Down High Impedance Inputs/Outputs
Over-Voltage Tolerance Inputs Facilitate 5 V to 3 V
Translation
Ultra-Small MicroPak™ Packages
Ordering Information
Part Number
Top Mark
Package
Packing Method
NC7WZ07P6X
Z07
6-Lead SC70, EIAJ SC88 1.25 mm Wide
3000 Units on Tape & Reel
NC7WZ07L6X
D3
6-Lead MicroPak™, 1.00 mm Wide
5000 Units on Tape & Reel
NC7WZ07FHX
D3
6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
5000 Units on Tape & Reel
Connection Diagrams
IEEE/IEC
Figure 1. Logic Symbol
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
www.fairchildsemi.com
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
April 2013
Figure 2. SC70 (Top View)
Figure 3. MicroPak™ (Top Through View)
Figure 4. Pin 1 Orientation
Notes:
1. AAA represents product code top mark (see Ordering Information).
2. Orientation of top mark determines pin one location.
3. Reading the top mark left to right, pin one is the lower left pin.
Pin Definitions
Pin # SC70
Pin # MicroPak™
Name
Description
1
1
A1
Input
2
2
GND
Ground
3
3
A2
Input
4
4
Y2
Output
5
5
VCC
Supply Voltage
6
6
Y1
Output
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
Pin Configurations
Function Table
Y= A
Inputs
Output
A
Y
LOW Logic Level
LOW Logic Level
HIGH Logic Level
High Impedance Output State, Open Drain
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply Voltage
-0.5
7.0
V
VIN
DC Input Voltage
-0.5
7.0
V
VOUT
7.0
V
IIK
DC Input Diode Current
VIN < -0.5 V
-50
mA
IOK
DC Output Diode Current
VOUT < -0.5 V
-50
mA
IOUT
DC Output Current
±50
mA
DC VCC or Ground Current
±100
mA
+150
°C
+150
°C
+260
°C
ICC or IGND
TSTG
DC Output Voltage
-0.5
Storage Temperature Range
-65
TJ
Junction Temperature Under Bias
TL
Junction Lead Temperature (Soldering, 10 Seconds)
PD
Power Dissipation at +85°C
SC70-6
150
MicroPak™-6
130
MicroPak2™-6
ESD
mW
120
Human Body Model, JEDEC:JESD22-A114
4000
Charge Device Model, JEDEC:JESD22-C101
2000
V
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
Absolute Maximum Ratings
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
VIN
VOUT
Parameter
Min.
Max.
Supply Voltage Operating
1.65
5.50
Supply Voltage Data Retention
1.5
5.5
Input Voltage
0
5.5
V
Output Voltage
0
5.5
V
VCC at 1.8 V, ±0.15 V,
2.5 V ± 0.2 V
0
20
VCC at 3.3 V ±0.3 V
0
10
tr, tf
Input Rise and Fall Times
TA
Operating Temperature
Conditions
VCC at 5.0 V ±0.5 V
JA
Thermal Resistance
0
5
-40
+85
SC70-6
425
MicroPak™-6
500
MicroPak2™-6
560
Unit
V
ns/V
°C
°C/W
Note:
4. Unused inputs must be held HIGH or LOW. They may not float.
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
www.fairchildsemi.com
3
Symbol
Parameter
VCC
TA=+25°C
Conditions
Min.
Typ.
TA=-40 to +85°C
Max.
Min.
VIH
HIGH Level Input
Voltage
1.65 to 1.95
0.75VCC
0.75VCC
2.30 to 5.50
0.70VCC
0.70VCC
VIL
LOW Level Input
Voltage
1.65 to 1.95
0.25VCC
0.25VCC
2.30 to 5.50
0.30VCC
0.30VCC
ILKG
HIGH Level
Output Leakage
Current
±5
±10
1.65 to 5.50
IIN
LOW Level Output
Voltage
Input Leakage
Current
0.00
0.10
0.00
1.80
0.00
0.10
0.10
0.00
0.10
0.10
3.00
0.00
0.10
0.10
4.50
0.00
0.10
0.10
VIN=VIL, IOL=100 µA
V
µA
V
1.65
IOL=4 mA
0.80
0.24
0.24
2.30
IOL=8 mA
0.10
0.30
0.30
3.00
IOL=16 mA
0.16
0.40
0.40
3.00
IOL=24 mA
0.24
0.55
0.55
4.50
IOL=32 mA
0.25
0.55
0.55
±0.1
±1.0
µA
VIN or VOUT=5.5 V
1
10
µA
VIN=5.5 V, GND
1
10
µA
0 to 5.5
IOFF
Power Off
Leakage Current
0
ICC
Quiescent Supply
Current
1.65 to 5.50
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
V
1.65
2.30
VOL
VIN=VIH,
VOUT=VCC or GND
Units
Max.
0 VIN 5.5 V
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
DC Electrical Characteristics
www.fairchildsemi.com
4
Symbol
Parameter
VCC
Conditions
Min.
Typ.
Max.
Min.
Max.
1.8
6.6
11.5
1.8
12.6
1.8
5.5
9.5
1.8
10.5
1.2
3.7
5.8
1.2
6.4
0.8
2.9
4.4
0.8
4.8
5.00 ± 0.50
0.5
2.3
3.5
0.5
3.9
1.65
1.8
5.5
11.5
1.8
12.6
1.8
4.3
9.5
1.8
10.5
1.2
2.8
5.8
1.2
6.4
0.8
2.1
4.4
0.8
4.8
0.5
1.4
3.5
0.5
3.9
1.65
1.80
2.50 ± 0.20
3.30 ± 0.30
tPZL, tPLZ
Propagation Delay
1.80
2.50 ± 0.20
3.30 ± 0.30
CL=50 pF,
RU=500 
RD=500 
VI=2 x VCC
CL=50 pF,
RU=500 
RD=500 
VI=2 x VCC
5.00 ± 0.50
CIN
TA=-40 to
+85°C
TA=+25°C
Input Capacitance
0
2.5
COUT
Output Capacitance
0
4.0
CPD
Power Dissipation
(5)
Capacitance
3.30
3
5.00
4
Units
Figure
ns
Figure 5
Figure 6
pF
pF
Figure 7
Note:
5. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating
current consumption (ICCD) at no output loading and operating at 50% duty cycle. CPD is related to ICCD dynamic
operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic).
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
AC Electrical Characteristics
Notes:
6. CL includes load and stray capacitance.
7. Input PRR = 1.0MHz, tW = 500ns.
Figure 5. AC Test Circuit
Figure 6. AC Waveforms
Note:
8. Input=AC Waveform; tr=tf=1.8ns.
9. PRR=Variable; Duty Cycle=50%.
Figure 7. ICCD Test Circuit
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
www.fairchildsemi.com
5
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
Physical Dimensions
SYMM
C
L
2.00±0.20
0.65
A
0.50 MIN
4
6
B
PIN ONE
1.25±0.10
1
1.90
3
0.30
0.15
(0.25)
0.40 MIN
0.10
0.65
A B
1.30
LAND PATTERN RECOMMENDATION
1.30
1.00
0.80
SEE DETAIL A
1.10
0.80
0.10 C
0.10
0.00
C
2.10±0.30
SEATING
PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE
PLANE
(R0.10)
0.25
0.10
0.20
A) THIS PACKAGE CONFORMS TO EIAJ
SC-88, 1996.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH.
D) DRAWING FILENAME: MKT-MAA06AREV6
30°
0°
0.46
0.26
DETAIL A
SCALE: 60X
Figure 8. 6-Lead, SC70, EIAJ SC88, 1.25 mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Package Designator
P6X
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
Tape Section
Cavity Number
Cavity Status Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
6
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
Physical Dimensions
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
PIN 1 IDENTIFIER
5
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
DETAIL A
1.0
0.10
0.05
0.45
0.35
0.10
0.00 6X
0.25
0.15 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
BOTTOM VIEW
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 9. 6-Lead, MicroPak™, 1.0 mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Package Designator
L6X
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
Tape Section
Cavity Number
Cavity Status Cover Type Status
Leader (Start End)
125 (Typical)
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
7
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
Physical Dimensions
0.89
0.35
0.05 C
1.00
2X
B
A
5X 0.40
PIN 1
MIN 250uM
0.66
1.00
1X 0.45
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.05 C
0.35
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
(0.08) 4X
1
DETAIL A
2
1X 0.57
0.09
0.19 6X
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
5X 0.35
0.25
5
6
4
0.35
0.60
(0.08)
4X
0.10
.05 C
C B A
0.40
0.30
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 10.
0.075X45°
CHAMFER
DETAIL A
PIN 1 LEAD SCALE: 2X
6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Package Designator
FHX
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
Tape Section
Cavity Number
Leader (Start End)
125 (Typical)
Cavity Status Cover Type Status
Empty
Sealed
Carrier
5000
Filled
Sealed
Trailer (Hub End)
75 (Typical)
Empty
Sealed
www.fairchildsemi.com
8
NC7WZ07 — TinyLogic® UHS Dual Buffer (Open-Drain Outputs)
© 2000 Fairchild Semiconductor Corporation
NC7WZ07 • Rev. 1.0.7
www.fairchildsemi.com
9