TOP (TCP/IP Offload Platform)
W3150A Datasheet
(Ver. 1.0.1)
W3150A Datasheet (Ver. 1.0.1)
©2005 WIZnet Co., Inc. All Rights Reserved.
For more information, visit our website at http://www.wiznet.co.kr
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Data
OCT 27, 2005
Ver. 1.0.1
NOV 21, 2005
Description
Release with W3150A Launching
Replace, 1.8V operation Æ 3.3V operation
(p.3)
Change block diagram
(p.4)
Change figure
(p.32)
Replace, g_Sn_TX_BASE Æ g_Sn_RX_BASE
(p.33)
Replace, memcpy( , ,left_size) Æ in memcpy( , ,upper_size)
(p.40, p.41, p.47, p.48, p.49 )
Replace, get_offset = Sn_TX_RR & Æ get_offset = Sn_TX_WR &
(p.41, p.49)
Replace, SOCK_UDP Æ SOCK_IPRAW
(p.51)
W3150A Datasheet (Ver. 1.0.1)
Revision
Ver. 1.0.0
TOP (TCP/IP Offload Platform)
Document History Information
1/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
If you have something to ask about WIZnet Products, Write down your question on Q&A
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Board of ‘Support’ menu in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will
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W3150A Datasheet (Ver. 1.0.1)
Click
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WIZnet’s Online Technical Support
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Description
The W3150A is an LSI of hardware protocol stack that provides an easy, low-cost solution for high-speed
Internet connectivity for digital devices by allowing simple installation of TCP/IP stack in the hardware.
The W3150A offers system designers a quick, easy way to add Ethernet networking functionality to any
standard protocols from the system, thereby significantly reducing the software development cost.
The W3150A contains TCP/IP Protocol Stacks such as TCP, UDP, ICMP, IPv4, ARP and PPPoE protocols, as
well as Ethernet protocols such as Data Link Control and MAC protocol. The total internal memory size is
16Kbytes, which is the buffer for transmit and receive operations.
The W3150A provides a local bus interface to various MCUs and standard MII(Media Independent
Interface) specification consisting of nibble data bus for Ethernet PHY devices.
W3150A Datasheet (Ver. 1.0.1)
product. Implementing this LSI into a system can completely offload Internet connectivity and processing
TOP (TCP/IP Offload Platform)
W3150A Datasheet
The W3150A is a best-fitted device for embedded application with Internet-Connectivity including IPSetop Box, Internet-DVR, Internet phones, VoIP SOC chips, Internet MP3 players, handheld medical devices,
various industrial system monitoring and metering, and many other non-portable electronic devices such
as large consumer electronic products.
Features
Support Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IGMP, IPv4, ARP, PPPoE, Ethernet
Support ADSL connection (with support PPPoE Protocol with PAP/CHAP Authentication mode)
Supports 4 independent sockets simultaneously
No support IP Fragmentation
Standard MII Interface for Ethernet-PHY chip
Supports 10BaseT/100BaseTX
Supports full-duplex mode
Internal 16Kbytes Memory for Tx/Rx Buffers
0.18 µm CMOS technology
3.3V operation with 5V I/O signal tolerance
Small 64 Pin LQFP Package
Lead-Free Package
3/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
TOP (TCP/IP Offload Platform)
Block Diagram
W3150A Datasheet (Ver. 1.0.1)
Figure 1. Block Diagram
T
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Description ................................................................................................................... 3
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Features ...................................................................................................................... 3
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Block Diagram ................................................................................................................ 4
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Table of Contents............................................................................................................ 5
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Pin Assignment ......................................................................................................... 7
1.
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MII Signal Description ..................................................................................... 8
1.1.
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Miscellaneous Signal Description ...................................................................... 10
1.3.
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Power Supply Signal Description ....................................................................... 11
1.4.
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W3150A Registers .................................................................................................... 13
3.
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Memory map.......................................................................................................... 12
2.
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Common Registers ....................................................................................... 13
3.1.
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Socket Registers .......................................................................................... 14
3.2.
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Register Descriptions ................................................................................................ 18
4.
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Common Registers ....................................................................................... 18
4.1.
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Socket Registers .......................................................................................... 24
4.2.
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Functional Description .............................................................................................. 34
5.
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Initialization .............................................................................................. 34
5.1.
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Data communication .................................................................................... 37
5.2.
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5.2.1.
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5.2.2.
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TCP ............................................................................................................ 37
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5.2.3.
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UDP ............................................................................................................ 46
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Direct Bus I/F Mode. .................................................................................... 53
6.1.
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Indirect Bus I/F Mode. .................................................................................. 53
6.2.
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MII (Media Independent Interface) .................................................................... 55
6.3.
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Electrical Specification ............................................................................................. 56
7.
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IP raw ......................................................................................................... 51
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Application Information ............................................................................................ 53
6.
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Absolute Maximum Ratings ............................................................................. 56
7.1.
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DC Characteristics ....................................................................................... 56
7.2.
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AC Characteristics ....................................................................................... 57
7.3.
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7.3.1.
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7.3.2.
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Reset Timing ................................................................................................ 57
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Register/Memory READ Timing ......................................................................... 58
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7.3.3.
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8.
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Register/Memory WRITE Timing........................................................................ 59
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W3150A Datasheet (Ver. 1.0.1)
MCU Interface Signal Description........................................................................ 9
1.2.
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TOP (TCP/IP Offload Platform)
Table of Contents
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MII(Media Independent Interface) Timing ........................................................... 60
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IR Reflow Temperature Profile (Lead-Free) ..................................................................... 62
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
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Package Description ................................................................................................. 63
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TOP (TCP/IP Offload Platform)
9.
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W3150A Datasheet (Ver. 1.0.1)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
TOP (TCP/IP Offload Platform)
/CS
/RD
/WR
/INT
NC
NC
VCC
VOUT
TEST
TXC
GND
TXEN
TXD[3]
TXD[2]
TXD[1]
TXD[0]
1. Pin Assignment
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
48
COL
VCC
2
47
CRS
GND
3
46
RXC
TEST
4
45
GND
A[14]
5
44
RXDV
A[13]
6
43
RXD[3]
A[12]
7
42
RXD[2]
A[11]
8
41
RXD[1]
A[10]
9
40
RXD[0]
A[9]
10
39
VCC
A[8]
11
38
VCC
TEST
12
37
AVIN
GND
13
36
GND
A[7]
14
35
CLOCK
A[6]
15
34
/FDPLX
A[5]
16
33
PLOCK
W3150A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A[4]
A[3]
A[2]
A[1]
A[0]
VCC
GND
D[7]
D[6]
D[5]
D[4]
VIN
D[3]
D[2]
D[1]
D[0]
64 LQFP
W3150A Datasheet (Ver. 1.0.1)
/RESET
7/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Pin#
Signal
I/O
Description
Transmit Clock
55
TXC
I
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN. TXC is sourced by the PHY. TXC is 2.5 MHz in 10BASET Nibble mode,
and 25 MHz in 100BASETX Nibble mode.
Transmit Enable
53
TXEN
O
It becomes active when the first nibble data of the packet is valid on
TXD[3:0] and goes low after the last nibble data of the packet is clocked out
of TXD[3:0]. This signal connects directly to the PHY device. This signal is
active high.
52
TXD[3]
51
TXD[2]
50
TXD[1]
49
TXD[0]
Transmit Data
O
These pins provide Nibble NRZ data to the PHY synchronously with TXC when
TXEN is asserted.
Receive Clock
46
RXC
I
W3150A Datasheet (Ver. 1.0.1)
This output signal indicates the presence of a valid nibble data on TXD[3:0].
TOP (TCP/IP Offload Platform)
1.1. MII Signal Description
This pin provides a continuous clock reference for RXDV and RXD[3:0]
signals. RXC is sourced by the PHY. RXC is 2.5 MHz in 10BASET Nibble mode,
and 25 MHz in 100BASETX Nibble mode.
Collision Detect
48
COL
I
This pin becomes active when a collision has been detected in Half Duplex
modes. This signal is asynchronous, active high and ignored during fullduplex operation. This signal is active high.
47
CRS
I
Carrier Sense
This pin indicates that carrier is present. This signal is active high.
Receive Data Valid
44
RXDV
I
This signal is asserted high when received data is present on the RXD[3:0]
pins; the signal is deasserted at the end of the packet. The signal is valid on
the rising of the RXC.
43
RXD[3]
42
RXD[2]
41
RXD[1]
40
RXD[0]
Receive Data
I
These pins receive Nibble NRZ data from the PHY device synchronously with
RXC when RXDV is asserted.
8/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Pin#
Signal
I/O
Description
RESET
Active Low input that initializes or re-initializes W3150A.
1
/RESET
I
Asserting this pin low for at least 125us will force a reset process to occur
which will result in all internal registers re-initializing to their default
states.
This pin is the Primary clock required for internal operation of W3150A.
25MHz is required. In general, PHY driving clock can be shared for saving
35
CLOCK
cost.
I
Note) Sharing crystal source clock with multiple devices may cause some
troubles. In our reference design, we used one crystal for both PHY and
W3150A with verification.
But for other kind of PHY, please confirm safety prior to decision.
5:11
A[14:8]
14:21
A[7:0]
24:27,
D[7:4]
29:32
D[3:0]
ADDRESS PINS
I
These pins are used to select a register or memory.
I/O
W3150A Datasheet (Ver. 1.0.1)
CLOCK
TOP (TCP/IP Offload Platform)
1.2. MCU Interface Signal Description
DATA PINS
These pins are used to read and write register or memory data.
INTERRUPT
This pin Indicates that W3150A requires MCU attention after socket
61
/INT
O
connecting, disconnecting, receiving data or timeout. The interrupt is
cleared by reading IR(Interrupt Register) or Sn_IR (Socket nth Interrupt
Register). All interrupts are maskable. This signal is active low.
CHIP SELECT
64
/CS
I
Chip Select places for MCU access to internal registers/memory. /WR and
/RD select direction of data transfer. This signal is active low.
WRITE ENABLE
62
/WR
I
Strobe from MCU to write an internal register/memory selected by A[14:0].
Data is latched into the W3150A on the rising edge of this input. This signal
is active low.
READ ENABLE
63
/RD
I
Strobe from MCU to read an internal register/memory selected by A[14:0].
This signal is active low.
9/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Pin#
Signal
I/O
Description
FULL/HALF DUPLEX SELECT
This pin selects Half/Full Duplex operation.
34
/FDPLX
I
This pin must be externally pulled low (typically x kΩ) in order to configure
the W3150A for Full Duplex operation.
Low = Full Duplex
PLL Lock
33
PLOCK
O
Internal PLL Lock detector out. When the lock signal is High, W3150A is
ready to start. The lock signal always low when the PLL is in setting time.
This signal is active high.
4,12,56,
59,60
FACTORY TEST INPUT
TEST
I
Used to check the chip's internal functions. This should be tied low during
normal operation.
W3150A Datasheet (Ver. 1.0.1)
High = Half Duplex
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1.3. Miscellaneous Signal Description
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Pin#
Signal
2, 22, 38, 39, 58
VCC
28
VIN
I/O
Description
POSITIVE 3.3V SUPPLY PINS
1.8V power input
1.8V power supply
1.8V Analog power input
1.8V power supply for analog circuit ; should be well
AVIN
decoupled.
Refer Figure 1-1. Reference Schematic for Power input.
1.8V power out
57
Be sure to connect 10uF tantalum capacitor and a 0.1uF
VOUT
capacitor for noise de-coupling. Then connect this pin through
a ferrite bead to VIN and AVIN.
3, 13, 23, 36, 45, 54
GND
NEGATIVE (GROUND) SUPPLY PINS
VIN
W3150A Datasheet (Ver. 1.0.1)
37
TOP (TCP/IP Offload Platform)
1.4. Power Supply Signal Description
L3
VOUT
CP2
AVIN
C21
+
4.7uH
CP3
C22
+
10uF
0.1uF
0.1uF
2.2uF
Figure 1-1. Reference Schematic for Power input
11/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
W3150A is composed of Common Register, Socket Register, TX Memory, and RX Memory. Each fields are
shown as below.
0x0000
Common Registers
0x0030
Not Used
Socket Registers
0x0800
Not Used
W3150A Datasheet (Ver. 1.0.1)
0x0400
TOP (TCP/IP Offload Platform)
2. Memory map
0x4000
TX memory
0x6000
RX memory
0x8000
12/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
3.1. Common Registers
Address
Register
Address
Register
0x0000
Mode (MR)
0x001A
RX Memory Size (RMSR)
Gateway Address
0x001B
TX Memory Size (TMSR)
(GAR0)
0x0002
(GAR1)
0x001C
(PATR0)
0x0003
(GAR2)
0x001D
(PATR1)
0x0004
(GAR3)
0x001E
Subnet mask Address
~
0x0005
(SUBR0)
0x0027
0x0006
(SUBR1)
0x0028
PPP LCP Request Timer (PTIMER)
0x0007
(SUBR2)
0x0029
PPP LCP Magic number (PMAGIC)
0x0008
(SUBR3)
Authentication Type in PPPoE
Reserved
Unreachable IP Address
Source Hardware Address
0x002A
(UIPR0)
0x0009
(SHAR0)
0x002B
(UIPR1)
0x000A
(SHAR1)
0x002C
(UIPR2)
0x000B
(SHAR2)
0x002D
(UIPR3)
0x000C
(SHAR3)
0x000D
(SHAR4)
0x002E
(UPORT0)
0x000E
(SHAR5)
0x002F
(UPORT1)
Source IP Address
0x0030
0x000F
(SIPR0)
~
0x0010
(SIPR1)
0x03FF
0x0011
(SIPR2)
0x0012
(SIPR3)
0x0013
Reserved
W3150A Datasheet (Ver. 1.0.1)
0x0001
TOP (TCP/IP Offload Platform)
3. W3150A Registers
Unreachable Port
Reserved
0x0014
0x0015
Interrupt (IR)
0x0016
Interrupt Mask (IMR)
Retry Time
0x0017
(RTR0)
0x0018
(RTR1)
0x0019
Retry Count (RCR)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Address
Register
Address
Register
0x0400
Socket 0 Mode (S0_MR)
0x0415
Socket 0 IP TOS (S0_TOS)
0x0401
Socket 0 Command (S0_CR)
0x0416
Socket 0 IP TTL (S0_TTL)
0x0402
Socket 0 Interrupt (S0_IR)
0x0417
0x0403
Socket 0 Socket Status (S0_SSR)
Reserved
0x041F
Socket 0 TX Free Size
0x0404
(S0_PORT0)
0x0405
(S0_PORT1)
0x0420
(S0_TX_FSR0)
Socket 0 Destination Hardware Address
0x0421
(S0_TX_FSR1)
Socket 0 TX Read Pointer
0x0406
(S0_DHAR0)
0x0407
(S0_DHAR1)
0x0422
(S0_TX_RD0)
0x0408
(S0_DHAR2)
0x0423
(S0_TX_RD1)
0x0409
(S0_DHAR3)
0x040A
(S0_DHAR4)
0x0424
(S0_TX_WR0)
0x040B
(S0_DHAR5)
0x0425
(S0_TX_WR1)
Socket 0 TX Write Pointer
Socket 0 Destination IP Address
Socket 0 RX Received Size
0x040C
(S0_DIPR0)
0x0426
(S0_RX_RSR0)
0x040D
(S0_DIPR1)
0x0427
(S0_RX_RSR0)
0x040E
(S0_DIPR2)
0x040F
(S0_DIPR3)
0x0428
(S0_RX_RR0)
Socket 0 Destination Port
0x0429
(S0_RX_RR1)
0x0410
(S0_DPORT0)
0x042A
Reserved
0x0411
(S0_DPORT1)
0x042B
Socket 0 Maximum Segment Size
0x042C
0x0412
(S0_MSSR0)
0x0413
(S0_MSSR1)
W3150A Datasheet (Ver. 1.0.1)
Socket 0 Source Port
~
TOP (TCP/IP Offload Platform)
3.2. Socket Registers
Socket 0 RX Read Pointer
~
Reserved
0x04FF
Socket 0 Protocol in IP Raw mode
0x0414
(S0_PROTO)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Register
Address
Register
0x0500
Socket 1 Mode (S1_MR)
0x0515
Socket 1 IP TOS (S1_TOS)
0x0501
Socket 1 Command (S1_CR)
0x0516
Socket 1 IP TTL (S1_TTL)
0x0502
Socket 1 Interrupt (S1_IR)
0x0517
0x0503
Socket 1 Socket Status (S1_SSR)
Socket 1 Source Port
~
Reserved
0x051F
Socket 1 TX Free Size
(S1_PORT0)
0x0505
(S1_PORT1)
0x0520
(S1_TX_FSR0)
Socket 1 Destination Hardware Address
0x0521
(S1_TX_FSR1)
Socket 1 TX Read Pointer
(S1_DHAR0)
0x0506
(S1_DHAR1)
0x0522
(S1_TX_RD0)
0x0507
(S1_DHAR2)
0x0523
(S1_TX_RD1)
0x0508
(S1_DHAR3)
0x0509
(S1_DHAR4)
0x0524
(S1_TX_WR0)
0x050A
(S1_DHAR5)
0x0525
(S1_TX_WR1)
Socket 1 TX Write Pointer
0x050B
Socket 1 RX Received Size
Socket 1 Destination IP Address
0x0526
(S1_RX_RSR0)
0x050C
(S1_DIPR0)
0x0527
(S1_RX_RSR0)
0x050D
(S1_DIPR1)
0x050E
(S1_DIPR2)
0x0528
(S1_RX_RR0)
0x050F
(S1_DIPR3)
0x0529
(S1_RX_RR1)
Socket 1 Destination Port
0x052A
Reserved
0x0510
(S1_DPORT0)
0x052B
0x0511
(S1_DPORT1)
0x052C
Socket 1 RX Read Pointer
Socket 1 Maximum Segment Size
0x0512
(S1_MSSR0)
0x0513
(S1_MSSR1)
W3150A Datasheet (Ver. 1.0.1)
0x0504
TOP (TCP/IP Offload Platform)
Address
~
Reserved
0x05FF
Socket 1 Protocol in IP Raw mode
0x0514
(S1_PROTO)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Register
Address
Register
0x0600
Socket 2 Mode (S2_MR)
0x0615
Socket 2 IP TOS (S2_TOS)
0x0601
Socket 2 Command (S2_CR)
0x0616
Socket 2 IP TTL (S2_TTL)
0x0602
Socket 2 Interrupt (S2_IR)
0x0617
0x0603
Socket 2 Socket Status (S2_SSR)
Socket 2 Source Port
~
Reserved
0x061F
Socket 2 TX Free Size
(S2_PORT0)
0x0605
(S2_PORT1)
0x0620
(S2_TX_FSR0)
Socket 2 Destination Hardware Address
0x0621
(S2_TX_FSR1)
Socket 2 TX Read Pointer
(S2_DHAR0)
0x0606
(S2_DHAR1)
0x0622
(S2_TX_RD0)
0x0607
(S2_DHAR2)
0x0623
(S2_TX_RD1)
0x0608
(S2_DHAR3)
0x0609
(S2_DHAR4)
0x0624
(S2_TX_WR0)
0x060A
(S2_DHAR5)
0x0625
(S2_TX_WR1)
Socket 2 TX Write Pointer
0x060B
Socket 2 RX Received Size
Socket 2 Destination IP Address
0x0626
(S2_RX_RSR0)
0x060C
(S2_DIPR0)
0x0627
(S2_RX_RSR0)
0x060D
(S2_DIPR1)
0x060E
(S2_DIPR2)
0x0628
(S2_RX_RR0)
0x060F
(S2_DIPR3)
0x0629
(S2_RX_RR1)
Socket 2 Destination Port
0x062A
Reserved
0x0610
(S2_DPORT0)
0x062B
0x0611
(S2_DPORT1)
0x062C
Socket 2 RX Read Pointer
Socket 2 Maximum Segment Size
0x0612
(S2_MSSR0)
0x0613
(S2_MSSR1)
W3150A Datasheet (Ver. 1.0.1)
0x0604
TOP (TCP/IP Offload Platform)
Address
~
Reserved
0x06FF
Socket 2 Protocol in IP Raw mode
0x0614
(S2_PROTO)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Register
Address
Register
0x0700
Socket 3 Mode (S3_MR)
0x0715
Socket 3 IP TOS (S3_TOS)
0x0701
Socket 3 Command (S3_CR)
0x0716
Socket 3 IP TTL (S3_TTL)
0x0702
Socket 3 Interrupt (S3_IR)
0x0717
0x0703
Socket 3 Socket Status (S3_SSR)
Socket 3 Source Port
~
Reserved
0x071F
Socket 3 TX Free Size
(S3_PORT0)
0x0705
(S3_PORT1)
0x0720
(S3_TX_FSR0)
Socket 3 Destination Hardware Address
0x0721
(S3_TX_FSR1)
Socket 3 TX Read Pointer
(S3_DHAR0)
0x0706
(S3_DHAR1)
0x0722
(S3_TX_RD0)
0x0707
(S3_DHAR2)
0x0723
(S3_TX_RD1)
0x0708
(S3_DHAR3)
0x0709
(S3_DHAR4)
0x0724
(S3_TX_WR0)
0x070A
(S3_DHAR5)
0x0725
(S3_TX_WR1)
Socket 3 TX Write Pointer
0x070B
Socket 3 RX Received Size
Socket 3 Destination IP Address
0x0726
(S3_RX_RSR0)
0x070C
(S3_DIPR0)
0x0727
(S3_RX_RSR0)
0x070D
(S3_DIPR1)
0x070E
(S3_DIPR2)
0x0728
(S3_RX_RR0)
0x070F
(S3_DIPR3)
0x0729
(S3_RX_RR1)
Socket 3 Destination Port
0x072A
Reserved
0x0710
(S3_DPORT0)
0x072B
0x0711
(S3_DPORT1)
0x072C
Socket 3 RX Read Pointer
Socket 3 Maximum Segment Size
0x0712
(S3_MSSR0)
0x0713
(S3_MSSR1)
W3150A Datasheet (Ver. 1.0.1)
0x0704
TOP (TCP/IP Offload Platform)
Address
~
Reserved
0x07FF
Socket 3 Protocol in IP Raw mode
0x0714
(S3_PROTO)
17/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
4.1. Common Registers
MR (Mode Register) [R/W] [0x0000] [0x00]1
TP
PT
This Register is used for S/W Reset, memory test mode, ping block mode, PPPoE mode and Indirect bus I/F.
7
6
Bit
4
3
2
1
0
MT
PB
PPPoE
LB
AI
IND
Symbol
Description
S/W Reset
7
RST
If this bit is ‘1’, internal register will be initialized. It will be automatically cleared
with Reset.
6
Reserved
Reserved
Memory Test Mode
0 : Disable memory test mode
W3150A Datasheet (Ver. 1.0.1)
RST
5
TOP (TCP/IP Offload Platform)
4. Register Descriptions
1 : Enable memory test mode
TX memory is used for data transmission. In this memory, only WRITE can be
5
MT
performed. At the RX memory, users can receive data and only READ can be performed.
If a user wants to perform both of WRITE and READ in order to check operation status
of TX memory and RX memory, the bit should be set as ‘1’. Memory Test Mode is used
only for checking of TX/RX memory operation status. For the general usage, Memory
Test Mode should be cleared first.
Ping Block Mode
4
PB
0 : Disable Ping block
1 : Enable Ping block
If the bit is set as ‘1’, there is no response to the Ping request.
PPPoE Mode
0 : Disable PPPoE mode
1 : Enable PPPoE mode
3
PPPoE
If you are under the circumstance of ADSL without router or etc. you should set the bit
as ‘1’, and connect to ADSL SERVER. For more detail, refer to the application note,
“How to connect ADSL”.
1
TP
PT
[Read/Write] [Address] [Reset value]
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
0 : Big-endian ordering
2
LB
1 : Little-endian ordering
At the Indirect Bus I/F mode, Indirect address Register ordering is decided. For more
detail, refer to 6.1.2.Indirect Bus IF Mode.
Address Auto-Increment in Indirect Bus I/F
0 : Disable auto-increment
AI
1 : Enable auto-increment
At the Indirect Bus I/F mode, if this bit is set as ‘1’, the address will automatically
increase by 1 whenever Read and Write are performed. For more detail, refer to 6.1.2
Indirect Bus IF Mode.
Indirect Bus I/F mode
0 : Disable Indirect bus I/F mode
0
IND
1 : Enable Indirect bus I/F mode
If this bit is set as ‘1’, Indirect Bis I/F mode is used. For more detail, refer to 6.
Application Information, 6.1.2. Indirect Bus IF Mode.
GWR (Gateway IP Address Register) [R/W] [0x0001 – 0x0004] [0x00]
W3150A Datasheet (Ver. 1.0.1)
1
TOP (TCP/IP Offload Platform)
Little-endian / Big-endian ordering in Indirect Bus I/F
This Register sets up the default gateway address.
Ex) in case of “192.168.0.1”
0x0001
0x0002
0x0003
0x0004
192 (0xC0)
168 (0xA8)
0 (0x00)
1 (0x01)
SUBR (Subnet Mask Register) [R/W] [0x0005 – 0x0008] [0x00]
This Register sets up the subnet mask address.
Ex) in case of “255.255.255.0”
0x0005
0x0006
0x0007
0x0008
255 (0xFF)
255 (0xFF)
255 (0xFF)
0 (0x00)
SHAR (Source Hardware Address Register) [R/W] [0x0009 – 0x000E] [0x00]
This Register sets up the Source Hardware address.
Ex) In case of “00.08.DC.01.02.03”
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x00
0x08
0xDC
0x01
0x02
0x03
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
TOP (TCP/IP Offload Platform)
SIPR (Source IP Address Register) [R/W] [0x000F – 0x0012] [0x00]
This Register sets up the Source IP address.
Ex) in case of “192.168.0.3”
0x000F
0x0010
0x0011
0x0012
192 (0xC0)
168 (0xA8)
0 (0x00)
3 (0x03)
IR (Interrupt Register) [R] [0x0015] [0x00]
This Register is accessed by the host processor to know the cause of an interrupt.
unmasked signal is set, and will not go high until all unmasked bits in this Register have been cleared.
7
6
5
4
3
2
1
0
CONFLICT
UNREACH
PPPoE
Reserved
S3_INT
S2_INT
S1_INT
S0_INT
Bit
Symbol
Description
IP Conflict
7
CONFLICT
It is set as ‘1’, when there is ARP request with same IP address as Source IP address.
W3150A Datasheet (Ver. 1.0.1)
Any interrupt can be masked in the Interrupt Mask Register (IMR). The /INT signal retain low as long as any
This bit is cleared to ‘0’ only with Read action.
Destination unreachable
W3150A will receive ICMP(Destination Unreachable) packet if not-existing Destination IP
6
UNREACH
address is transmitted during UDP data transmission. (Refer to 5.2.2. UDP). In this case,
the IP address and Port number will be saved in Unreachable IP Address (UIPR) and
Unreachable Port Register (UPORT), and the bit will be set as ‘1’. This bit will be
cleared to ‘0’ only with Read action.
PPPoE Close
5
PPPoE
In the PPPoE Mode, if the PPPoE connection is closed, ‘1’ is set. This bit will be cleared
to ‘0’ only with Read action.
4
Reserved
Reserved
Occurrence of Socket 3 Socket Interrupt
3
S3_INT
It is set in case that interrupt occurs at the socket 3. For more detailed information of
socket interrupt, refer to “Socket 3 Interrupt Register(S3_IR). This bit will be
automatically cleared when S3_IR is cleared to 0x00.
Occurrence of Socket 2 Socket Interrupt
2
S2_INT
It is set in case that interrupt occurs at the socket 2. For more detailed information of
socket interrupt, refer to “Socket 2 Interrupt Register(S2_IR). This bit will be
automatically cleared when S2_IR is cleared to 0x00.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
It is set in case that interrupt occurs at the socket 1. For more detailed information of
S1_INT
1
socket interrupt, refer to “Socket 1 Interrupt Register(S1_IR). This bit will be
automatically cleared when S1_IR is cleared to 0x00.
Occurrence of Socket 0 Socket Interrupt
0
It is set in case that interrupt occurs at the socket 0. For more detailed information of
S0_INT
socket interrupt, refer to “Socket 0 Interrupt Register(S0_IR). This bit will be
automatically cleared when S0_IR is cleared to 0x00.
The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the
Interrupt Register (IR). If an interrupt mask bit is set, an interrupt will be issued whenever the
corresponding bit in the IR is set. If any bit in the IMR is set as ‘0’, an interrupt will not occur though the
bit in the IR is set.
7
6
5
4
3
2
1
0
IM_IR7
IM_IR6
IM_IR5
Reserved
IM_IR3
IM_IR2
IM_IR1
IM_IR0
Bit
Symbol
7
IM_IR7
IP Conflict Enable
6
IM_IR6
Destination unreachable Enable
5
IM_IR5
PPPoE Close Enable
4
Reserved
3
IM_IR3
Occurrence of Socket 3 Socket Interrupt Enable
2
IM_IR2
Occurrence of Socket 2 Socket Interrupt Enable
1
IM_IR1
Occurrence of Socket 1 Socket Interrupt Enable
0
IM_IR0
Occurrence of Socket 0 Socket Interrupt Enable
W3150A Datasheet (Ver. 1.0.1)
IMR (Interrupt Mask Register) [R/W] [0x0016] [0x00]
TOP (TCP/IP Offload Platform)
Occurrence of Socket 1 Socket Interrupt
Description
It should be set as ‘0’
RTR (Retry Time-value Register) [R/W] [0x0017 – 0x0018] [0x07D0]
This register sets the period of timeout. Vaule 1 means 100us. The initial value is 2000(0x07D0). That will
be set as 200ms.
Ex) For 400ms configuration, set as 4000(0x0FA0)
0x0017
0x0018
0x0F
0xA0
Re-transmission will occur when there is no response from the remote peer to the commands of CONNECT,
DISCON, CLOSE, SEND, SEND_MAC and SEND_KEEP, or the response is delayed.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
This register sets the number of re-transmission. If retransmission occurs more than recorded number,
Timeout Interrupt (TIMEOUT bit of Socket n Interrupt Register (Sn_IR) is set as ‘1’) will occur.
RMSR(RX Memory Size Register) [R/W] [0x001A] [0x55]
This register assigns total 8K RX Memory to the socket.
7
6
5
S1
3
Socket 2
S0
S1
2
1
Socket 1
S0
S1
0
Socket 0
S0
S1
S0
The memory size according to the configuration of S1, S0, is as below.
S1
S0
Memory size
0
0
1KB
0
1
2KB
1
0
4KB
1
1
8KB
W3150A Datasheet (Ver. 1.0.1)
Socket 3
4
TOP (TCP/IP Offload Platform)
RCR (Retry Count Register) [R/W] [0x0019] [0x08]
Accoridng to the value of S1 and S0, the memory is assigned to the sockets from socket 0 within the range
of 8KB. If there is not enough memory to be assigned, the socket should not be used. The initial value is
0x55 and the memory is assined to 4 sockets respectively with 2K.
Ex) When setting as 0xAA, the memory should be assigned to each socket with 4KB.
However, the total memory size is 8KB. The memory is normally assigned to the socket 0 and 1, but not to
the socket 2 and 3. Therefore, user should not use socket 2 and 3 absolutely.
Socket 3
Socket 2
Socket 1
Socket 0
0KB
0KB
4KB
4KB
TMSR(TX Memory Size Register) [R/W] [0x001B] [0x55]
This register is used in assigning total 8K TX Memory to sockets. Configuration can be done in the same
way of RX Memory Size Register (RMSR). The initial value is 0x55 and assined to 4 socketes respectively
with 2K.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
This register notifies authentication method that has been agreed at the connection with PPPoE Server.
W3150A supports only two ways of PAP and CHAP.
Value
Authentication Type
0xC023
PAP
0xC223
CHAP
PTIMER (PPP LCP Request Timer Register) [R/W] [0x0028] [0x28]
Ex) in case that PTIMER is 200,
200 * 25(ms) = 5000(ms) = 5 seconds
PMAGIC (PPP LCP Magic number Register) [R/W] [0x0029] [0x00]
This register is used in Magic number option during LCP negotiation. Refer to the application note, “How
to connect ADSL”.
UIPR (Unreachable IP Address Register) [R] [0x002A – 0x002D] [0x00]
In case of data transmission by using UDP (refer to 5.2.2. UDP), if transmitting to not-existing IP address,
W3150A Datasheet (Ver. 1.0.1)
This register indicates the duration for sending LCP Echo Request. Vaule 1 is about 25ms.
TOP (TCP/IP Offload Platform)
PATR (Authentication Type in PPPoE mode) [R] [0x001C-0x001D] [0x0000]
ICMP (Destination Unreachable) packet will be received. In this case, that IP address and Port number will
be respectively saved in the Unreachable IP Address Register(UIPR) and Unreachable Port Register(UPORT).
Ex) in case of “192.168.0.11”,
0x002A
0x002B
0x002C
0x002D
192 (0xC0)
168 (0xA8)
0 (0x00)
11 (0x0B)
UPORT (Unreachable Port Register) [R] [0x002E – 0x002F] [0x0000]
Refer to Unreachable IP Address Register (UIPR)
Ex) In case of 5000(0x1388),
0x002E
0x002F
0x13
0x88
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Sn2_MR (Socket n Mode Register) [R/W] [0x0400, 0x0500, 0x0600, 0x0700] [0x00]3
TP
PT
TP
PT
This Register sets up socket option or protocol of the corresponding Socket.
7
6
MULTI
Bit
5
4
3
2
1
0
MC
ZC
P3
P2
P1
P0
Symbol
Description
0 : disable Multicasting
1 : enable Multicasting
7
MULTI
It is applied only in case of UDP.
For using multicasting, write multicast group address to Socket n Destination IP and
multicast group port number to Socket n Destination Port Register, before OPEN
command.
6
Reserved
Reserved
Multicast
5
MC
W3150A Datasheet (Ver. 1.0.1)
Multicasting
TOP (TCP/IP Offload Platform)
4.2. Socket Registers
0 : using IGMP version 2
1 : using IGMP version 1
It is applied only in case of MULTI is ‘1’
Zero Chksum Enable
0 : disable Zero Chksum
4
ZC
1 : enable Zero Chksum
It is applied only in case of UDP. If this bit is set as ‘1’, checksum field of transmitting
packet is 0x00.
Protocol
3
2
1
2
TP
PT
3
TP
PT
P3
P2
P1
Sets up corresponding Socket as TCP, UDP, IP RAW mode
P3
P2
P1
P0
Meaning
0
0
0
0
Closed
0
0
0
1
TCP
0
0
1
0
UDP
0
0
1
1
IPRAW
n is socket number (0, 1, 2, 3).
[Read/Write] [address of socket 0, address of socket 1, address of socket 2, address of socket 3] [Reset value]
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
0
P0
P3
P2
P1
P0
Meaning
0
1
0
0
MACRAW
0
1
0
1
PPPoE
Sn_CR (Socket n Command Register) [R/W] [0x0401, 0x0501, 0x0601, 0x0701] [0x00]
This register utilized for socket initialization, close, connection establishiment, connection termination,
data transmitting and receiving commands. After performing the commands, the register value will be
Value
Symbol
Description
It is used to initialize the socket. According to the vaule of Socket n Mode
0x01
OPEN
Register(Sn_MR), Socket n Status Register(Sn_SSR) value is changed to SOCK_INIT,
SOCK_UDP, SOCK_IPRAW.
For more detail, refer to 5. Functional Description.
It is only used in TCP mode.
0x02
LISTEN
It changes the value of Socket n Status Register(Sn_SSR) to SOCK_LISTEN in order
to wait for a connection request from any remote peer (Client).
W3150A Datasheet (Ver. 1.0.1)
automatically cleared to 0x00.
TOP (TCP/IP Offload Platform)
* In case of socket 0, MACRAW and PPPoE mode exist.
For more detail, refer to 5.2.1.1. SERVER.
It is only used in TCP mode.
0x04
CONNECT
It sends a connection request to remote peer(SERVER). If the connection is failed,
Timeout interrupt will occur.
For more detail, refer to 5.2.1.2. CLIENT.
It is only used in TCP mode.
It sends connection termination request. If connection termination is failed,
0x08
DISCON
Timeout interrupt will occur. For more detail, refert to 5.2.1.1. SERVER.
* In case of using CLOSE command instead of DISCON, only the value of Socket n
Status Register(Sn_SSR) is changed to SOCK_CLOSED without the connection
termination process.
0x10
CLOSE
It is used to close the socket. It changes the vaule of Socket n Status
Register(Sn_SSR) to SOCK_CLOSED.
It transmits the data as much as the increased size of Socket n TX Write Pointer.
0x20
SEND
For more detail, refert to Socket n TX Free Size Register (Sn_TX_FSR), Socket n TX
Write
Pointer
Register(Sn_TX_WR),
and
Socket
n
TX
Read
Pointer
Register(Sn_TX_RR) or 5.2.1.1. SERVER.
0x21
SEND_MAC
It is used in UDP mode.
The basic operation is same as SEND. Normally SEND operation is needed
25/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Protocol)
process.
But
SEND_MAC
uses
Socket
ARP(Address Resolution
n
Destination
Hardware
Address(Sn_DHAR) that is written by users without ARP process.
It is only used in TCP mode.
0x22
SEND_KEEP
It checks the connection by sending 1byte data previously. If the connection is
already terminated or Peer has no response, Timeout interrupt will occur.
Receiving is processed including the value of Socket n RX Read Pointer
Register(Sn_RX_RR).
RECV
For more detail, refer to Socket n RX Received Size Register (Sn_RX_RSR), Socket
n RX Write Pointer Register(Sn_RX_WR), and Socket n RX Read Pointer
Register(Sn_RX_RR) or 5.2.1.1. SERVER
Sn_IR (Socket n Interrupt Register) [R] [0x0402, 0x0502, 0x0602, 0x0702] [0x00]
This register is used for notifying connection establishment and termination, receiving data and Timeout.
The values are cleared by reading this register. Howerver, it takes 2ms to clear register after reading
internally, and you may wait about 2ms after reading this register.
7
6
Reserved
Bit
Reserved
5
Reserved
4
Reserved
3
TIMEOUT
Symbol
2
RECV
1
DISCON
0
CON
Description
7
Reserved
Reserved
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
TIMEOUT
It is set as ‘1’ if Timeout occurs during connection establishment or termination
3
2
1
0
W3150A Datasheet (Ver. 1.0.1)
0x40
TOP (TCP/IP Offload Platform)
Destination Hardware Address that is received in
and data transmission.
RECV
It is set as ‘1’ if data is received.
DISCON
It is set as ‘1’ if receive connection termination request or if connection
termination is finished.
CON
It is set as ‘1’ if connection is established.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
This register has the status vaule of socket. The main status is shown in the below diagram.
TOP (TCP/IP Offload Platform)
Sn_SR (Socket n Status Register) [R] [0x0403, 0x0503, 0x0603, 0x0703] [0x00]
W3150A Datasheet (Ver. 1.0.1)
Value
0x00
Symbol
Description
SOCK_CLOSED
In case that OPEN commands are given to Sn_CR, Timeout interrupt is
asserted or connection is terminated.
0x13
SOCK_INIT
In case that Sn_MR is set as TCP and OPEN commands are given to
Sn_CR.
0x14
SOCK_LISTEN
In case that under the SOCK_INIT status, LISTEN commands are given to
Sn_CR.
0x17
SOCK_ESTABLISHED
In case that connection is established.
0x1C
SOCK_CLOSE_WAIT
In case that connection termination request is received.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
SOCK_UDP
In case that OPEN commands are given to Sn_CR when Sn_MR is set as
UDP.
0x32
SOCK_IPRAW
In case that OPEN commands are given to Sn_CR when Sn_MR is set as
IPRAW.
0x42
SOCK_MACRAW
In case that OPEN commands are given to S0_CR when S0_MR is set as
MACRAW.
0x5F
SOCK_PPPOE
In case that OPEN commands are given to S0_CR when S0_MR is set as
PPPoE.
Value
0x15
Symbol
SOCK_SYNSENT
Description
It is shown in case that CONNECT commands are given to Socket n
Command Register(Sn_CR) at the SOCK_INIT status. It is automatically
changed to SOCK_ESTABLISH when the connection is established.
0x16
SOCK_SYNRECV
It is shown in case that connection request is received from remote
peer(CLIENT). It normally responds to the requests and changes to
SOCK_ESTABLISH.
0x18
SOCK_FIN_WAIT
0x1A
SOCK_CLOSING
0X1B
SOCK_TIME_WAIT
0X1D
SOCK_LAST_ACK
0x11
SOCK_ARP
W3150A Datasheet (Ver. 1.0.1)
Below is shown in the status change, and does not need much attention.
TOP (TCP/IP Offload Platform)
0x22
It is shown in the process of connection termination. If the termination
is
normally
processed
or
Timeout
interrupt
is
asserted
then
automatically changed to SOCK_CLOSED.
It is shown when ARP Request is sent in order to acquire Hardware
0x21
Address of remote peer when it sends connection request in TCP mode
0x31
or sends data in UDP mode. If ARP Reply is received, it changes to the
status, SOCK_SYNSENT, SOCK_UDP or SOCK_ICMP, for next operation.
Sn_PORT (Socket n Source Port Register) [R/W] [0x0404–0x0405, 0x0504–0x0505, 0x0604–0x0605,
0x0704–0x0705] [0x00]
This Register sets the Source Port number for each Socket when using TCP or UDP mode, and the set-up
needs to be made before executing the OPEN Command.
Ex) In case of Socket 0 Port = 5000(0x1388), configure as below,
0x0404
0x0405
0x13
0x88
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
0x0606–0x060B, 0x0706–0x070B] [0x00]
This Register sets the Destination Hardware address of each Socket.
Ex) In case of Socket 0 Hardware address = 08.DC.00.01.02.10, configuration is as below,
0x0406
0x0407
0x0408
0x0409
0x040A
0x040B
0x08
0xDC
0x00
0x01
0x02
0x0A
Sn_DIPR (Socket n Destination IP Address Register) [R/W] [0x040C–0x040F, 0x050C–0x050F, 0x060C–
This Register sets the Destination IP Address of each Socket to be used in setting the TCP connection. In
active mode, IP address needs to be set before executing the Connect command.
In passive mode,
W3150A sets up the connection and then updates with peer IP internally.
Ex) In case of Socket 0 Destination IP address = 192.168.0.11, configure as below.
0x040C
0x040D
0x040E
0x040F
192 (0xC0)
168 (0xA8)
0 (0x00)
11 (0x0B)
Sn_DPORT (Socket n Destination Port Register) [R/W] [0x0410–0x0411, 0x0510–0x0511, 0x0610–
0x0611, 0x0710–0x0711] [0x00]
W3150A Datasheet (Ver. 1.0.1)
0x060F, 0x070C–0x070F] [0x00]
TOP (TCP/IP Offload Platform)
Sn_DHAR (Socket n Destination Hardware Address Register) [R/W] [0x0406–0x040B, 0x0506–0x050B,
This Register sets the Destination Port number of each Socket to be used in setting the TCP connection.
In active mode, port number needs to be set before executing the Connect command. In passive mode,
W3150A sets up the connection and then updates with peer port number internally.
Ex) In case of Socket 0 Destination Port = 5000(0x1388), configure as below,
0x0410
0x0411
0x13
0x88
Sn_MSS (Socket n Maximum Segment Size Register) [R/W] [0x0412-0x0413, 0x0512-0x0513, 0x06120x0613, 0x0712-0x0713] [0x00]
This Register is used for MSS (Maximum Segment Size) of TCP, and the Register displays MSS set by the
other party when TCP is activated in Passive Mode.
Ex) In case of Socket 0 MSS = 1460(0x05B4), configure as below,
0x0412
0x0413
0x05
0xB4
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
This IP Protocol Register is used to be set up the Protocol Field of IP Header when executing the IP Layer
RAW Mode. There are several protocol numbers defined in advance by registering to IANA. For the overall
list of upper level protocol idenentification number that IP is using, refer to online documents of IANA
(http://www.iana.org/assignments/protocol-numbers).
Ex) Internet Control Message Protocol (ICMP) = 0x01, Internet Group Management Protocol = 0x02
Sn_TOS (Socket n IP Type Of Service Register) [R/W] [0x0415,0x0515,0x0615,0x0715] [0x00]
Sn_TTL (Socket n IP Time To Live Register) [R/W] [0x0416,0x0516,0x0616,0x0716] [0x80]
This Register sets up at the TTL Field of IP Header.
Sn_TX_FSR (Socket n TX Free Size Register) [R] [0x0420-0x0421, 0x0520-0x0521, 0x0620-0x0621,
0x0720-0x0721] [0x0800]
This regiser notifies the information of data size that user can transmit. For data transmission, user should
check this value first and control the size of transmitting data. When checking this register, user should
read upper byte(0x0420,0x0520,0x0620,0x0720) first and lower byte(0x0421,0x0521,0x0621,0x0721) later
W3150A Datasheet (Ver. 1.0.1)
This Register sets up at the TOS Field of IP Header.
TOP (TCP/IP Offload Platform)
Sn_PROTO (Socket n IP Protocol Register) [R/W] [0x0414, 0x0514, 0x0614, 0x0714] [0x00]
to get the correct value.
Ex) In case of 2048(0x0800) in S0_TX_FSR,
0x0420
0x0421
0x08
0x00
Total size can be decided according to the value of TX Memory Size Regster. In the process of transmission,
it reduces by the size of transmitting data, and automatically increases after transimission finished.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
0x0722-0x0723] [0x0000]
This register shows the addres that transmission is finished at the TX Memory. With the SEND command of
Socket n Command Register, it transmits data from current Sn_TX_RR to Sn_TX_WR and automatically
changes after transmission is finished. Therefore, after transmission is finished, Sn_TX_RR and Sn_TX_WR
will have same value. When reading this register, user should read upper byte (0x0422, 0x0522, 0x0622,
0x0722) first and lower byte (0x0423, 0x0523, 0x0623, 0x0723) later to get the correct value.
0x0625, 0x0724-0x0725] [0x0000]
This register offers the location information to write the transmission data. When reading this register,
user should read upper byte (0x0424, 0x0524, 0x0624, 0x0724) first and lower byte (0x0425, 0x0525,
0x0625, 0x0725) later to get the correct value.
Ex) In case of 2048(0x0800) in S0_TX_WR,
0x0424
0x0425
0x08
0x00
But this value itself is not the physical address to write. So, the physical address should be calculated as
follow.
W3150A Datasheet (Ver. 1.0.1)
Sn_TX_WR (Socket n TX Write Pointer Register) [R/W] [0x0424-0x0425, 0x0524-0x0525, 0x0624-
TOP (TCP/IP Offload Platform)
Sn_TX_RR (Socket n TX Read Pointer Register) [R] [0x0422-0x0423, 0x0522-0x0523, 0x0622-0x0623,
1. Socket n TX Base Address (hereafter we'll call gSn_TX_BASE) and Socket n TX Mask Address
(hereafter we'll call gSn_TX_MASK) are calculated on TMSR value. Refer to the psedo code of the
5.1 Initialization if the detail is needed.
2. The bitwise-AND operation of two values, Sn_TX_WR and gSn_TX_MASK give result the offset
address(hereafter we'll call get_offset) in TX memory range of the socket.
3. Two values get_offset and gSn_TX_BASE are added together to give result the physical
address(hereafter, we'll call get_start_address).
Now, write the transmission data to get_start_address as large as you want. (* There's a case that it
exceeds the TX memory upper-bound of the socket while writing. In this case, write the transmission data
to the upper-bound, and change the physical address to the gSn_TX_BASE. Next, write the rest of the
transmission data.)
After that, be sure to increase the Sn_TX_WR value as large as the data size, that indicates the size of
writing data. Finally, give SEND command to Sn_CR(Socket n Command Register).
Refer to the psedo code of the transmission part on 5.2.1.1. TCP Server mode if the detail is needed.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
TOP (TCP/IP Offload Platform)
W3150A Datasheet (Ver. 1.0.1)
Figure 2. Calculate physical address
Sn_RX_RSR (RX Received Size Register) [R] [0x0426-0x0427, 0x0526-0x0527, 0x0626-0x0627,
0x0726-0x0727] [0x0000]
This register notifies the data size received in RX Memory. As this value is internally calculated with the
values of Sn_RX_RR and Sn_RX_WR, it is automatically changed by RECV command of Socket n
Command Register(Sn_CR) and receiving data for remote peer. When reading this register, user should
read upper byte(0x0426,0x0526,0x0626,0x0726) first and lower byte(0x0427,0x0527,0x0627,0x0727)
later to get the correct value.
Ex) In case of 2048(0x0800) in S0_RX_RSR,
0x0426
0x0427
0x08
0x00
The total size of this value can be decided according to the value of RX Memory Size Register.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
0x0629, 0x0728-0x0729] [0x0000]
This register offers the location information to read the receiving data. When reading this register, user
should read upper byte (0x0428, 0x0528, 0x0628, 0x0728) first and lower byte (0x0429, 0x0529, 0x0629,
0x0729) later to get the correct value.
Ex) In case of 2048(0x0800) in S0_RX_RR,
0x0429
0x08
0x00
But this value itself is not the physical address to read. So, the physical address should be calculated as
follow.
1. Socket n RX Base Address (hereafter we'll call gSn_RX_BASE) and Socket n RX Mask Address
(hereafter we'll call gSn_RX_MASK) are calculated on RMSR value. Refer to the psedo code of the
5.1 Initialization if the detail is needed.
2. The bitwise-AND operation of two values, Sn_RX_RR and gSn_RX_MASK give result the offset
address(hereafter we'll call get_offset), in RX memory range of the socket.
3. Two values get_offset and gSn_RX_BASE are added together to give result the physical
W3150A Datasheet (Ver. 1.0.1)
0x0428
TOP (TCP/IP Offload Platform)
Sn_RX_RR (Socket n RX Read Pointer Register) [R/W] [0x0428-0x0429, 0x0528-0x0529, 0x0628-
address(hereafter, we'll call get_start_address).
Now, read the receiving data from get_start_address as large as you want. (* There's a case that it
exceeds the RX memory upper-bound of the socket while reading. In this case, read the receiving data to
the upper-bound, and change the physical address to the gSn_RX_BASE. Next, read the rest of the
receiving data.)
After that, be sure to increase the Sn_RX_RR value as large as the data size, that indicates the size of
reading data. (* Must not increase more than the size of received data. So must check Sn_RX_RSR before
receiving process.) Finally, give RECV command to Sn_CR(Socket n Command Register).
Refer to the psedo code of the receiving part on 5.2.1.1. TCP Server mode if the detail is needed.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
By setting some register and memory operation, W3150A provides internet connectivity. This chapter
describes how it can be operated.
5.1. Initialization
Setting network information
environment.
1. Gateway Address Register (GAR)
2. Source Hardware Address Register (SHAR)
3. Subnet Mask Register (SUBR)
4. Source IP Address Register (SIPR)
The Source Hardware Address Regiter (SHAR) is the H/W address to be used in MAC layer, and can be used
with the address that manufacturer has been assigned. The MAC address can be assigned from IEEE. For
more detail, refer to IEEE homepage.
W3150A Datasheet (Ver. 1.0.1)
Below register is for basic network configuration information to be configured according to the network
TOP (TCP/IP Offload Platform)
5. Functional Description
Inform Gateway of local network information & Getting Gateway Hardware address
Inform Gateway of local network information for updating ARP cache table on Gateway and getting
Gateway Hardware Address using UDP sending. This procedure can be processed as below.
{
START:
/* set TCP on socket 0 mode register and open socket */
S0_MR = 0x01;
S0_CR = OPEN;
if (S0_SSR != SOCK_INIT) S0_CR = CLOSE; goto START;
/* request TCP connection to any host in different network */
S0_DIPR0 = SIPR0 + 1; // for making different network
S0_CR = CONNECT; // Set CONNECT command
Wait 10 msec;
/* getting Gateway Hardware Address */
If (S0_DHAR0 == 0xFF) goto START; // Can’t receive information
else gGatewayHA = S0_DHAR; // save gateway hardware address (6bytes)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
S0_CR = CLOSE;
}
Set socket memory information
This stage set the socket tx/rx memory information. Each socket base address, mask address are fixed and
saved in this stage.
In case of, assign 2K rx memory per socket.
RMSR = 0x55; // assign 2K rx memory per socket.
gS0_RX_BASE = chip_base_address + RX_memory_base_address(0x6000);
gS0_RX_MASK = 2K – 1 ; // 0x07FF, for getting offset address within assigned socket 0 RX memory.
gS1_RX_BASE = gS0_BASE + (gS0_MASK + 1);
gS1_RX_MASK = 2K – 1 ;
gS2_RX_BASE = gS1_BASE + (gS1_MASK + 1);
gS2_RX_MASK = 2K – 1 ;
gS3_RX_BASE = gS2_BASE + (gS2_MASK + 1);
gS3_RX_MASK = 2K – 1 ;
W3150A Datasheet (Ver. 1.0.1)
{
TOP (TCP/IP Offload Platform)
/* close socket */
TMSR = 0x55; // assign 2K tx memory per socket.
Same
method,
set
gS0_TX_BASE,
gS0_TX_MASK,
gS1_TX_BASE,
gS1_TX_MASK,
gS2_TX_BASE,
gS2_TX_MASK, gS3_TX_BASE and gS3_TX_MASK.
}
In case of, assign 4K,2K,1K,1K.
{
RMSR = 0x06; // assign 4K,2K,1K,1K rx memory per socket.
gS0_RX_BASE = chip_base_address + RX_memory_base_address(0x6000);
gS0_RX_MASK = 4K – 1 ; // 0x0FFF, for getting offset address within assigned socket 0 RX memory.
gS1_RX_BASE = gS0_BASE + (gS0_MASK + 1);
gS1_RX_MASK = 2K – 1 ; // 0x07FF
gS2_RX_BASE = gS1_BASE + (gS1_MASK + 1);
gS2_RX_MASK = 1K – 1 ; // 0x03FF
gS3_RX_BASE = gS2_BASE + (gS2_MASK + 1);
gS3_RX_MASK = 1K – 1 ; // 0x03FF
TMSR = 0x06; // assign 4K,2K,1K,1K rx memory per socket.
Same
method,
set
gS0_TX_BASE,
gS0_TX_MASK,
gS1_TX_BASE,
gS1_TX_MASK,
gS2_TX_BASE,
gS2_TX_MASK, gS3_TX_BASE and gS3_TX_MASK.
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
TOP (TCP/IP Offload Platform)
W3150A Datasheet (Ver. 1.0.1)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Data communication is available through TCP or UDP. In order to select it, configure protocol field of
Socket n Mode Register(Sn_MR) of the commnucation sockets (W3150A supports total 4 sockets) as
TCP(0x01) or UDP(0x02).
5.2.1.
TCP
TCP is connection oriented communication method that will establish connection in advance and deliver
methods to establish the connection. One is SERVER mode(passive open) that is waiting for connection
request. The other is CLIENT mode(active open) that sends connection request to SERVER.
W3150A Datasheet (Ver. 1.0.1)
the data through the connection by using IP Address and Port number of the systems. There are two
TOP (TCP/IP Offload Platform)
5.2. Data communication
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
TOP (TCP/IP Offload Platform)
5.2.1.1. SERVER mode
W3150A Datasheet (Ver. 1.0.1)
Socket Initialization
It initializes the socket as TCP,
{
START:
/* sets TCP mode */
Sn_MR = 0x01;
/* sets source port number */
Sn_PORT = source_port;
/* sets OPEN command */
Sn_CR = OPEN;
if (Sn_SSR != SOCK_INIT) Sn_CR = CLOSE; goto START;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
LISTEN
In order to wait for a connection request.
{
/* listen socket */
Sn_CR = LISTEN;
if (Sn_SSR != SOCK_LISTEN) Sn_CR = CLOSE; goto START; // check socket status
}
ESTABLISHED ?
If received connection request of remote peer (the stauts of SOCK_SYNRECV), W3150A sends ACK
packet and changes to SOCK_ESTABLISHED status. This status can be checked as below.
First method :
{
If (Sn_IR(CON bit) == ‘1’) goto ESTABLISHED stage;
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
}
W3150A Datasheet (Ver. 1.0.1)
TOP (TCP/IP Offload Platform)
Second method :
{
If (Sn_SSR == SOCK_ESTABLISHED) goto ESTABLISHED stage;
}
As connection is established, data transmission and receipt can be performed.
ESTABLISHED : Received Data ?
Check as below to know if data is received from remote peer or not.
First method :
{
if (Sn_RX_RSR != 0x0000) goto Receving Process stage;
}
Second Method :
{
If (Sn_IR(RECV bit) == ‘1’) goto Receving Process stage;
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Recevied data can be processed as below.
{
/* first, get the received size */
get_size = Sn_RX_RSR;
/* calculate offset address */
get_offset = Sn_RX_RR & gSn_RX_MASK;
/* calculate start address(physical address) */
/* if overflow socket RX memory */
if ( (get_offset + get_size) > (gSn_RX_MASK + 1) )
{
/* copy upper_size bytes of get_start_address to destination_addr */
upper_size = (gSn_RX_MASK + 1) – get_offset;
memcpy(get_start_address, destination_addr, upper_size);
/* update destination_addr*/
destination_addr += upper_size;
W3150A Datasheet (Ver. 1.0.1)
get_start_address = gSn_RX_BASE + get_offset;
TOP (TCP/IP Offload Platform)
ESTABLISHED : Receving Process
/* copy left_size bytes of gSn_RX_BASE to destination_addr */
left_size = get_size – upper_size;
memcpy(gSn_RX_BASE, destination_addr, left_size);
}
else
{
/* copy get_size bytes of get_start_address to destination_addr */
memcpy(get_start_address, destination_addr, get_size);
}
/* increase Sn_RX_RR as length of get_size */
Sn_RX_RR += get_size;
/* set RECV command */
Sn_CR = RECV;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
The sending procedure is as below.
{
/* first, get the free TX memory size */
FREESIZE:
get_free_size = Sn_TX_FSR;
if (get_free_size < send_size) goto FREESIZE;
get_offset = Sn_TX_WR & gSn_TX_MASK;
/* calculate start address(physical address) */
get_start_address = gSn_TX_BASE + get_offset;
/* if overflow socket TX memory */
if ( (get_offset + send_size) > (gSn_TX_MASK + 1) )
{
/* copy upper_size bytes of source_addr to get_start_address */
upper_size = (gSn_TX_MASK + 1) – get_offset;
W3150A Datasheet (Ver. 1.0.1)
/* calculate offset address */
TOP (TCP/IP Offload Platform)
ESTABLISHED : Send DATA ? / Sending Process
memcpy(source_addr, get_start_address, upper_size);
/* update source_addr*/
source_addr += upper_size;
/* copy left_size bytes of source_addr to gSn_TX_BASE */
left_size = send_size – upper_size;
memcpy(source_addr, gSn_TX_BASE, left_size);
}
else
{
/* copy send_size bytes of source_addr to get_start_address */
memcpy(source_addr, get_start_address, send_size);
}
/* increase Sn_TX_WR as length of send_size */
Sn_TX_WR += send_size;
/* set SEND command */
Sn_CR = SEND;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
ESTABLISHED : Received FIN?
Waiting for a connection termination request from remote peer.
It can be checked as below if it received connection termination request of remote peer.
First method :
{
If (Sn_IR(DISCON bit) == ‘1’) goto CLOSED stage;
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
Second method :
{
If (Sn_SSR == SOCK_CLOSE_WAIT) goto CLOSED stage;
}
ESTABLISHED : Disconnect ? / Disconnecting Process
Check if user requests to terminate this connection.
To terminate the connection, proceed as below,
{
W3150A Datasheet (Ver. 1.0.1)
}
TOP (TCP/IP Offload Platform)
/* set DISCON command */
Sn_CR = DISCON;
}
ESTABLISHED : CLOSED ?
No connection state at all. It can be checked as below,
First method :
{
If (Sn_IR(DISCON bit) == ‘1’) goto CLOSED stage;
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
}
Second method :
{
If (Sn_SSR == SOCK_CLOSED) goto CLOSED stage;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
ESTABLISHED : Timeout
In case that connection is closed due to the error of remote peer during data receving or connection
closing process, data transmission can not be normally processed. At this time Timeout occurs after
some time.
First method :
{
If (Sn_IR(TIMEOUT bit) == ‘1’) goto CLOSED stage;
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
}
Second method :
{
If (Sn_SSR == SOCK_CLOSED) goto CLOSED stage;
}
Socket Close
This process should be processed in case that connection is closed after data exchage, socket should
be closed with Timeout occurrence, or forcible disconnection is necessary due to abonormal operation.
W3150A Datasheet (Ver. 1.0.1)
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
TOP (TCP/IP Offload Platform)
{
/* set CLOSE command */
Sn_CR = CLOSE;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Whole process is shown as below.
TOP (TCP/IP Offload Platform)
5.2.1.2. CLIENT mode
W3150A Datasheet (Ver. 1.0.1)
Socket Initialization
Refer to 5.2.1.1 SERVER (The operation is same as SERVER).
CONNECT
Sends connection request to remote HOST(SERVER) is as below.
{
/* Write the value of server_ip, server_port to the Socket n Destination IP Address Register(Sn_DIPR),
Socket n Destination Port Register(Sn_DPORT). */
Sn_DIPR = server_ip;
Sn_DPORT = server_port;
/* set CONNECT command */
Sn_CR = CONNECT;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
ESTABLISHED ?
The connection is established. It can be checked as below,
First method :
{
If (Sn_IR(CON bit) == ‘1’) goto ESTABLISHED stage;
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
}
{
If (Sn_SSR == SOCK_ESTABLISHED) goto ESTABLISHED stage;
}
Timeout
Socket is closed as Timeout occurs as there is not response from remote peer. It can be checked as
below.
First method :
{
W3150A Datasheet (Ver. 1.0.1)
Second method :
TOP (TCP/IP Offload Platform)
If (Sn_IR(TIMEOUT bit) == ‘1’) goto CLOSED stage;
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
}
Second method :
{
If (Sn_SSR == SOCK_CLOSED) goto CLOSED stage;
}
ESTABLISHED
Refer to 5.2.1.1. SERVER (The operation is same as SERVER mode)
45/65
© Copyright 2005 WIZnet Co., Inc. All rights reserved.
UDP
UDP provides unreliable and connectionless datagram transmission structure. It processes data without
connection establishment that TCP does. Therefore, UDP message can be lost, overlapped, reversed. As
packets can arrive faster, recipient can not process all of them. In this case, user application should
guarantee the reliability of data transmission. UDP transmission can be proceeded as below,
TOP (TCP/IP Offload Platform)
5.2.2.
W3150A Datasheet (Ver. 1.0.1)
Socket Initialization
Initialize the socket as UDP.
{
START:
/* sets UDP mode */
Sn_MR = 0x02;
/* sets source port number */
/* ※ The value of Source Port can be appropriately delivered when remote HOST knows it. */
Sn_PORT = source_port;
/* sets OPEN command */
Sn_CR = OPEN;
/* Check if the value of Socket n Socket Status Register(Sn_SSR) is SOCK_UDP. */
if (Sn_SSR != SOCK_UDP) Sn_CR = CLOSE; goto START;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Received DATA?
It can be checked as below if data is received from remote peer.
First method :
{
if (Sn_RX_RSR != 0x0000) goto Receving Process stage;
}
Second Method :
{
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
}
Receiving Process
Received data can be processed as below. In case of UDP, 8byte header is attached to receiving data.
The structure of the header is as below.
IP Address (4)
Port (2)
Data size (2) (*data size except for 8byte of header)
W3150A Datasheet (Ver. 1.0.1)
If (Sn_IR(RECV bit) == ‘1’) goto Receving Process stage;
TOP (TCP/IP Offload Platform)
{
/* first, get the received size */
get_size = Sn_RX_RSR;
/* calculate offset address */
get_offset = Sn_RX_RR & gSn_RX_MASK;
/* calculate start address(physical address) */
get_start_address = gSn_RX_BASE + get_offset;
/* read head information (8 bytes) */
header_size = 8;
/* if overflow socket RX memory */
if ( (get_offset + header_size) > (gSn_RX_MASK + 1) )
{
/* copy upper_size bytes of get_start_address to header_addr */
upper_size = (gSn_RX_MASK + 1) – get_offset;
memcpy(get_start_address, header_addr, upper_size);
/* update header_addr*/
header_addr += upper_size;
/* copy left_size bytes of gSn_RX_BASE to header_addr */
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
memcpy(gSn_RX_BASE, header_addr, left_size);
/* update get_offset */
get_offset = left_size;
}
else
{
/* copy header_size bytes of get_start_address to header_addr */
/* update get_offset */
get_offset += header_size;
}
/* update get_start_address */
get_start_address = gSn_RX_BASE + get_offset;
/* save remote peer information & received data size */
peer_ip = header[0 to 3];
peer_port = header[4 to 5];
W3150A Datasheet (Ver. 1.0.1)
memcpy(get_start_address, header_addr, header_size);
TOP (TCP/IP Offload Platform)
left_size = header_size – upper_size;
get_size = header[6 to 7];
/* if overflow socket RX memory */
if ( (get_offset + get_size) > (gSn_RX_MASK + 1) )
{
/* copy upper_size bytes of get_start_address to destination_addr */
upper_size = (gSn_RX_MASK + 1) – get_offset;
memcpy(get_start_address, destination_addr, upper_size);
/* update destination_addr*/
destination_addr += upper_size;
/* copy left_size bytes of gSn_RX_BASE to destination_addr */
left_size = get_size – upper_size;
memcpy(gSn_RX_BASE, destination_addr, left_size);
}
else
{
/* copy get_size bytes of get_start_address to destination_addr */
memcpy(get_start_address, destination_addr, get_size);
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Sn_RX_RR = Sn_RX_RR + get_size + header_size;
/* set RECV command */
Sn_CR = RECV;
}
Send Data? / Sending Process
Data transmission process is as below.
/* first, get the free TX memory size */
FREESIZE:
get_free_size = Sn_TX_FSR;
if (get_free_size < send_size) goto FREESIZE;
/* Write the value of remote_ip, remote_port to the Socket n Destination IP Address Register(Sn_DIPR),
Socket n Destination Port Register(Sn_DPORT). */
Sn_DIPR = remote_ip;
Sn_DPORT = remote_port;
W3150A Datasheet (Ver. 1.0.1)
{
TOP (TCP/IP Offload Platform)
/* increase Sn_RX_RR as length of get_size+header_size */
/* calculate offset address */
get_offset = Sn_TX_WR & gSn_TX_MASK;
/* calculate start address(physical address) */
get_start_address = gSn_TX_BASE + get_offset;
/* if overflow socket TX memory */
if ( (get_offset + send_size) > (gSn_TX_MASK + 1) )
{
/* copy upper_size bytes of source_addr to get_start_address */
upper_size = (gSn_TX_MASK + 1) – get_offset;
memcpy(source_addr, get_start_address, upper_size);
/* update source_addr*/
source_addr += upper_size;
/* copy left_size bytes of source_addr to gSn_TX_BASE */
left_size = send_size – upper_size;
memcpy(source_addr, gSn_TX_BASE, left_size);
}
else
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
/* copy send_size bytes of source_addr to get_start_address */
memcpy(source_addr, get_start_address, send_size);
}
/* increase Sn_TX_WR as length of send_size */
Sn_TX_WR += send_size;
/* set SEND command */
Sn_CR = SEND;
Complete Sending?
The sending completion should be checked after SEND command.
{
If (Sn_CR == 0x00) transmission is completed.
}
Timeout
Timeout occurs if there is not remote peer or data transmission is not proceeded due to abnormal
W3150A Datasheet (Ver. 1.0.1)
}
TOP (TCP/IP Offload Platform)
{
network. It can be checked as below.
{
If (Sn_IR(TIMEOUT bit) == ‘1’) goto next stage;
/* In this case, if the interrupt of Socket n is activated, interrupt occurs. Refer to Interrupt
Register(IR), Interrupt Mask Register (IMR) and Socket n Interrupt Register (Sn_IR). */
}
Finished? / Socket Close
If all the actions are finished, close the socket.
{
/* set CLOSE command */
Sn_CR = CLOSE;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
IP raw
IP Raw mode can be utilized if transport layer protocol of some ICMP or IGMP that W3150A does not
support, needs to be processed.
W3150A Datasheet (Ver. 1.0.1)
TOP (TCP/IP Offload Platform)
5.2.3.
Socket Initialization
It initializes the socket as IP raw.
{
START:
/* sets IP raw mode */
Sn_MR = 0x03;
/* sets Protocol value */
/* The value of Protocol is the value used in Protocol Field of IP Header.
For the list of protocol identification number of upper classification, refer to on line documents of
IANA (http://www.iana.org/assignments/protocol-numbers). */
HTU
UTH
Sn_PROTO = protocol_value;
/* sets OPEN command */
Sn_CR = OPEN;
/* Check if the value of Socket n Socket Status Register(Sn_SSR) is SOCK_IPRAW. */
if (Sn_SSR != SOCK_IPRAW) Sn_CR = CLOSE; goto START;
}
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
Received DATA?
This is same as UDP. Refer to 5.2.2 UDP.
Receiving Process
This is same as UDP. Refer to 5.2.2 UDP except the header information and header size.
In case of IP raw, 6byte header is attached to the data received. The header structure is as below.
IP Address (4)
Send DATA? / Sending Process
This is same as UDP. Refer to 5.2.2 UDP except that remote_port information is don’t needed.
Complete Sending
Timeout
Finished? / Socket Closed
Next actions are same as UDP. Refer to 5.2.2 UDP.
W3150A Datasheet (Ver. 1.0.1)
Data Size (2) (*Data size except for 6 bytes of header)
TOP (TCP/IP Offload Platform)
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For the communication with MCU, W3150A provides Direct Bus I/F and Indirect Bus I/F mode. For the
communication with Ethernet PHY, MII is used.
6.1. Direct Bus I/F Mode.
Direct Bus I/F mode uses 15bit address line and 8bit data line, /CS, /RD, /WR, /INT.
Indirect Bus I/F mode uses 2bit address line and 8bit data line, /CS, /RD, /WR, /INT.
W3150A Datasheet (Ver. 1.0.1)
6.2. Indirect Bus I/F Mode.
TOP (TCP/IP Offload Platform)
6. Application Information
[14:2], other address lines should process Pull-down.
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Value
Symbol
Description
It performs the selection of Indirect bus I/F mode, Little/Big endian,
0x00
MR
and address automatic increase. Refer to 4. Register Description” for
more detail.
Indirect bus I/F mode address Register
MSB/LSB can be decided by LB bit of MODE Register.
1. In case that LB bit is set to 0
0x02
IDM_AR0 : MSB
IDM_AR1 : LSB
Ex) In case of reading S0_CR(0x0401),
0x01
IDM_AR0
0x02
IDM_AR1
0x01(IDM_AR0)
0x02(IDM_AR1)
0x04
0x01
2. In case that LB bit is set to 1
0x01
0x02
IDM_AR0 : LSB
IDM_AR1 : MSB
W3150A Datasheet (Ver. 1.0.1)
0x01
TOP (TCP/IP Offload Platform)
Indirect bus I/F mode related register is as below.
Ex) In case of reading S0_CR(0x0401),
0x03
IDM_DR
0x01(IDM_AR0)
0x02(IDM_AR1)
0x01
0x04
Indirect bus I/F mode data Register
In order to read or write the internal register or internal TX/RX Memory,
1. Write the address to read or write on IDM_AR0,1.
2. Read or Write IDM_DR.
In order to read or write the data on the sequential address, set AI bit of MR(Mode Register). With this,
user performs above 1 only one time. Whenever reading or writing IDM_DR, IDM_AR value increases by 1
automatically. So, the value can be processed on the sequential address just by continuous reading or
writing of IDM_DR.
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
The MII handles the data transfer between the W3150A and the Physical Layer Device.
The MII is composed of TX_CLK, TXE, and TXD[0:3] signals for sending data and RX_CLK, CRS, RXDV,
RXD[0:3], and COL signals for receiving data.
When sending data from the W3150A, TXE and TXD[0:3] are output in synchronization with the falling
edges of TX_CLK input from the Physical Layer Device because Physical Layer Devices generally recognize
the rising edges of TX_CLK.
in synchronization with the falling edges of RX_CLK, so the W3150A recognizes the signals at the rising
edges of RX_CLK.
W3150A Datasheet (Ver. 1.0.1)
When receiving data, in general, the Physical Layer Devices output CRS, RXDV, RXD[0:3], and COL signals
TOP (TCP/IP Offload Platform)
6.3. MII (Media Independent Interface)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
7.1. Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
DC Supply voltage
-0.5 to 3.6
V
VIN
DC input voltage
-0.5 to 5.5 (5V tolerant)
V
DC input current
±5
mA
Operating temperature
0 to 80
°C
Storage temperature
-55 to 125
°C
B
B
B
IIN
B
B
B
TOP
B
B
TSTG
B
B
*COMMENT: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
7.2. DC Characteristics
Symbol
Parameter
Test Condition
Junction temperature is from -
Min
Max
Unit
3.6
V
VDD
DC Supply voltage
VIH
High level input voltage
2.0
Low level input voltage
- 0.5
0.8
V
B
B
B
VIL
B
B
B
VOH
B
VOL
B
II
B
B
B
B
55C to 125C
3.0
Typ
5.5
V
High level output voltage
IOH = 2, 4, 8, 12, 16, 24 mA
2.0
3.6
V
Low level output voltage
IOL = -2, -4, -8, -12, -16, -24 mA
0.0
0.4
V
Input Current
VIN = VDD
±5
µA
B
B
B
B
W3150A Datasheet (Ver. 1.0.1)
VDD
TOP (TCP/IP Offload Platform)
7. Electrical Specification
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TOP (TCP/IP Offload Platform)
7.3. AC Characteristics
7.3.1.
Reset Timing
tRST
B
B
Reset Cycle Time
B
tRLC
Parameter
B
/RESET to PLOCK Output
Min
Max
96 ns
-
-
10 ms
W3150A Datasheet (Ver. 1.0.1)
Symbol
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
TOP (TCP/IP Offload Platform)
7.3.2.
Register/Memory READ Timing
W3150A Datasheet (Ver. 1.0.1)
Symbol
Min
Max
80 ns
-
/CS to Valid Output
-
80 ns
/RD to Valid Output
-
80 ns
tCLZ
/CS to Low-Z Output
0 ns
-
tRLZ
/RD to Low-Z Output
0 ns
-
tCHZ
/CS to High-Z Output
-
1 ns
tRHZ
/RD to High-Z Output
-
1 ns
tRC
B
Read Cycle Time
B
tCVO
B
tRVO
B
B
B
B
B
B
B
B
B
Parameter
B
B
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TOP (TCP/IP Offload Platform)
7.3.3.
Register/Memory WRITE Timing
Min
Max
Write Cycle Time
70 ns
-
/CS to Write End
70 ns
-
tWP
/WR Pulse width
63 ns
-
tSD
/WR low to SD valid
-
14 ns
0 ns
-
tWC
B
tCW
B
B
B
B
B
tHD
B
B
B
B
Parameter
Data Hold from Write End
W3150A Datasheet (Ver. 1.0.1)
Symbol
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
TOP (TCP/IP Offload Platform)
7.3.4.
MII(Media Independent Interface) Timing
MII Tx TIMING
tCO
B
B
tDCS
B
tCO
B
B
tDCS
B
B
B
Parameter
Notes
Min
Typ
Max
TX_CLK to TXD, TX_EN
10 Mbps
202 ns
-
205 ns
TXD, TX_EN setup time to TX_CLK
10 Mbps
195 ns
-
198 ns
TX_CLK to TXD, TX_EN
100 Mbps
22 ns
-
25 ns
TXD, TX_EN setup time to TX_CLK
100 Mbps
15 ns
-
18 ns
W3150A Datasheet (Ver. 1.0.1)
Symbol
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.
tDCS
B
B
tCDH
B
B
B
tCDH
B
B
B
Parameter
Notes
Valid Data to RX_CLK (setup)
10 Mbps
RX_CLK to Valid Data (hold)
Min
Typ
Max
5 ns
-
-
10 Mbps
5 ns
-
-
Valid Data to RX_CLK (setup)
100 Mbps
5 ns
-
-
RX_CLK to Valid Data (hold)
100 Mbps
5 ns
-
-
W3150A Datasheet (Ver. 1.0.1)
Symbol
tDCS
TOP (TCP/IP Offload Platform)
MII Rx TIMING
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Moisture Sensitivity Level at 260oC IR Condition: 2.
Dry Bag Required: Yes
1 year out of bag time at max 30oC/60%RH.
Max. Temperature 260oC
< 3oC/second
Pre-heat temperature at 175°C(±25°C)
77-95 seconds
Temperature above 217°C
96-107 seconds
Time within 5°C of actual peak temperature
17-25 seconds
Peak temperature range
258-260oC
Ramp-down rate
< 6oC/second
W3150A Datasheet (Ver. 1.0.1)
Ramp up rate
TOP (TCP/IP Offload Platform)
8. IR Reflow Temperature Profile (Lead-Free)
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TOP (TCP/IP Offload Platform)
9. Package Description
W3150A Datasheet (Ver. 1.0.1)
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TOP (TCP/IP Offload Platform)
W3150A Datasheet (Ver. 1.0.1)
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© Copyright 2005 WIZnet Co., Inc. All rights reserved.