ZL38003 AEC with Noise Reduction & Codecs for Digital Hands-Free Communication Data Sheet A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. May 2006 Ordering Information ZL38003GMG 81 Ball CBGA Trays, Bake & Drypack ZL38003GMG2 81 Ball CBGA** Trays, Bake & Drypack **Pb Free Tin/Silver/Copper Features • Handles up to -6 dB acoustic echo return loss • 127 ms acoustic echo canceller • Provides up to 12 dB of Noise Reduction • Operate in two modes, Dual Analog mode and single Analog mode (other port is digital PCM) • PCM Data Formats in single Port mode- 16-bit Linear, companded ITU-T A-law or U-law -40°C to +85°C • Howling prevention eliminates uncontrolled oscillation in high loop gain conditions • AGC on speaker path • Transparent data transfer and mute options • Boot loadable for future factory software upgrades • Serial micro-controller interface • Two 16 bit linear ACD and DAC that meet ITU-T G.711/712 recommendations • Advanced NLP design - full duplex speech with no switched loss on audio paths • Tracks changing echo environment quickly • Adaptation algorithm converges even during Double-Talk • Four Audio TX/RX Interfaces • Designed for performance in high background noise environments • Differential Microphone Inputs • • Provides protection against narrow-band signal divergence Programmable Bias Voltage Output for Electret microphones • Microphone Presence Detection, Microphone Mute SCLK CS_CODEC CS_AEC DATA1 EAR Serial Microport Interface G.712 Codec #1 PCM Timing BIAS EAR Rout/Sout Rin AEC Sout MIC #3 MICDET DATA2 FPi C4i Audio Interface Audio Interface MIC #2 BIAS MICDET Crosspoint Sin/Rin G.712 Codec #0 Audio Interface EAR #1 MIC Audio Interface MCLK #0 RESETB AUXTONE Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005-2006, Zarlink Semiconductor Inc. All Rights Reserved. EAR/SPEAKER MIC BIAS ZL38003 • Data Sheet Multiple Gain pad settings • Adjustable gain pads from -24 dB to +21 dB at Xin, Sin and Sout to compensate for different system requirements • Programmable Microphone Gain (0dB to +46.5 dB in 1.5 dB Steps) • Side tone Mute, Programmable Side tone Gain (-39 dB to +6 dB in 3 dB Steps) • User gain control provided for speaker path (-24 dB to +21 dB in 3 dB steps) • Programmable Earpiece Gain (-28 dB to +2 dB in 2 dB Steps) • RX Channel Mute, Programmable RX Volume control (-21 dB to 0 dB in 3 dB Steps) • Differential Earpiece Driver Outputs (66 mW rms into 32 Ohms, 150 mW rms into 16 Ohms) • Cross-Point Connects PCM Channels to any of the Four Audio TX/RX Interfaces Applications • Hands-free car kits • Full duplex speaker-phone for digital telephone • Echo cancellation for video conferences • Intercom Systems • Security Systems MT93L16 ZL38001 ZL38002 ZL38003 Description AEC for analog handsfree communication AEC for analog hands- AEC with noise reduction for digital free communication hands-free communication AEC with noise reduction & codecs for digital hands-free communication Application Analog Desktop phone Analog Intercom Hands-free Car Kits Analog Desktop phone Hands-free Car Kits Analog Intercom Digital Desktop Phone Home Security Digital Desktop Phone Home Security Intercom & Pedestals Intercom & Pedestals Features AEC 1 channel 1 channel 1 channel 1 channel LEC 1 channel 1 channel Custom Load Custom Load Gains User Gain User Gain/18 dB Gain on Sout User Gain + System tuning gains User Gain + System tuning gains Noise Reduction N N Y Y Integrated Codecs N N N dual channel Table 1 - Acoustic Echo Cancellation Family 1.0 Functional Description The ZL38003 is an Acoustic Echo Canceller (AEC) with dual codec as shown in Figure 2. The ZL38003 provides 127 ms of acoustic echo cancellation, which makes it ideal for hand free car kits, and speaker phones designs. Each of the codecs in the dual codec can be connected to 1 of 4 four analog ports through a cross point switch. Also, the network side can be routed to a digital PCM interface that input/outputs either linear 2's complement or A-/mu law commanded PCM data. 2 Zarlink Semiconductor Inc. ZL38003 2.0 Data Sheet Acoustic Echo Canceller (AEC) Description The AEC section is comprised of an acoustic echo canceller, noise reduction and the operational control functions for operation. The AEC guarantees clear signal transmission in both transmit and receive audio path directions ensuring reliable voice communication even when low level signals are provided. The AEC does not use variable attenuators during double-talk or single-talk periods of speech, as do many other acoustic echo cancellers for speakerphones. Instead, the AEC provides high performance full-duplex operation similar to network echo cancellers. This results in users experiencing clear speech and uninterrupted background signals during the conversation and prevents subjective sound quality problems associated with “noise gating” or “noise contrasting”. The AEC uses an advanced adaptive filter algorithm that is double-talk stable, allowing convergence even while both parties are talking. This algorithm continually tracks changes in the echo path, regardless of double-talk, as long as a reference signal is available for the echo canceller. The echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (127 ms) to cancel echo in an average sized office or large size car with a reverberation time of less than 127 ms. HP Filter Linear ACOUSTIC ECHO PATH Sin µ/A-Law/ Gain Pad S1 + S2 + - Limiter ADV NLP Noise Reduction Linear/ µ/A-Law Gain Pad Program RAM NBSD CONTROL Adaptive Filter Program ROM UNIT Double Talk Detector Gain Pad R1 Sout Micro Interface Howling R1 NBSD Controller -24 -> +21dB Rout Linear/ µ/A-Law AGC User Gain Limiter Figure 2 - AEC Block Diagram 3 Zarlink Semiconductor Inc. HP Filter µ/A-Law/ Linear Rin ZL38003 2.1 Data Sheet In addition to the echo cancellers, the following functions are supported: • 12 dB of noise reduction • User gain control provided for speaker path (-24 dB to +21 dB in 3 dB steps) • Gain pads at the Sin and Sout ports plus one at the input of adaptive filter (XRAM) • Control of adaptive filter convergence speed during periods of double-talk, far end single-talk and near-end echo path changes • Control of Non-Linear Processor thresholds for suppression of residual non-linear echo • Howling detector to identify when instability is starting to occur and to take action to prevent oscillation • Narrow-Band Detector for preventing adaptive filter divergence caused by narrow-band signals • Programmable high pass filters at Rin and Sin for removal of DC components in PCM channels • Limiters that introduce controlled saturation levels • Serial controller interface compatible with Motorola, National and Intel micro controllers • PCM encoder/decoder compatible with m/A-Law ITU-T G.711, m/A-Law Sign-Mag or linear 2’s complement coding • Automatic gain control on the receive speaker path • Idle channel noise suppression 3.0 Dual Codec Description The CODEC Dual Codec provides complete audio to PCM interfaces including filtering and optional data companding as required by the ITU-T G.711 & G.712 recommendations. Programmable gain allows adjustment for a wide range of transducer sensitivities - two microphone amplifiers and four ear piece amplifiers are provided to allow connection to a handset, headset, auxiliary channel and microphone/speaker. A cross-point circuit allows either codec to be connected to any of the four audio interfaces. Programmable voltage sources are available for electret biasing on the Microphone channels. PCM voice data is passed via a serial interface which operates in ST-BUS or GCI mode. ST-BUS mode allows the Codecs to be allocated to any of the 32 available channels. Control and programming of the Codecs is carried out over a flexible serial micro-controller interface. 4 Zarlink Semiconductor Inc. ZL38003 4 Serial uPort Data Control for companding mode, RX gain control(s), sidetone level, RX hi-pass filter, cross-point, muting, electret biasing, microphone pre-amp and gain, PLL D A C u/A Law Electret Bias Mic Detect G.712 Filtering Sidetone Data Data Sheet A D C u/A Law Codec #1 4 Electret Bias Codec #0 Data u/A Law G.712 Filtering Sidetone Data Mic Detect D A C A D C u/A Law Status VREF PLL Voice Serial PCM Interface Cross-Point SYSCLK RESETB VREF AUXTONE Figure 3 - Block Diagram 5 Zarlink Semiconductor Inc. Electret Bias Package Code c Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Previous package codes For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE