Revised February 2005 NC7WZ132 TinyLogic£ UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs General Description Features The NC7WZ132 is a dual 2-Input NAND Gate from Fairchild's Ultra High Speed Series of TinyLogic£. The device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while maintaining low static power dissipation over a broad VCC operating range. The device is specified to operate over the 1.65V to 5.5V VCC operating range. The inputs and output are high impedance when VCC is 0V. Inputs tolerate voltages up to 7V independent of VCC operating voltage. Schmitt trigger inputs achieve typically 1V hysteresis between the positive-going and negative-going input threshold voltage at 5V VCC. ■ Space saving US8 surface mount package ■ MicroPak¥ Pb-Free leadless package ■ Ultra High Speed; tPD 3.1 ns typ into 50 pF at 5V VCC ■ High Output Drive; r24 mA at 3V VCC ■ Broad VCC Operating Range; 1.65V to 5.5V ■ Matches the performance of LCX when operated at 3.3V VCC ■ Power down high impedance inputs/output ■ Overvoltage tolerant inputs facilitate 5V to 3V translation ■ Patented noise/EMI reduction circuitry implemented ■ Schmitt trigger inputs are tolerant of slow changing input signals Ordering Code: Product Order Package Code Number Number Top Mark MAB08A WZD2 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide NC7WZ132K8X_NL MAB08A (Note 1) WZD2 Pb-Free 8-Lead US8, JEDEC MO-187, Variation CA 3k Units on Tape and Reel 3.1mm Wide NC7WZ132K8X NC7WZ132L8X MAC08A T5 Package Description Pb-Free 8-Lead MicroPak, 1.6 mm Wide Supplied As 3k Units on Tape and Reel 5k Units on Tape and Reel Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only. TinyLogic£ is a registered trademark of Fairchild Semiconductor Corporation. MicroPak¥ is a trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS500274 www.fairchildsemi.com NC7WZ132 TinyLogic£ UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs April 2000 NC7WZ132 Logic Symbol Connection Diagrams IEEE/IEC Pin Descriptions (Top View) Pin Names Description An , Bn Inputs Yn Output Pin One Orientation Diagram Function Table Y Inputs H AAA represents Product Code Top Mark - see ordering code AB A B Y L L H L H H H L H H H HIGH Logic Level Note: Orientation of Top Mark determines Pin One location. Read the top product code mark left to right, Pin One is the lower left pin (see diagram). Output L Pad Assignments for MicroPak L LOW Logic Level (Top Thru View) www.fairchildsemi.com 2 Recommended Operating Conditions (Note 3) 0.5V to 7V 0.5V to 7V 0.5V to 7V Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Supply Voltage Operating (VCC) 1.65V to 5.5V Supply Voltage Data Retention (VCC) DC Input Diode Current (IIK) 1.5V to 5.5V Input Voltage (VIN) @VIN 0.5V 50 mA 0V to 5.5V Output Voltage (VOUT) DC Output Diode Current (IOK) 0V to VCC 40qC to 85qC 250qC/W Operating Temperature (TA) @VOUT 0.5V 50 mA r 50 mA DC Output Current (IOUT) DC VCC/GND Current (ICC/IGND) Storage Temperature (TSTG) Junction Temperature under Bias (TJ) Thermal Resistance (TJA) r 100 mA 65qC to 150qC 150qC Note 2: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications. Junction Lead Temperature (TL); 260qC (Soldering, 10 seconds) Power Dissipation (PD) @ 85qC 250 mW Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VP VN VH VOH VOL Parameter VCC TA 25qC TA 40qC to 85qC (V) Min Typ Max Min Max Positive Threshold 1.65 0.6 0.99 1.4 0.6 1.4 Voltage 2.3 1.0 1.39 1.8 1.0 1.8 3.0 1.3 1.77 2.2 1.3 2.2 4.5 1.9 2.49 3.1 1.9 3.1 5.5 2.2 2.96 3.6 2.2 3.6 Negative Threshold 1.65 0.2 0.53 0.9 0.2 0.9 Voltage 2.3 0.4 0.78 1.15 0.4 1.15 3.0 0.6 1.02 1.5 0.6 1.5 4.5 1.0 1.48 2.0 1.0 2.0 2.3 Hysteresis Voltage 5.5 1.2 1.76 2.3 1.2 1.65 0.15 0.46 0.9 0.15 0.9 2.3 0.25 0.61 1.1 0.25 1.1 3.0 0.4 0.75 1.2 0.4 1.2 4.5 0.6 1.01 1.5 0.6 1.5 1.7 0.7 1.7 Units Conditions V V V 5.5 0.7 1.20 HIGH Level Output 1.65 1.55 1.65 1.55 Voltage 2.3 2.2 2.3 2.2 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 1.65 1.29 1.52 1.29 IOH 2.3 1.9 2.15 1.9 IOH 8 mA 3.0 2.4 2.80 2.4 IOH 16 mA 3.0 2.3 2.68 2.3 IOH 24 mA 4.5 3.8 4.20 3.8 IOH 32 mA LOW Level Output 1.65 Voltage IIN Input Leakage Current IOFF Power Off Leakage Current V VIN V 0.0 0.10 0.10 2.3 0.0 0.10 0.10 3.0 0.0 0.10 0.10 V VIN 100 PA VIL IOH VIH IOL 4 mA 100 PA 4.5 0.0 0.10 0.10 1.65 0.08 0.24 0.24 IOL 2.3 0.10 0.3 0.3 IOL 8 mA 3.0 0.15 0.4 0.4 IOL 16 mA 3.0 0.22 0.55 0.55 IOL 24 mA 4.5 0.22 0.55 0.55 IOL 32 mA 0 to 5.5 r0.1 r1 PA VIN 0.0 1 10 PA VIN or VOUT 3 V 4 mA 5.5V, GND 5.5V www.fairchildsemi.com NC7WZ132 Absolute Maximum Ratings(Note 2) NC7WZ132 DC Electrical Characteristics Symbol VCC Parameter TA (V) Quiescent Supply Current ICC (Continued) Min 25qC Typ TA Max 1.65 to 5.5 40qC to 85qC Min Units Conditions Max 1 PA 10 VIN 5.5V, GND AC Electrical Characteristics Symbol tPLH, Parameter Propagation Delay tPHL Propagation Delay tPLH, tPHL CIN Input Capacitance CPD Power Dissipation Capacitance TA VCC (V) 25qC TA Min Typ Max 1.8 r 0.15 3.0 7.1 2.5 r 0.2 2.0 4.5 3.3 r 0.3 1.2 3.4 40qC to 85qC Min Max 13.0 3.0 13.5 7.5 2.0 8.0 5.0 1.2 5.5 5.0 r 0.5 0.8 2.6 3.8 0.8 4.2 3.3 r 0.3 1.8 4.0 5.8 1.8 6.3 5.0 r 0.5 1.2 3.1 4.5 1.2 4.9 0 2.5 3.3 15 5.0 18 Units ns ns Conditions CL 15 pF, RL 1 M: CL 50 pF, RL 500: Figure Number Figures 1, 3 Figures 1, 3 pF pF (Note 4) Figure 2 Note 4: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression: ICCD (CPD)(VCC)(fIN) (ICCstatic). AC Loading and Waveforms CL includes load and stray capacitance Input PRR 1.0 MHz; tw 500 ns FIGURE 1. AC Test Circuit FIGURE 3. AC Waveforms Input AC Waveform; tr PRR 10 MHz; Duty Cycle tf 1.8 ns; 50% FIGURE 2. ICCD Test Circuit www.fairchildsemi.com 4 Tape Format for US8 Package Designator Tape Number Cavity Section Cavities Status Status 125 (typ) Empty Sealed Leader (Start End) K8X Carrier Trailer (Hub End) Cover Tape 3000 Filled Sealed 75 (typ) Empty Sealed Cover Tape TAPE DIMENSIONS inches (millimeters) Tape Format for MicroPak Package Designator Tape Number Cavity Section Cavities Status Status 125 (typ) Empty Sealed Leader (Start End) L8X Carrier Trailer (Hub End) 3000 Filled Sealed 75 (typ) Empty Sealed TAPE DIMENSIONS inches (millimeters) 5 www.fairchildsemi.com NC7WZ132 Tape and Reel Specification NC7WZ132 Tape and Reel Specification (Continued) REEL DIMENSIONS inches (millimeters) Tape Size 8 mm A B C D N W1 W2 W3 7.0 0.059 0.512 0.795 2.165 0.331 0.059/0.000 0.567 W1 0.078/0.039 (177.8) (1.50) (13.00) (20.20) (55.00) (8.40 1.50/0.00) (14.40) (W1 2.00/1.00) www.fairchildsemi.com 6 NC7WZ132 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Package Number MAB08A 7 www.fairchildsemi.com NC7WZ132 TinyLogic£ UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 8-Lead MicroPak, 1.6 mm Wide Package Number MAC08A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8