Am29F032B Data Sheet The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 21610 Revision D Amendment 5 Issue Date November 2, 2006 THIS PAGE LEFT INTENTIONALLY BLANK. DATA SHEET Am29F032B 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ 5.0 V ± 10%, single power supply operation — Minimizes system level power requirements ■ Manufactured on 0.32 µm process technology ■ High performance — Access times as fast as 70 ns ■ Low power consumption — 30 mA typical active read current — 30 mA typical program/erase current — <1 µA typical standby current (standard access time to active mode) ■ Flexible sector architecture — 64 uniform sectors of 64 Kbytes each — Any combination of sectors can be erased. — Supports full chip erase — Group sector protection: — A hardware method of locking sector groups to prevent any program or erase operations within that sector group — Temporary Sector Group Unprotect allows code changes in previously locked sectors ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ■ Minimum 1,000,000 write/erase cycles guaranteed ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ Package options — 40-pin TSOP — 44-pin SO ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply Flash standard — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase cycle completion ■ Ready/Busy output (RY/BY#) — Provides a hardware method for detecting program or erase cycle completion ■ Erase Suspend/Resume — Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation ■ Hardware reset pin (RESET#) — Resets internal state machine to the read mode — Embedded Program algorithm automatically writes and verifies bytes at specified addresses This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21610 Rev: D Amendment: 5 Issue Date: November 2, 2006 D A T A S H E E T GENERAL DESCRIPTION The Am29F032B is a 32 Mbit, 5.0 volt-only Flash memory organized as 4,194,304 bytes of 8 bits each. The 4 Mbytes of data are divided into 64 sectors of 64 Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0–DQ7. The Am29F032B is offered in 40-pin TSOP and 44-pin SO packages. The Am29F032B is manufactured using AMD’s 0.32 µm process technology. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 70 and 90 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 volt Flash or EPROM devices. The device is programmed by executing the program command sequence. This invokes the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The device is erased by executing the erase command sequence. This invokes the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. 2 The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. A sector is typically erased and verified within one second. The device is erased when shipped from the factory. The hardware sector group protection feature disables both program and erase operations in any combination of the eight sector groups of memory. A sector group consists of four adjacent sectors. The Erase Suspend feature enables the system to put erase on hold for any period of time to read data from, or program data to, a sector that is not being erased. True background erase can thus be achieved. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The host system can detect whether a program or erase cycle is complete by using the RY/BY# pin, the DQ7 (Data# Polling) or DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device automatically returns to the read mode. A hardware RESET# pin terminates any operation in progress. The internal state machine is reset to the read mode. The RESET# pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during either an Embedded Program or Embedded Erase algorithm, the device is automatically reset to the read mode. This enables the system’s microprocessor to read the boot-up firmware from the Flash memory. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y, a n d c o s t effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the programming mechanism of hot electron injection. Am29F032B 21610D5 November 2, 2006 D A T A S H E E T TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 4 4 5 6 6 7 8 Table 1. Am29F032B Device Bus Operations .................................. 8 Requirements for Reading Array Data ..................................... Writing Commands/Command Sequences .............................. Program and Erase Operation Status ...................................... Standby Mode .......................................................................... RESET#: Hardware Reset Pin ................................................. Output Disable Mode................................................................ 8 8 9 9 9 9 Table 2. Am29F032B Sector Address Table................................... 10 Autoselect Mode..................................................................... 11 Table 3. Am29F032B Autoselect Codes ......................................... 11 Sector Group Protection/Unprotection.................................... 12 Table 4. Sector Group Addresses................................................... 12 Temporary Sector Group Unprotect ....................................... 12 Figure 1. Temporary Sector Group Unprotect Operation................ 12 Hardware Data Protection ...................................................... 13 Low VCC Write Inhibit..................................................................... 13 Write Pulse “Glitch” Protection........................................................ 13 Logical Inhibit .................................................................................. 13 Power-Up Write Inhibit .................................................................... 13 Command Definitions . . . . . . . . . . . . . . . . . . . . . 13 Reading Array Data ................................................................ 13 Reset Command..................................................................... 13 Autoselect Command Sequence ............................................ 14 Byte Program Command Sequence....................................... 14 Chip Erase Command Sequence ........................................... 14 Figure 2. Program Operation .......................................................... 15 Sector Erase Command Sequence ........................................ 15 Erase Suspend/Erase Resume Commands........................... 15 Figure 3. Erase Operation............................................................... 16 Table 5. Am29F032B Command Definitions................................... 17 Write Operation Status . . . . . . . . . . . . . . . . . . . . 18 DQ7: Data# Polling................................................................. 18 Figure 4. Data# Polling Algorithm ................................................... 18 DQ6: Toggle Bit I .................................................................... 19 November 2, 2006 21610D5 DQ2: Toggle Bit II ................................................................... Reading Toggle Bits DQ6/DQ2............................................... DQ5: Exceeded Timing Limits ................................................ DQ3: Sector Erase Timer ....................................................... 19 19 20 20 Figure 5. Toggle Bit Algorithm........................................................ 20 Table 6. Write Operation Status..................................................... 21 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22 Figure 6. Maximum Negative Overshoot Waveform ...................... 22 Figure 7. Maximum Positive Overshoot Waveform........................ 22 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23 TTL/NMOS Compatible .......................................................... 23 CMOS Compatible.................................................................. 23 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 8. Test Setup...................................................................... 24 Table 7. Test Specifications ........................................................... 24 Key To Switching Waveforms . . . . . . . . . . . . . . . 24 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25 Read-only Operations............................................................. 25 Figure 9. Read Operation Timings ................................................. 25 Hardware Reset (RESET#) .................................................... 26 Figure 10. RESET# Timings .......................................................... 26 Write (Erase/Program) Operations ......................................... 27 Figure 11. Program Operation Timings.......................................... Figure 12. Chip/Sector Erase Operation Timings .......................... Figure 13. Data# Polling Timings (During Embedded Algorithms). Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... Figure 15. DQ2 vs. DQ6................................................................. 28 29 30 30 31 Temporary Sector Unprotect .................................................. 31 Figure 16. Temporary Sector Group Unprotect Timings ................ 31 Write (Erase/Program) Operations—Alternate CE# Controlled Writes .................................................................... 32 Figure 17. Alternate CE# Controlled Write Operation Timings ...... 33 Erase And Programming Performance . . . . . . . 34 Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 34 TSOP And SO Pin Capacitance . . . . . . . . . . . . . 34 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 35 SO 044–44-Pin Small Outline Package.................................. 35 TS 040–40-Pin Standard Thin Small Outline Package........... 36 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 37 Am29F032B 3 D A T A S H E E T PRODUCT SELECTOR GUIDE Family Part Number Am29F032B VCC = 5.0 V ± 5% Speed Options -75 VCC = 5.0 V ± 10% -90 Max access time, ns (tACC) 70 90 Max CE# access time, ns (tCE) 70 90 Max OE# access time, ns (tOE) 40 40 Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM DQ0–DQ7 Sector Switches VCC VSS Erase Voltage Generator RY/BY# RESET# WE# Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable CE# OE# VCC Detector Address Latch STB Timer A0–A21 4 Am29F032B STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 21610D5 November 2, 2006 D A T A S H E E T CONNECTION DIAGRAMS A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-Pin Standard TSOP NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS November 2, 2006 21610D5 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SO Am29F032B 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A20 A21 WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 VCC CE# A12 A13 A14 A15 A16 A17 A18 A19 NC NC A20 A21 WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC 5 D A T A PIN CONFIGURATION A0–A21 = LOGIC SYMBOL 22 Addresses DQ0–DQ7 = 8 Data Inputs/Outputs CE# = Chip Enable WE# = Write Enable OE# = Output Enable RESET# = Hardware Reset Pin, Active Low RY/BY# = Ready/Busy Output VCC = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) VSS = Device Ground NC = Pin Not Connected Internally 6 S H E E T 22 A0–A21 8 DQ0–DQ7 CE# OE# WE# RESET# Am29F032B RY/BY# 21610D5 November 2, 2006 D A T A S H E E T ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29F032B -75 E I TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) D = Commercial (0oC to +70oC) with Pb-free Package F = Industrial (–40°C to +85°C) with Pb-free Package K = Extended (–55°C to +125°C) with Pb-free Package PACKAGE TYPE E = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040) S = 44-Pin Small Outline Package (SO 044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F032B 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory 5.0 V Read, Program, and Erase Valid Combinations Valid Combinations AM29F032B-75 EC, EI, ED, EF, SC, SI, SD, SF AM29F032B-90 EC, EI, EE, ED, EF, EK SC, SI, SE, SD, SF, SK November 2, 2006 21610D5 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29F032B 7 D A T A S H E E T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29F032B Device Bus Operations Operation CE# OE# WE# RESET# A0–A21 DQ0–DQ7 Read L L H H AIN DOUT Write L H L H AIN DIN VCC ± 0.5 V X X VCC ± 0.5 V X High-Z TTL Standby H X X H X High-Z Output Disable L H H H X High-Z Hardware Reset X X X L X High-Z Temporary Sector Unprotect (See Note) X X X VID AIN DIN CMOS Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” on page 13 for more information. Refer to the AC Read Operations table for timing specifications and to Figure 9, on page 25 for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing 8 sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” on page 11 and “Autoselect Command Sequence” on page 14 sections for more information. ICC2 in the “DC Characteristics” on page 23 table represents the active current specification for the write mode. The ““AC Characteristics” on page 25 section Am29F032B 21610D5 November 2, 2006 D A T A contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. The Erase Resume command is valid only during the Erase Suspend mode.Refer to “Erase Suspend/Erase Resume Commands” on page 15 for more information, and to each “AC Characteristics” on page 25 section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”. S H E E T RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VIL, the device enters the TTL standby mode; if RESET# is held at VSS ± 0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the “AC Characteristics” on page 25 tables for RESET# parameters and timing diagram. I CC3 in DC Characteristics tables, represents the standby current specification. Output Disable Mode November 2, 2006 21610D5 When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29F032B 9 D A T A Table 2. S H E E T Am29F032B Sector Address Table (Sheet 1 of 2) Sector A21 A20 A19 A18 A17 A16 Sector Size Address Range SA0 0 0 0 0 0 0 64K 000000h–00FFFFh SA1 0 0 0 0 0 1 64K 010000h–01FFFFh SA2 0 0 0 0 1 0 64K 020000h–02FFFFh SA3 0 0 0 0 1 1 64K 030000h–03FFFFh SA4 0 0 0 1 0 0 64K 040000h–04FFFFh SA5 0 0 0 1 0 1 64K 050000h–05FFFFh SA6 0 0 0 1 1 0 64K 060000h–06FFFFh SA7 0 0 0 1 1 1 64K 070000h–07FFFFh SA8 0 0 1 0 0 0 64K 080000h–08FFFFh 10 SA9 0 0 1 0 0 1 64K 090000h–09FFFFh SA10 0 0 1 0 1 0 64K 0A0000h–0AFFFFh SA11 0 0 1 0 1 1 64K 0B0000h–0BFFFFh SA12 0 0 1 1 0 0 64K 0C0000h–0CFFFFh SA13 0 0 1 1 0 1 64K 0D0000h–0DFFFFh SA14 0 0 1 1 1 0 64K 0E0000h–0EFFFFh SA15 0 0 1 1 1 1 64K 0F0000h–0FFFFFh SA16 0 1 0 0 0 0 64K 100000h–10FFFFh SA17 0 1 0 0 0 1 64K 110000h–11FFFFh SA18 0 1 0 0 1 0 64K 120000h–12FFFFh SA19 0 1 0 0 1 1 64K 130000h–13FFFFh SA20 0 1 0 1 0 0 64K 140000h–14FFFFh SA21 0 1 0 1 0 1 64K 150000h–15FFFFh SA22 0 1 0 1 1 0 64K 160000h–16FFFFh SA23 0 1 0 1 1 1 64K 170000h–17FFFFh SA24 0 1 1 0 0 0 64K 180000h–18FFFFh SA25 0 1 1 0 0 1 64K 190000h–19FFFFh SA26 0 1 1 0 1 0 64K 1A0000h–1AFFFFh SA27 0 1 1 0 1 1 64K 1B0000h–1BFFFFh SA28 0 1 1 1 0 0 64K 1C0000h–1CFFFFh SA29 0 1 1 1 0 1 64K 1D0000h–1DFFFFh SA30 0 1 1 1 1 0 64K 1E0000h–1EFFFFh SA31 0 1 1 1 1 1 64K 1F0000h–1FFFFFh SA32 1 0 0 0 0 0 64K 200000h–20FFFFh SA33 1 0 0 0 0 1 64K 210000h–21FFFFh SA34 1 0 0 0 1 0 64K 220000h–22FFFFh SA35 1 0 0 0 1 1 64K 230000h–23FFFFh SA36 1 0 0 1 0 0 64K 240000h–24FFFFh SA37 1 0 0 1 0 1 64K 250000h–25FFFFh SA38 1 0 0 1 1 0 64K 260000h–26FFFFh SA39 1 0 0 1 1 1 64K 270000h–27FFFFh SA40 1 0 1 0 0 0 64K 280000h–28FFFFh SA41 1 0 1 0 0 1 64K 290000h–29FFFFh SA42 1 0 1 0 1 0 64K 2A0000h–2AFFFFh SA43 1 0 1 0 1 1 64K 2B0000h–2BFFFFh Am29F032B 21610D5 November 2, 2006 D A T A Table 2. S H E E T Am29F032B Sector Address Table (Sheet 2 of 2) Sector A21 A20 A19 A18 A17 A16 Sector Size Address Range SA44 1 0 1 1 0 0 64K 2C0000h–2CFFFFh SA45 1 0 1 1 0 1 64K 2D0000h–2DFFFFh SA46 1 0 1 1 1 0 64K 2E0000h–2EFFFFh SA47 1 0 1 1 1 1 64K 2F0000h–2FFFFFh SA48 1 1 0 0 0 0 64K 300000h–30FFFFh SA49 1 1 0 0 0 1 64K 310000h–31FFFFh SA50 1 1 0 0 1 0 64K 320000h–32FFFFh SA51 1 1 0 0 1 1 64K 330000h–33FFFFh SA52 1 1 0 1 0 0 64K 340000h–34FFFFh SA53 1 1 0 1 0 1 64K 350000h–35FFFFh SA54 1 1 0 1 1 0 64K 360000h–36FFFFh SA55 1 1 0 1 1 1 64K 370000h–37FFFFh SA56 1 1 1 0 0 0 64K 380000h–38FFFFh SA57 1 1 1 0 0 1 64K 390000h–39FFFFh SA58 1 1 1 0 1 0 64K 3A0000h–3AFFFFh SA59 1 1 1 0 1 1 64K 3B0000h–3BFFFFh SA60 1 1 1 1 0 0 64K 3C0000h–3CFFFFh SA61 1 1 1 1 0 1 64K 3D0000h–3DFFFFh SA62 1 1 1 1 1 0 64K 3E0000h–3EFFFFh SA63 1 1 1 1 1 1 64K 3F0000h–3FFFFFh Note: All sectors are 64 Kbytes in size. Autoselect Mode tection, the sector group address must appear on the appropriate highest order address bits (see Table 4 on page 12). Table 3 also shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5 on page 17. This method does not require VID on an address line. Refer to the Autoselect Command Sequence section for more information. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 3. In addition, when verifying sector group proTable 3. Am29F032B Autoselect Codes A21-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 Identifier Code on DQ7-DQ0 Manufacturer ID: AMD X X VID X VIL X VIL VIL 01h Device ID: Am29F032B X X VID X VIL X VIL VIH 41h Sector Group Protection Verification Sector Group Address X VID X VIL X VIH VIL Description 01h (protected) 00h (unprotected) Note: Identifier codes for manufacturer and device IDs exhibit odd parity with DQ7 defined as the parity bit. November 2, 2006 21610D5 Am29F032B 11 D A T A S H E E T Sector Group Protection/Unprotection Temporary Sector Group Unprotect The hardware sector group protection feature disables both program and erase operations in any sector group. Each sector group consists of four adjacent sectors. Table 4 shows how the sectors are grouped, and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID (11.5 V – 12.5 V). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once V ID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 16 shows the timing diagrams, for this feature. Sector group protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 22184. Contact an AMD representative to obtain a copy of the appropriate document. START RESET# = VID (Note 1) The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. Perform Erase or Program Operations It is possible to determine whether a sector group is protected or unprotected. See “Autoselect Mode” on page 11 for details. Table 4. Sector Group A21 Temporary Sector Group Unprotect Completed (Note 2) Sector Group Addresses A20 A19 A18 Sectors SGA0 0 0 0 0 SA0–SA3 SGA1 0 0 0 1 SA4–SA7 SGA2 0 0 1 0 SA8–SA11 SGA3 0 0 1 1 SA12–SA15 SGA4 0 1 0 0 SA16–SA19 SGA5 0 1 0 1 SA20–SA23 SGA6 0 1 1 0 SA24–SA27 SGA7 0 1 1 1 SA28–SA31 SGA8 1 0 0 0 SA32–SA35 SGA9 1 0 0 1 SA36–SA39 SGA10 1 0 1 0 SA40–SA43 SGA11 1 0 1 1 SA44–SA47 SGA12 1 1 0 0 SA48–SA51 SGA13 1 1 0 1 SA52–SA55 SGA14 1 1 1 0 SA56–SA59 SGA15 1 1 1 1 SA60–SA63 12 RESET# = VIH Notes: 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected once again. Figure 1. Am29F032B Temporary Sector Group Unprotect Operation 21610D5 November 2, 2006 D A T A Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO (see DC Characteristics for voltage levels), the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled. Under this condition the device resets to the read mode. Subsequent writes are ignored until the VCC level is greater S H E E T than VLKO. The system must ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be at VIL while OE# is at VIH. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in “AC Characteristics” on page 25. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” on page 15 for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See “Reset Command”, next. November 2, 2006 21610D5 See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Am29F032B 13 D A T A Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2 on page 10 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. Table 5 on page 17 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Table 6 on page 21 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a 14 S H E E T hardware reset immediately terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Chip Erase Command Sequence Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 5 on page 17 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. The Erase Resume command is valid only during the Erase Suspend mode. See “Erase Suspend/Erase Resume Commands” on page 15 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3, on page 16 illustrates the algorithm for the erase operation. See Figure 3, on page 16 for parameters, and to the Figure 12, on page 29 for timing waveforms. Am29F032B 21610D5 November 2, 2006 D A T A otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? The system can monitor DQ3 to determine if the sector erase timer has timed out. (See “DQ3: Sector Erase Timer” on page 20.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. No Yes No Increment Address Last Address? Programming Completed Note: See Table 5 for program command sequence. Program Operation Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 5 on page 17 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, November 2, 2006 21610D5 Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. The Erase Resume command is valid only during the Erase Suspend mode. See “Erase Suspend/Erase Resume Commands” on page 15for information on these status bits. Yes Figure 2. S H E E T Figure 3, on page 16 illustrates the algorithm for the erase operation. See Figure 3, on page 16 for parameters, and to the Figure 12, on page 29 for timing waveforms. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately ter- Am29F032B 15 D A T A minates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. The Erase Resume command is valid only during the Erase Suspend mode. See “Erase Suspend/Erase Resume Commands” on page 15 for information on these status bits. S H E E T writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. START Write Erase Command Sequence Data Poll from System After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Erase Suspend/Erase Resume Commands” on page 15 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” on page 14 for more information. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further 16 No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1. See the appropriate Command Definitions table for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information. Am29F032B Figure 3. Erase Operation 21610D5 November 2, 2006 D A T A S H E E T Command Definitions Command Sequence (Note 1) Cycles Table 5. Am29F032B Command Definitions Bus Cycles (Notes 2–4) First Second Addr Data Third Addr Data Addr Fourth Data Addr Data Read (Note 5) 1 RA RD Reset (Note 6) 1 XXX F0 4 555 AA 2AA 55 555 90 X00 01 4 555 AA 2AA 55 555 90 X01 41 555 AA 2AA 55 555 90 SGA X02 XX00 4 Manufacturer ID Autoselect Device ID (Note 7) Sector Group Protect Verify (Note 8) Fifth Sixth Addr Data Addr Data XX01 Program 4 555 AA 2AA 55 555 A0 PA PD Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend (Note 9) 1 XXX B0 Erase Resume (Note 10) 1 XXX 30 Legend: X = Don’t care PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. Notes: 1. See Table 1 on page 8 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Address bits A21–A11 are don’t cares for unlock and command cycles, unless SA or PA required. 5. No unlock or command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). November 2, 2006 21610D5 SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21–A16 select a unique sector. SGA = Address of the sector group to be verified. Address bits A21–A18 select a unique sector group. 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector group and 01h for a protected sector group.See “Autoselect Command Sequence” for more information. 9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode. Am29F032B 17 D A T A S H E E T WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 on page 21 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 6 on page 21 shows the outputs for Data# Polling on DQ7. Figure 4 shows the Data# Polling algorithm. START DQ7: Data# Polling Read DQ7–DQ0 Addr = VA The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algor ithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 2 µs, then the device returns to reading array data. DQ7 = Data? No No When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7– DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algorithms) figure in the “AC Characteristics” section illustrates this. 18 DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Yes DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am29F032B Figure 4. Data# Polling Algorithm 21610D5 November 2, 2006 D A T A RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the relationship of RY/BY# to other signals. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. November 2, 2006 21610D5 S H E E T The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC Characteristics” section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 on page 22 to compare outputs for DQ2 and DQ6. Figure 5, on page 20 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 5, on page 20 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and Am29F032B 19 D A T A the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 5). S H E E T erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6 on page 21 shows the outputs for DQ3. START Read DQ7–DQ0 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Read DQ7–DQ0 (Note 1) Toggle Bit = Toggle? No Yes No Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ5 = 1? Yes DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 µs. See also “Sector Erase Command Sequence” on page 15. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector 20 Read DQ7–DQ0 Twice Toggle Bit = Toggle? (Notes 1, 2) No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. Am29F032B Figure 5. Toggle Bit Algorithm 21610D5 November 2, 2006 D A T A S H E E T Table 6. Write Operation Status DQ7 (Note 1) DQ6 DQ5 (Note 2) DQ3 DQ2 (Note 1) RY/BY# DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase Suspended Sector 1 No toggle 0 N/A Toggle 1 Reading within Non-Erase Suspended Sector Data Data Data Data Data 1 Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0 Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information. November 2, 2006 21610D5 Am29F032B 21 D A T A S H E E T ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –55°C to +125°C 20 ns 20 ns +0.8 V Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . –2.0 V to 7.0 V –0.5 V A9, OE#, RESET# (Note 2) . . . . . –2.0 V to 13.0 V –2.0 V All other pins (Note 1) . . . . . . . . . . –2.0 V to 7.0 V 20 ns Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may overshoot VSS to – 2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on output and I/O pins is VCC + 0.5 V. During voltage transitions, outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 7. 2. Minimum DC input voltage on A9, OE#, RESET# pins is – 0.5V. During voltage transitions, A9, OE#, RESET# pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input voltage on A9, OE#, and RESET# is 13.0 V which may overshoot to 13.5 V for periods up to 20 ns. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Figure 6. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V Stresses greater than those listed in this section may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns 20 ns Figure 7. Maximum Positive Overshoot Waveform OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . –55°C to +125°C VCC Supply Voltages VCC for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V VCC for ± 10% devices . . . . . . . . . .+4.50 V to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. 22 Am29F032B 21610D5 November 2, 2006 D A T A S H E E T DC CHARACTERISTICS TTL/NMOS Compatible Parameter Symbol Parameter Description Test Description ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.0 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH ICC2 VCC Write Current (Notes 2, 3) ICC3 Min Typ Max Unit ±1.0 µA 50 µA ±1.0 µA 30 40 mA CE# = VIL, OE# = VIH 40 60 mA VCC Standby Current (CE# Controlled) CE# = VIH, RESET# = VIH 0.4 1.0 mA ICC4 VCC Standby Current (RESET# Controlled) VCC = VCC Max, RESET# = VIL 0.4 1.0 mA VIL Input Low Level –0.5 0.8 V VIH Input High Level 2.0 VCC + 0.5 V VID Voltage for Autoselect and Sector VCC = 5.0 V Protect 11.5 12.5 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V VOH Output High Level IOH = –2.5 mA VCC = VCC Min VLKO Low VCC Lock-out Voltage 2.4 V 3.2 4.2 V Max Unit CMOS Compatible Parameter Symbol Parameter Description Test Description Min Typ ±1.0 µA 50 µA ±1.0 µA 30 40 mA CE# = VIL, OE# = VIH 30 40 mA VCC Standby Current (CE# Controlled) CE# = VCC ± 0.5 V, RESET# = VCC ± 0.5 V 1 5 µA ICC4 VCC Standby Current (RESET# Controlled) RESET# = VSS ± 0.5 V 1 5 µA VIL Input Low Level –0.5 0.8 V VIH Input High Level 0.7x VCC VCC + 0.3 V VID Voltage for Autoselect and Sector Protect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.0 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ICC1 VCC Read Current (Note 1) CE# = VIL, OE# = VIH ICC2 VCC Write Current (Notes 2, 3) ICC3 VOH1 VOH2 VLKO Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V IOH = –100 µA, VCC = VCC Min VCC – 0.4 V Low VCC Lock-out Voltage 3.2 4.2 V Notes for DC Characteristics (both tables): 1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Program or Embedded Erase algorithm is in progress. 3. Not 100% tested. November 2, 2006 21610D5 Am29F032B 23 D A T A S H E E T TEST CONDITIONS Table 7. 5.0 V Test Specifications Test Condition 2.7 kΩ Device Under Test CL -75 Output Load 6.2 kΩ Figure 8. Test Setup Unit 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 100 pF Input Rise and Fall Times 5 20 ns 0.0–3.0 0.45–2.4 V Input timing measurement reference levels 1.5 0.8 V Output timing measurement reference levels 1.5 2.0 V Input Pulse Levels Note: Diodes are IN3064 or equivalent All others KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 24 Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) Am29F032B 21610D5 November 2, 2006 D A T A S H E E T AC CHARACTERISTICS Read-only Operations Parameter Symbol Speed Options JEDEC Std Parameter Description tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE Output Enable to Output Delay tOEH Output Enable Hold Time (Note 1) Test Setup -75 -90 Unit Min 70 90 ns CE# = VIL OE# = VIL Max 70 90 ns OE# = VIL Max 70 90 ns Max 40 40 ns Read Min 0 ns Toggle and Data# Polling Min 10 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 20 20 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 20 20 ns tAXQX tOH Output Hold Time From Addresses CE# or OE# Whichever Occurs First Min 0 ns RESET# Pin Low to Read Mode (Note 1) Max 20 µs tReady Notes: 1. Not 100% tested. 2. Refer to Figure 8 and Table 7 for test specifications. tRC Addresses Stable Addresses tACC CE# tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 9. November 2, 2006 21610D5 Read Operation Timings Am29F032B 25 D A T A S H E E T AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH RESET# High Time Before Read (See Note) Min 50 ns tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 10. 26 RESET# Timings Am29F032B 21610D5 November 2, 2006 D A T A S H E E T AC CHARACTERISTICS Write (Erase/Program) Operations Parameter Speed Options JEDEC Std Parameter Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min tWLAX tAH Address Hold Time Min 40 45 ns tDVWH tDS Data Setup Time Min 40 45 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recover Time Before Write (OE# high to WE# low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs Typ 1 sec tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Max 8 sec 50 µs tVCS VCC Set Up Time (Note 1) Min tBUSY WE# to RY/BY# Valid Max -75 -90 Unit 70 90 ns 0 40 40 ns 45 40 ns ns Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. November 2, 2006 21610D5 Am29F032B 27 D A T A S H E E T AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses 555h Read Status Data (last two cycles) PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status tBUSY DOUT tRB RY/BY# tVCS VCC Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 11. 28 Program Operation Timings Am29F032B 21610D5 November 2, 2006 D A T A S H E E T AC CHARACTERISTICS tAS tWC 2AAh Addresses VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Note: SA = Sector Address. VA = Valid Address for reading status data. Figure 12. November 2, 2006 21610D5 Chip/Sector Erase Operation Timings Am29F032B 29 D A T A S H E E T AC CHARACTERISTICS tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ0–DQ6 Status Data Status Data Valid Data True High Z Valid Data True tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 13. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ6/DQ2 tBUSY Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 14. 30 Toggle Bit Timings (During Embedded Algorithms) Am29F032B 21610D5 November 2, 2006 D A T A S H E E T AC CHARACTERISTICS Enter Embedded Erasing Erase Suspend Erase WE# Enter Erase Suspend Program Erase Resume Erase Suspend Program Erase Suspend Read Erase Suspend Read Erase Complete Erase DQ6 DQ2 Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector. Figure 15. DQ2 vs. DQ6 Temporary Sector Unprotect Parameter JEDEC Std Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect All Speed Options Unit Min 500 ns Min 4 µs Note: Not 100% tested. 12 V RESET# 0 or 5 V 0 or 5 V tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP RY/BY# Figure 16. Temporary Sector Group Unprotect Timings November 2, 2006 21610D5 Am29F032B 31 D A T A S H E E T AC CHARACTERISTICS Write (Erase/Program) Operations—Alternate CE# Controlled Writes Parameter Symbol Speed Options JEDEC Std Parameter Description -75 -90 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 ns tAVEL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 40 45 ns tDVEH tDS Data Setup Time Min 40 45 ns tEHDX tDH Address Hold Time Min 0 ns tGHEL tGHEL Read Recover Time Before Write Min 0 ns tWLEL tWS CE# Setup Time Min 0 ns tEHWH tWH CE# Hold Time Min 0 ns tELEH tCP Write Pulse Width Min tEHEL tCPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs Typ 1 sec tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Max 8 sec 0 40 ns 45 ns Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 32 Am29F032B 21610D5 November 2, 2006 D A T A S H E E T AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. Figure 17. November 2, 2006 21610D5 Alternate CE# Controlled Write Operation Timings Am29F032B 33 D A T A S H E E T ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Sector Erase Time 1 8 sec Chip Erase Time 64 Byte Programming Time 7 300 µs 28.8 86.4 sec Chip Programming Time (Note 3) sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles (4.75 V for -75). 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 5 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTIC Description Input Voltage with respect to VSS on I/O pins VCC Current Min Max –1.0 V VCC + 1.0 V –100 mA +100 mA Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time. TSOP AND SO PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Min Max Unit 6 7.5 pF Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF CIN Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time 34 Am29F032B 21610D5 November 2, 2006 D A T A S H E E T PHYSICAL DIMENSIONS SO 044–44-Pin Small Outline Package Dwg rev AC; 10/99 November 2, 2006 21610D5 Am29F032B 35 D A T A S H E E T PHYSICAL DIMENSIONS TS 040–40-Pin Standard Thin Small Outline Package Dwg rev AA; 10/99 36 Am29F032B 21610D5 November 2, 2006 D A T A S H E E T REVISION SUMMARY Revision A (June 1998) Revision D+1 (December 5, 2000) Initial release. Added table of contents. Revision B (July 1998) Ordering Information Distinctive Characteristics Deleted burn-in option. Changed typical active read current to 30 mA to match DC Characteristics table. Revision D+2 (November 8, 2004) Operating Ranges Added cover page, colophon, and referenced links Corrected temperature range descriptions to “ambient.” Global Updated Trademark. Revision C (January 1999) Ordering Information Distinctive Characteristics Added temperature range for Pb-free Packages. Added 20-year data retention subbullet. Valid Combinations Revision C+1 (April 14, 1999) Added new combinations. Deleted duplicate sections in the full data sheet. Revision D3 (December 22, 2005) Data Retention Global Added table. Deleted 120 and 150 ns speed options, and deleted reverse TSOP package option. Revision D (November 17, 1999) AC Characteristics—Figure 11. Program Operations Timing and Figure 12. Chip/Sector Erase Operations Revision D4 (May 19, 2006) Deleted tGHWL and changed OE# waveform to start at high. AC Characteristics Physical Dimensions Revision D5 (November 2, 2006) Replaced figures with more detailed illustrations. Added “Not recommended for new designs” note. Changed tBUSY specification to maximium value. Deleted “Not recommended for new designs” note. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those pr Trademarks Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 2, 2006 21610D5 Am29F032B 37