MC1489, MC1489A Quad Line EIA−232D Receivers The MC1489 monolithic quad line receivers are designed to interface data terminal equipment with data communications equipment in conformance with the specifications of EIA Standard No. EIA−232D. http://onsemi.com Features • • • • • Input Resistance − 3.0 k to 7.0 k Input Signal Range − ± 30 V Input Threshold Hysteresis Built In Response Control a) Logic Threshold Shifting b) Input Noise Filtering Pb−Free Packages are Available SOIC−14 D SUFFIX CASE 751A 14 1 PDIP−14 P SUFFIX CASE 646 14 1 SOEIAJ−14 M SUFFIX CASE 965 14 1 PIN CONNECTIONS Interconnecting Cable Line Driver MC1488 MDTL Logic Input Interconnecting Cable Line Receiver MC1489 MDTL Logic Output Input A 1 14 VCC Response Control A 2 13 Input D Output A 3 12 Response Control D Input B 4 11 Output D Response Control B 5 10 Input C Output B 6 9 Response Control C Ground 7 8 Output C Figure 1. Simplified Application ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 8 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 8 1 Publication Order Number: MC1489/D MC1489, MC1489A 14 VCC 9.0 k 5.0 k 1.7 k RF Response Control 2 3 Output 3.8 k Input 1 RF MC1489 MC1489A 6.7 k 1.6 k 10 k 7 GND Figure 2. Representative Schematic Diagram (1/4 of Circuit Shown) http://onsemi.com 2 MC1489, MC1489A MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted) Rating Symbol Value Unit Power Supply Voltage VCC 10 Vdc Input Voltage Range VIR ± 30 Vdc Output Load Current IL 20 mA PD 1/JA 1000 6.7 mW mW/°C Operating Ambient Temperature Range TA 0 to + 75 °C Storage Temperature Range Tstg − 65 to + 175 °C Power Dissipation (Package Limitation, SOIC−14 and Plastic Dual In−Line Package) Derate above TA = + 25°C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. ELECTRICAL CHARACTERISTICS (Response control pin is open.) (VCC = + 5.0 Vdc ± 10%, TA = 0 to + 75°C, unless otherwise noted) Characteristics Symbol Min Typ Max Unit Positive Input Current (VIH = + 25 Vdc) (VIH = + 3.0 Vdc) IIH 3.6 0.43 − − 8.3 − mA Negative Input Current (VIH = − 25 Vdc) (VIH = − 3.0 Vdc) IIL − 3.6 − 0.43 − − − 8.3 − mA 1.0 1.75 − 1.95 1.5 2.25 0.75 0.75 − 0.8 1.25 1.25 Input Turn−On Threshold Voltage (TA = + 25°C, VOL 0.45 V) VIH MC1489 MC1489A Input Turn−Off Threshold Voltage (TA = + 25°C, VOH 2.5 V, IL = − 0.5 mA) Vdc VIL MC1489 MC1489A Vdc Output Voltage High (VIH = 0.75 V, IL = − 0.5 mA) (Input Open Circuit, IL = − 0.5 mA) VOH 2.5 2.5 4.0 4.0 5.0 5.0 Vdc Output Voltage Low (VIL = 3.0 V, IL = 10 mA) VOL − 0.2 0.45 Vdc Output Short−Circuit Current IOS − − 3.0 − 4.0 mA Power Supply Current (All Gates “on,” Iout = 0 mA, VIH = + 5.0 Vdc) ICC − 16 26 mA Power Consumption PC − 80 130 mW tPLH − 25 85 ns (VIH = + 5.0 Vdc) SWITCHING CHARACTERISTICS (VCC = 5.0 Vdc ± 1%, TA = + 25°C, See Figure 3.) Propagation Delay Time (RL = 3.9 k) Rise Time (RL = 3.9 k) tTLH − 120 175 ns Propagation Delay Time (RL = 390 k) tPHL − 25 50 ns Fall Time (RL = 390 k) tTHL − 10 20 ns http://onsemi.com 3 MC1489, MC1489A TEST CIRCUITS 5.0 Vdc RL All diodes 1N3064 or equivalent Ein VR Eo R CL 3.0 V 50% 50% C Ein tPLH EO tTHL tTLH and tTHL measured 10% − 90% Vin tTLH 1.5 V 1/4 MC1489A Response Node 1.5 V CL = 15 pF = total parasitic capacitance which includes probe and wiring capacitances C, capacitor is for noise filtering. R, resistor is for threshold shifting. Figure 3. Switching Response Figure 4. Response Control Node http://onsemi.com 4 VO MC1489, MC1489A TYPICAL CHARACTERISTICS (VCC = 5.0 Vdc, TA = +25°C, unless otherwise noted) 10 6.0 5.0 6.0 VO , OUTPUT VOLTAGE (Vdc) IL, INPUT CURRENT (mA) 8.0 4.0 2.0 0 −2.0 II −4.0 VI −6.0 −8.0 −10 −25 −20 −15 −10 −5.0 0 5.0 10 15 20 25 VI 4.0 RT 5.0 k 3.0 Vth 5.0 V 2.0 RT 13 k Vth 5.0 V 0 −3.0 −2.0 −1.0 VIH , INPUT THRESHOLD VOLTAGE (Vdc) EO RT 11 k Vth −5.0 V RT Vth 1.0 0 −3.0 −2.0 VILH −1.0 0 1.0 VIHL 2.0 3.0 0 1.0 2.0 3.0 4.0 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 −60 MC1489A VIH MC1489 VIH MC1489 VIL MC1489A VIL 0 +60 VI, INPUT VOLTAGE (V) T, TEMPERATURE (°C) Figure 7. MC1489A Input Threshold Voltage Adjustment Figure 8. Input Threshold Voltage versus Temperature 2.0 INPUT THRESHOLD VOLTAGE (Vdc) VO , OUTPUT VOLTAGE (Vdc) Vin 2.0 Vth Figure 6. MC1489 Input Threshold Voltage Adjustment 5.0 RT RT VI, INPUT VOLTAGE (V) 6.0 RT 5.0 k Vth 5.0 V 1.0 VIH MC1489A VIH MC1489 VIL MC1489 VIL MC1489A 0 3.0 EO VILH VIHL Figure 5. Input Current 3.0 RT 11 k Vth −5.0 V 1.0 Vin, INPUT VOLTAGE (V) 4.0 RT 4.0 5.0 VCC, POWER SUPPLY VOLTAGE (V) Figure 9. Input Threshold versus Power Supply Voltage http://onsemi.com 5 6.0 +120 MC1489, MC1489A APPLICATIONS INFORMATION General Information turn−on voltage of 1.25 V and turn−off of 1.0 V for a typical hysteresis of 250 mV. The MC1489A has typical turn−on of 1.95 V and turn−off of 0.8 V for typically 1.15 V of hysteresis. Each receiver section has an external response control node in addition to the input and output pins, thereby allowing the designer to vary the input threshold voltage levels. A resistor can be connected between this node and an external power supply. Figures 4, 6 and 7 illustrate the input threshold voltage shift possible through this technique. This response node can also be used for the filtering of high frequency, high energy noise pulses. Figures 10 and 11 show typical noise pulse rejection for external capacitors of various sizes. These two operations on the response node can be combined or used individually for many combinations of interfacing applications. The MC1489 circuits are particularly useful for interfacing between MOS circuits and MDTL/MTTL logic systems. In this application, the input threshold voltages are adjusted (with the appropriate supply and resistor values) to fall in the center of the MOS voltage logic levels (see Figure 12). The response node may also be used as the receiver input as long as the designer realizes that he may not drive this node with a low impedance source to a voltage greater than one diode above ground or less than one diode below ground. This feature is demonstrated in Figure 13 where two receivers are slaved to the same line that must still meet the EIA−232D impedance requirement. The Electronic Industries Association (EIA) has released the EIA−232D specification detailing the requirements for the interface between data processing equipment and data communications equipment. This standard specifies not only the number and type of interface leads, but also the voltage levels to be used. The MC1488 quad driver and its companion circuit, the MC1489 quad receiver, provide a complete interface system between DTL or TTL logic levels and the EIA−232D defined levels. The EIA−232D requirements as applied to receivers are discussed herein. The required input impedance is defined as between 3000 and 7000 for input voltages between 3.0 and 25 V in magnitude; and any voltage on the receiver input in an open circuit condition must be less than 2.0 V in magnitude. The MC1489 circuits meet these requirements with a maximum open circuit voltage of one VBE. The receiver shall detect a voltage between − 3.0 and −25 V as a Logic “1” and inputs between 3.0 and 25 V as a Logic “0.” On some interchange leads, an open circuit of power “OFF” condition (300 or more to ground) shall be decoded as an “OFF” condition or Logic “1.” For this reason, the input hysteresis thresholds of the MC1489 circuits are all above ground. Thus an open or grounded input will cause the same output as a negative or Logic “1” input. Device Characteristics The MC1489 interface receivers have internal feedback from the second stage to the input stage providing input hysteresis for noise rejection. The MC1489 input has typical 6 6 MC1489A MC1489 10 pF 100 pF 300 pF 5 500 pF E in , AMPLITUDE (V) E in , AMPLITUDE (V) 5 4 3 12 pF 100 pF 300 pF 4 500 pF 3 2 2 1 1 10 100 1000 10 10,000 100 1000 10,000 PW, INPUT PULSE WIDTH (ns) PW, INPUT PULSE WIDTH (ns) Figure 10. Typical Turn On Threshold versus Capacitance from Response Control Pin to GND Figure 11. Typical Turn On Threshold versus Capacitance from Response Control Pin to GND http://onsemi.com 6 MC1489, MC1489A +5.0 Vdc R MC1489 MOS Logic −VGG DTL or TTL −VDD +5.0 Vdc +5.0 Vdc Figure 12. Typical Translator Application − MOS to DTL or TTL VCC Response−Control Pin Input 1/2 MC1489 Output 8.0 k VCC Input Output 8.0 k Response−Control Pin Figure 13. Typical Paralleling of Two MC1489, A Receivers to Meet EIA−232D http://onsemi.com 7 MC1489, MC1489A ORDERING INFORMATION Device Package Operating Temperature Range Shipping MC1489D 55 Units/Rail MC1489DR2 2500 Tape & Reel SOIC−14 SO C MC1489AD 55 Units/Rail MC1489ADG SOIC−14 (Pb−Free) 55 Units/Rail MC1489ADR2 SOIC−14 2500 Tape & Reel MC1489ADR2G SOIC−14 (Pb−Free) 2500 Tape & Reel MC1489P PDIP−14 25 Units/Rail MC1489PG PDIP−14 (Pb−Free) MC1489AP PDIP−14 25 Units/Rail SOEIAJ−14 SO J 2000 Tape & Reel TA = 0 to +75°C 25 Units/Rail TA = 0 to +75°C MC1489M 50 Units/Rail MC1489MEL MC1489AM 50 Units/Rail MC1489AM SOEIAJ−14 (Pb−Free) 50 Units/Rail MC1489AMEL SOEIAJ−14 2000 Tape & Reel MC1489AMEL SOEIAJ−14 (Pb−Free) 2000 Tape & Reel TA = 0 to +75°C MARKING DIAGRAMS SOIC−14 D SUFFIX CASE 751A 14 14 MC1489AD AWLYWW 1 PDIP−14 P SUFFIX CASE 646 14 MC1489D AWLYWW 14 MC1489AP AWLYYWW 1 1 1 SOEIAJ−14 M SUFFIX CASE 965 MC1489 ALYW MC1489A ALYW A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 8 MC1489P AWLYYWW MC1489, MC1489A PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− 1 P 7 PL 0.25 (0.010) 7 G M B M F R X 45 C −T− SEATING PLANE 0.25 (0.010) M J M K D 14 PL T B S A DIM A B C D F G J K M P R S MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 PDIP−14 P SUFFIX CASE 646−06 ISSUE M 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F L N C −T− SEATING PLANE J K H G D 14 PL 0.13 (0.005) M M http://onsemi.com 9 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 0.38 1.01 MC1489, MC1489A PACKAGE DIMENSIONS SOEIAJ−14 M SUFFIX CASE 965−01 ISSUE O 14 LE 8 Q1 E HE L 7 1 M DETAIL P Z D VIEW P A e c 0.13 (0.005) DIM A A1 b c D E e HE 0.50 LE M Q1 Z A1 b M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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