AP7217C 1.25V 600mA CMOS LDO General Description Features • • • • • • • • • • • The AP7217C low-dropout linear regulator operates from a 2.5V to 5.5V supply and delivers a guaranteed 600mA (min) continuous load current. Very Low Dropout Voltage Low Current Consumption: Typ. 40µA Output Voltage: 1.25V Guaranteed 600mA (min) Output Input Range up to 5.5V Current Limiting Stability with Low ESR Capacitors Thermal shutdown Protection Low Temperature Coefficient SOP-8L-EP: Available in “Green” Molding Compound (No Br, Sb) Lead Free Finish / RoHS Compliant (Note 1) The space-saving SOP-8L-EP package is suitable for “pocket” and hand-held applications. Applications • • • • CD and MP3 Players Cellular and PCS Phones Digital Still Camera Hand-Held Computers Typical Application U1 4 VIN VIN VOUT 2 VOUT AP7217C ON CIN 1uF GND EN 8 OFF COUT 1uF 7 AP7217C Rev. 3 DS31424 1 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Ordering Information AP 7217C - 13 SP G - 13 Output voltage 13 : 1.25V Device AP7217C-13SPG-13 Notes: Package Green Packing SP : SOP-8L-EP G : Green 13 : Tape & Reel Package Code SP Packaging (Note 2) SOP-8L-EP 13” Tape and Reel Quantity Part Number Suffix 2500/Tape & Reel -13 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html. 2. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. Pin Assignments (1) SOP-8L-EP ( Top View ) GND 1 8 EN VOUT 2 7 GND GND 3 6 GND VIN 4 5 GND SOP-8L-EP Pin Descriptions Pin Name Pin No. GND VOUT VIN EN 1, 3, 5, 6, 7 2 4 8 AP7217C Rev. 3 DS31424 Description Ground Voltage Output Supply Voltage High Enable 2 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Block Diagram EN Enable VIN On Off - Bandgap ERROR AMP Current Limit + VOUT R1 R2 GND Absolute Maximum Ratings Symbol Parameter Rating Unit ESD HBM Human Body Model ESD Protection 3.5 KV ESD MM Machine Model ESD Protection 500 V +6 PD/ (VIN-VO) V mA 1650 mW -40 to +125 ºC VIN IOUT Input Voltage Output Current PD Power Dissipation TJ Operating Junction Temperature Range SOP-8L-EP Recommended Operating Conditions Symbol VIN IOUT TA AP7217C Rev. 3 DS31424 Parameter Input Voltage Output Current Operating Ambient Temperature 3 of 9 www.diodes.com Min 2.5 0 -40 Max 5.5 600 85 Unit V mA ºC OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Electrical Characteristics (TA = 25°C, CIN= 1µF, COUT= 1µF, VEN= VIN, unless otherwise noted) Symbol IQ ISTB Standby Current VOUT Output Voltage Accuracy VOUT Temperature Coefficient VDROPOUT IOUT ILIMIT ISHORT ∆VLINE/∆VIN/VOUT ∆VOUT PSRR VEH VEL IEN θJA θJC Notes: Parameter Quiescent Current Dropout Voltage Test Conditions IO = 0mA VEN = Off VIN = 5.0V IO = 30mA, VIN = 5V Min - 1.225 Typ. 40 Max 60 Unit µA 2 5 µA 1.25 1.275 V -40°C to 85°C, IOUT = 30mA ±100 IOUT = 100mA, VOUT = 1.25V 1250 IOUT = 600mA, VOUT = 1.25V 2000 Maximum Output Current Current Limit Short Circuit Current Line Regulation Load Regulation VIN = 5.3V VIN = 5.3V 4.3V ≤ VIN ≤ 5.5V; IOUT = 30mA 1mA ≤ IOUT ≤ 100mA, VIN = 5.3V Power Supply Rejection VIN = 4.3V+ 0.5Vp-pAC, F = 1KHz IOUT = 50mA EN Input Threshold Output ON Output OFF VIN = 5.3V Enable Pin Current Thermal Resistance SOP-8L-EP (Note 3) Junction-to-Ambient Thermal Resistance SOP-8L-EP (Note 3) Junction-to-Case ppm / oC mV 600 mA 750 70 0.01 10 ±0.2 20 55 dB 1.6 0.25 0.1 -0.1 mA mA %/V mV V V µA 82 ºC/W 12 ºC/W 3. Test condition for SOP-8L-EP: Device mounted on 2oz copper, minimum recommended pad layout on top & bottom layer with thermal vias, double sided FR-4 PCB. AP7217C Rev. 3 DS31424 4 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Typical Performance Characteristics Output Current vs. Dropout Voltage (Vout=1.25V) Input Voltage vs. Max Iout (Vout=1.25V) 2500 800 600 Max Iout (mA Dropout Voltage (mV 700 2000 1500 1000 500 400 300 200 500 100 0 0 100mA 200mA 300mA 400mA 500mA 600mA 2.5V 3V Output Current 5V 5.5V Input Voltage Quiescent Current vs. Tem perature Quiescent Current vs Input Voltage 55 Quiescent Current (uA) 55 Quiescent Current (uA) 4V 50 45 40 35 30 25 50 45 40 35 30 25 2.5V 3V 4V 5V 5.5V Input Voltage AP7217C Rev. 3 DS31424 -40℃ 0℃ 25℃ 85℃ 100℃ 120℃ Tem perature 5 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Typical Performance Characteristics (Continued) Load Transient Response (VOUT =1.25V) Load Transient Response (VOUT =1.25V) AP7217C Rev. 3 DS31424 6 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Application Note Input Capacitor A 1µF ceramic capacitor is recommended to connect between IN and GND pins to decouple input power supply glitch and noise. The amount of the capacitance may be increased without limit. A lower ESR (Equivalent Series Resistance) capacitor allows the use of less capacitance, while higher ESR type requires more capacitance. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both IN and GND. Thermal Considerations Thermal Shutdown Protection limits power dissipation in AP7217C. When the operation junction temperature exceeds 140°C, the Over Temperature Protection circuit starts the thermal shutdown function and turns the pass element off. The pass element turn on again after the junction temperature cools by 30°C. For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is: Output Capacitor The output capacitor is required to stabilize and help the transient response of the LDO. The AP7217C is designed to have excellent transient response for most applications with a small amount of output capacitance. The AP7217C is stable with any small ceramic output capacitors of 1.0µF or higher value, and the temperature coefficients of X7R or X5R type. Additional capacitance helps to reduce undershoot and overshoot during transient. For PCB layout, the output capacitor must be placed as close as possible to OUT and GND pins, and keep the leads as short as possible. PD = (VIN − VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junctions to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) - TA ) / θJA Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. Vin Iout Iin C Vout OUT IN AP7217C Co GND ESR Iq ENABLE/SHUTDOWN Operation The AP7217C (SOP-8L-EP) is turned on by setting the EN pin high, and is turned off by pulling it low. If this feature is not used, the EN pin should be tied to IN pin to keep the regulator output on at all time. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. AP7217C Rev. 3 DS31424 Current Limit Protection When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to approximately 750mA to prevent over-current and to protect the regulator from damage due to overheating. Short circuit protection When VOUT pin is shorted to GND or VOUT voltage is less than 200mV, short circuit protection will be triggered and clamp the output current to approximately 70mA. 7 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO Marking Information (1) SOP-8L-EP ( Top View ) 5 8 G : Green YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal Code SOP-8L-EP Logo 7217C-13 YY WW X X E Part No. 7217C-13 : for 1.25V 1 Package Information 4 (All Dimensions in mm) (1) Package Type: SOP-8L-EP Detail "A" Exposed pad 2.4Ref. 3.70/4.10 45° 0.35max. 3.85/3.95 5.90/6.10 7°~9° 7°~9° 1 1 0.15/0.25 Bottom View 1.75max. 1.30/1.50 3.3Ref. 0/0.13 0.254 0.3/0.5 1.27typ 4.85/4.95 1 Gauge Plane Seating Plane 0.62/0.82 Detail "A" 8x-0.60 5.4 Exposed pad 8x-1.55 6x-1.27 Land Pattem Recommendation (Unit:mm) AP7217C Rev. 3 DS31424 8 of 9 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217C 1.25V 600mA CMOS LDO IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDING TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 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