MC10H602, MC100H602 9−Bit Latch TTL to ECL Translator Description The MC10H/100H602 is a 9−bit, dual supply TTL to ECL translator with latch. Devices in the ON Semiconductor 9−bit translator series utilize the PLCC−28 for optimal power pinning, signal flow−through and electrical performance. The H602 features D−type latches. Latching is controlled by Latch Enable (LEN), while the Master Reset input resets the latches. A post−latch logic enable is also provided (ENECL), allowing control of the output state without destroying latch data. All control inputs are ECL level. The 10H version is compatible with MECL 10Ht ECL logic levels. The 100H version is compatible with 100K levels. http://onsemi.com PLCC−28 FN SUFFIX CASE 776 Features • 9−Bit Ideal for Byte−Parity Applications • Flow−Through Configuration • Extra TTL and ECL Power/Ground Pins to Minimize • • • • MARKING DIAGRAM* Switching Noise Dual Supply 3.5 ns Max D to Q PNP TTL Inputs for Low Loading Pb−Free Packages are Available* 1 MCxxxH602G AWLYYWW xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 10 1 Publication Order Number: MC10H602/D MC10H602, MC100H602 D5 D4 VCCT D3 25 24 23 22 D2 D1 D0 21 20 Table 1. PIN NAMES 19 D6 26 18 Q0 PIN D7 27 17 Q1 D8 28 16 VCCE 15 VCCO GND VCCE VCCO VCCT VEE D0 −D8 Q0 −Q8 ENECL LEN MR GND MR 2 14 Q2 LEN 3 13 VCCO ENECL 4 12 Q3 5 6 7 8 9 Q8 Q7 VCCO Q6 VEE 10 11 Q5 Q4 FUNCTION TTL Ground (0 V) ECL VCC (0 V) ECL VCC (0 V) — Outputs TTL Supply (+ 5.0 V) ECL Supply (− 5.2 / −4.5 V) Data Inputs (TTL) Data Outputs (ECL) Enable Control (ECL) Latch Enable (ECL) Master Reset (ECL) Figure 1. PLCC−28 Pinout (Top View) ENECL DQ EN Q0 D1 DQ EN Q1 D2 DQ EN Q2 D3 DQ EN Q3 D4 DQ EN Q4 D5 DQ EN Q5 D6 DQ EN Q6 D7 DQ EN Q7 D8 DQ EN Q8 D0 TTL Table 2. TRUTH TABLE D LEN MR ENECL Q L H X X X L L H X X L L L H X H H H H L L H Q0 L L ECL LEN MR Figure 2. LOGIC SYMBOL Table 3. DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = − 5.2 V ± 5% (10H version); VEE = − 4.2 V to − 5.5 V (100H version) 0°C Symbol Min Parameter 25°C Max Min 75°C Max Min Max Unit Power Supply Current IEE ECL ICCH ICCL TTL 10H 100H −125 −122 −125 −123 −125 −132 mA 48 50 48 50 48 50 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 2 MC10H602, MC100H602 Table 4. 10H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = − 5.2 V ± 5% 0°C Symbol Parameter Min Condition 25°C Max 75°C Max 175 Min Max Unit 175 mA mA IINH IINL Input HIGH Current Input LOW Current 0.5 VIH VIL Input HIGH Voltage Input LOW Voltage −1170 −1950 −840 −1480 −1130 −1950 −810 −1480 −1070 −1950 −735 −1450 mV VOH VOL Output HIGH Voltage Output LOW Voltage −1020 −1950 −840 −1630 −980 −1950 −810 −1630 −920 −1950 −735 −1600 mV 50 W to − 2.0 V 255 Min 0.5 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 5. 100H ECL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = − 4.2 V to − 5.5 V 0°C Symbol Parameter Min Condition 25°C Max Min Max IINH IINL Input HIGH Current Input LOW Current 0.5 VIH VIL Input HIGH Voltage Input LOW Voltage −1165 −1810 −880 −1475 −1165 −1810 −880 −1475 VOH VOL Output HIGH Voltage Output LOW Voltage −1025 −1810 −880 −1620 −1025 −1810 −880 −1620 50 W to − 2.0 V 255 75°C 175 0.5 Min Max Unit 175 mA mA −1165 −1810 −880 −1475 mV −1025 −1810 −880 −1620 mV 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 6. TTL DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = − 5.2 V ± 5% (10H version); VEE = − 4.2 V to − 5.5 V (100H version) 0°C Symbol Parameter Min Condition 2.0 25°C Max Min Max Min Unit 0.8 V V Input HIGH Voltage Input LOW Voltage IIH Input HIGH Current VIN = 2.7 V VIN = 7.0 V 20 100 20 100 20 100 mA IIL Input LOW Current VIN = 0.5 V −0.6 −0.6 −0.6 mA VIK Input Clamp Voltage IIN = −18 mA −1.2 −1.2 −1.2 V 0.8 2.0 Max VIH VIL 0.8 2.0 75°C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 3 MC10H602, MC100H602 Table 7. AC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = − 5.2 V ± 5% (10H version); VEE = − 4.2 V to − 5.5 V (100H version) 0°C Symbol Parameter D LEN MR ENECL 25°C 75°C Min Max Min Max Min Max Unit 1.4 2.0 2.0 1.6 3.0 3.4 3.4 3.2 1.5 2.1 2.1 1.7 3.2 3.5 3.5 3.3 1.7 2.4 2.5 1.8 3.5 3.7 3.9 3.7 ns tPLH tPHL Propagation Delay to Output ts Set−Up Time, D to LEN 2.0 2.0 2.0 ns th Hold Time, D to LEN 1.0 1.0 1.0 ns tw(L) LEN Pulse Width, LOW 2.0 2.0 2.0 ns tR tF Output Rise/Fall Time 20% −80% 0.5 1.5 0.5 1.5 0.5 1.5 ns NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. ORDERING INFORMATION Package Shipping † MC10H602FN PLCC−28 37 Units / Rail MC10H602FNG PLCC−28 (Pb−Free) 37 Units / Rail MC10H602FNR2 PLCC−28 500 / Tape & Reel MC10H602FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel MC100H602FN PLCC−28 37 Units / Rail MC100H602FNG PLCC−28 (Pb−Free) 37 Units / Rail MC100H602FNR2 PLCC−28 500 / Tape & Reel MC100H602FNR2G PLCC−28 (Pb−Free) 500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 4 MC10H602, MC100H602 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776−02 ISSUE E −N− 0.007 (0.180) B Y BRK T L−M M 0.007 (0.180) U M N S T L−M S S N S D Z −M− −L− W 28 D X V 1 A 0.007 (0.180) R 0.007 (0.180) C M M T L−M T L−M S S N S N S 0.007 (0.180) H N S S G J 0.004 (0.100) −T− SEATING T L−M S N T L−M S N S K PLANE F VIEW S G1 M K1 E S T L−M S VIEW D−D Z 0.010 (0.250) 0.010 (0.250) G1 VIEW S S NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM −T−, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 −−− 0.025 −−− 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 −−− 0.020 2_ 10_ 0.410 0.430 0.040 −−− http://onsemi.com 5 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 −−− 0.64 −−− 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 −−− 0.50 2_ 10_ 10.42 10.92 1.02 −−− 0.007 (0.180) M T L−M S N S MC10H602, MC100H602 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). MECL 10H is a trademark of Motorola, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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