ONSEMI MC74HCT74ADR2G

MC74HCT74A
Dual D Flip−Flop with Set
and Reset with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
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MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
14
1
1
Features
•
•
•
•
•
•
•
•
MC74HCT74AN
AWLYYWWG
14
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 136 FETs or 34 Equivalent Gates
Pb−Free Packages are Available
1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
A
L, WL
Y, YY
W, WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN ASSIGNMENT
1
2
5
3
6
Q1
RESET 1
1
14
VCC
DATA 1
2
13
RESET 2
CLOCK 1
3
12
DATA 2
SET 1
4
11
CLOCK 2
Q1
5
10
SET 2
Q1
6
9
Q2
GND
7
8
Q2
Q1
4
13
PIN 14 = VCC
PIN 7 = GND
12
9
11
8
FUNCTION TABLE
Inputs
Q2
Q2
10
Design Criteria
Value
Units
Internal Gate Count†
34
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
.0075
pJ
Speed Power Product
Outputs
Set Reset Clock Data
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SET 2
HCT74AG
AWLYWW
1
LOGIC DIAGRAM
RESET 1
SOIC−14
D SUFFIX
CASE 751A
14
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
L
H
X
X
X
H
L
X
X
X
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
†Equivalent to a two−input NAND gate.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 10
1
Publication Order Number:
MC74HCT74A/D
MC74HCT74A
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
750
500
mW
– 65 to + 150
_C
PD
Power Dissipation in Still Air
Tstg
Storage Temperature
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: –10mW/_C from 65_ to 125_C
SOIC Package: –7mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout| v 4.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout| v 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| v 4.0 mA
4.5
0.26
0.33
0.4
VOL
Maximum Low−Level Output
Voltage
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
5.5
2.0
20
80
mA
DICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 mA
≥ −55_C
25_C to 125_C
2.9
2.4
5.5
mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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2
MC74HCT74A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25_C
v 85_C
v 125_C
Unit
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Symbol
Parameter
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
24
30
36
ns
tPLH,
tPHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
24
30
36
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
Maximum Input Capacitance
10
10
10
pF
Cin
2. For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
32
Power Dissipation Capacitance (Per Enabled Output)*
3. Used to determine the no−load dynamic power consumption: P D = CPD VCC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2f
pF
+ ICC VCC . For load considerations, see Chapter 2 of the
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TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25_C
Symbol
Parameter
Fig.
Min
Max
v 85_C
Min
v 125_C
Max
Min
Max
Units
tsu
Minimum Setup Time, Data to Clock
3
15
19
22
ns
th
Minimum Hold Time, Clock to Data
3
3
3
3
ns
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
2
6
8
9
ns
tw
Minimum Pulse Width, Clock
1
15
19
22
ns
tw
Minimum Pulse Width, Set or Reset
2
15
19
22
ns
tr, tf
Maximum Input Rise and Fall Times
1
500
500
500
ns
ORDERING INFORMATION
Device
Package
MC74HCT74AN
PDIP−14
MC74HCT74ANG
PDIP−14
(Pb−Free)
MC74HCT74AD
SOIC−14
MC74HCT74ADG
SOIC−14
(Pb−Free)
MC74HCT74ADR2
SOIC−14
MC74HCT74ADR2G
SOIC−14
(Pb−Free)
Shipping †
25 Units / Rail
55 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MC74HCT74A
SWITCHING WAVEFORMS
tr
CLOCK
tw
tf
SET OR
RESET
3V
2.7 V
1.3 V
0.3 V
Q OR Q
1.3 V
1/fmax
Q OR Q
tPLH
tPHL
tPLH
1.3 V
Q OR Q
90%
1.3 V
10%
tTLH
trec
1.3 V
CLOCK
tTHL
3V
GND
Figure 1.
Figure 2.
VALID
TEST POINT
3V
DATA
GND
tPHL
GND
tw
3V
1.3 V
1.3 V
OUTPUT
GND
tsu
DEVICE
UNDER
TEST
th
3V
1.3 V
C L*
GND
CLOCK
*Includes all probe and jig capacitance
Figure 3.
SET
Figure 5.
4, 10
2, 12
5, 9
DATA
Q
CLOCK
3, 11
6, 8
Q
1, 13
RESET
Figure 4. Expanded Logic Diagram
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4
MC74HCT74A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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5
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC74HCT74A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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