CD40104BMS, CD40194BMS CMOS 4-Bit Bidirectional Universal Shift Register December 1992 Features Pinouts CD40104BMS TOP VIEW • High Voltage Type (20V Rating) • Medium Speed fCL = 12MHz (typ.) at VDD = 10V 16 VDD OUTPUT ENABLE 1 • Fully Static Operation SHIFT RIGHT IN 2 15 Q0 • Synchronous Parallel or Serial Operation D0 3 14 Q1 • Three State Outputs (CD40104BMS) D1 4 13 Q2 D2 5 12 Q3 D3 6 11 CLOCK • Asynchronous Master Reset (CD40194BMS) • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics SHIFT LEVEL IN 7 10 SELECT 1 VSS 8 9 SELECT 0 • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” CD40194BMS TOP VIEW Applications • Serial/Parallel Conversions SHIFT RIGHT IN 2 15 Q0 D0 3 14 Q1 D1 4 13 Q2 D2 5 12 Q3 D3 6 11 CLOCK • General Purpose Register for Bus Organized Systems • General Purpose Registers Description SHIFT LEVEL IN 7 10 SELECT 1 VSS 8 9 SELECT 0 The CD40104BMS is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high impedance third output state allowing the device to be used in bus organized systems. In the parallel load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with serial data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the register is accomplished by setting both mode controls low and clocking the register. When the output enable input is low, all outputs assume the high impedance state. Functional Diagrams The CD40194BMS is a universal shift register featuring parallel inputs, parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of the register is inhibited when both mode control inputs are low. When low, the RESET input resets all stages and forces all outputs low. The CD40194BMS is similar to industry types 340194 and MC40194. The CD40104BMS and CD40194BMS series types are supplied in these 16 lead outline packages Braze Seal DIP *HNX, †H4W Frit Seal DIP *H1L, †HIF Ceramic Flatpack H6W * CD40104B Only †CD40194B Only 16 VDD RESET 1 • Arithmetic Unit Bus Registers CD40104BMS OUTPUT ENABLE D0 D1 D2 D3 SHIFT LEFT IN SHIFT RIGHT IN S0 MODE SELECT S1 15 Q0 14 Q1 13 Q2 12 Q3 11 CLOCK VDD = 16 VSS = 8 CD40194BMS RESET D0 D1 D2 D3 SHIFT LEFT IN SHIFT RIGHT IN S0 MODE SELECT S1 CLOCK CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1307 1 3 4 5 6 7 2 9 10 1 3 4 5 6 7 2 9 10 15 Q0 14 Q1 13 Q2 12 Q3 11 VDD = 16 VSS = 8 File Number 3352 Specifications CD40104BMS, CD40194BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current SYMBOL IDD IIL TEMPERATURE MIN MAX 1 +25oC - 10 µA 2 +125oC - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VDD = 20V, VIN = VDD or GND VDD = 20V VDD = 18V Input Leakage Current IIH LIMITS GROUP A SUBGROUPS CONDITIONS (NOTE 1) VIN = VDD or GND VDD = 20V VDD = 18V Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 UNITS - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA -2.8 -0.7 V 0.7 2.8 V N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B Functional F Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V IOZH VIN = VDD or GND VOUT = VDD V -55oC +25oC, Tri-State Output Leakage VOH > VOL < VDD/2 VDD/2 +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V 1, 2, 3 +25oC, +125oC, -55oC - 4 V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 1 +25oC -0.4 - µA 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1308 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD40104BMS, CD40194BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Q SYMBOL TPHL TPLH GROUP A SUBGROUPS TEMPERATURE CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay CD40194BMS Reset to Q TPHL Propagation Delay CD40104BMS 3-State TPZH TPZL TPLZ VDD = 5V, VIN = VDD or GND (Note 2, 3) Propagation Delay CD40104BMS 3-State TPHZ VDD = 5V, VIN = VDD or GND (Note 2, 3) Transition Time Maximum Clock Input Frequency VDD = 5V, VIN = VDD or GND (Note 1, 2) TTHL TTLH VDD = 5V, VIN = VDD or GND (Note 1, 2) FCL VDD = 5V, VIN = VDD or GND (Note 1, 2) 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC o o +125 C, -55 C o LIMITS MIN MAX UNITS - 440 ns - 594 ns - 460 ns - 621 ns - 160 ns - 216 ns - 90 ns - 122 ns 9 +25 C - 200 ns 10, 11 +125oC, -55oC - 270 ns 3 - MHz 2.22 - MHz MIN MAX UNITS - 5 µA - 150 µA - 10 µA - 300 µA - 10 µA 9 10, 11 o +25 C o o +125 C, -55 C NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. VDD = 5V, CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE o o -55 C, +25 C o +125 C VDD = 10V, VIN = VDD or GND 1, 2 o o -55 C, +25 C o +125 C VDD = 15V, VIN = VDD or GND 1, 2 o o -55 C, +25 C +125 C - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA o Output Current (Sink) Output Current (Sink) Output Current (Source) IOL10 IOL15 IOH5A VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 7-1309 Specifications CD40104BMS, CD40194BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH5B CONDITIONS NOTES VDD = 5V, VOUT = 2.5V 1, 2 TEMPERATURE MIN MAX UNITS - -1.15 mA -55 C - -2.0 mA +125oC - -0.9 mA - -1.6 mA - -2.4 mA - -4.2 mA o +125 C o Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 o -55 C Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 o +125 C o -55 C o o Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25 C, +125 C, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V Propagation Delay Clock to Q TPHL TPLH VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25 C - 140 ns Propagation Delay CD40194B Reset to Q TPLH TPHL VDD = 10V 1, 2, 3 +25oC - 180 ns o - 130 ns o - 70 ns o VDD = 15V 1, 2, 3 +25 C Propagation Delay CD40104BMS 3-State TPZH TPZL TPLZ VDD = 10V VDD = 15V 1, 2, 3, 4 +25 C - 50 ns Propagation Delay CD40104BMS 3-State TPHZ VDD = 10V 1, 2, 4 +25oC Transition Time Minimum Data Setup Time, D0, D3, SRIN, SLIN to Clock 1, 2, 3, 4 o VDD = 15V TTHL TTLH TS 1, 2, 4 VDD = 10V 1, 2, 3 VDD = 15V 1, 2, 3 TH Maximum Clock Rise and Fall Time Minimum Data Hold Time Select 1, Select 0 to Clock TS ns - 100 ns o - 80 ns o +25 C +25 C - 100 ns +25oC - 70 ns o - 50 ns o - 0 ns o - 0 ns o - 0 ns o 1, 2, 3 VDD = 5V 1, 2, 3 1, 2, 3 1, 2, 3 VDD = 5V +25 C +25 C +25 C +25 C 1, 2, 3 +25 C - 180 ns 1, 2, 3 +25oC - 80 ns VDD = 15V 1, 2, 3 +25oC - 50 ns VDD = 5V 1, 2, 3, 5 +25oC 3 - µs VDD = 10V 1, 2, 3, 5 +25oC 6 - µs 1, 2, 3, 5 +25oC 8 - µs 1, 2, 3 +25oC - 400 ns 1, 2, 3 +25oC - 220 ns 1, 2, 3 +25oC - 130 ns 1, 2, 3 +25oC - 0 ns VDD = 10V 1, 2, 3 +25oC - 0 ns VDD = 15V 1, 2, 3 +25oC - 0 ns VDD = 5V VDD = 10V VDD = 15V TH 40 +25 C VDD = 15V Minimum Data Setup Time Select 1, Select 0 to Clock - o +25 C 1, 2, 3 VDD = 10V TRCL TFCL ns 1, 2, 3 VDD = 10V TW 50 VDD = 10V VDD = 15V Minimum Clock Pulse Width - o VDD = 5V VDD = 15V Minimum Data Hold Time D0, D3, SRIN, SLIN to Clock +25 C VDD = 5V 7-1310 Specifications CD40104BMS, CD40194BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Reset Pulse Width CD40194BMS Input Capacitance SYMBOL TW CONDITIONS NOTES VDD = 5V CIN TEMPERATURE 1, 2, 3 MIN MAX UNITS o - 300 ns o +25 C VDD = 10V 1, 2, 3 +25 C - 200 ns VDD = 15V 1, 2, 3 +25oC - 140 ns - 7.5 pF Any Input o 1, 2 +25 C NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F CONDITIONS NOTES VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA TEMPERATURE 1, 4 MIN MAX UNITS o - 25 µA o -2.8 -0.2 V o +25 C 1, 4 +25 C VDD = 10V, ISS = -10µA 1, 4 +25 C - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND 1, 4 +25 C - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns o VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 7-1311 Specifications CD40104BMS, CD40194BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz 12-15 11 2 CD40104BMS, CD40194BMS Static Burn-In 1 Note 1 12-15 1-11 16 Static Burn-In 2 Note 1 12-15 8 1-7, 9-11, 16 Dynamic BurnIn Note 1 - 7, 8, 10 1, 3-6, 9, 16 12-15 8 1-7, 9-11, 16 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 1312 CD40104BMS, CD40194BMS Logic Diagrams B SHIFT RIGHT * INPUT 2 p n OE B D D0 * 3 VDD p n D G p n VDD CL CL p n p n Q0 Q0 15 CL CL CL CL G p n VSS p n p n E CL Q0 E CL B p n VDD B D D1 * 4 p n OE D G p n VDD OUTPUT * ENABLE 1 CL CL Q1 Q1 14 VSS Q1 G OE E CL * p n CLOCK * CL 11 E ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK B p n B OE D D2 * p n 5 D S0 * 9 CL CL D 13 Q2 G D Q2 Q2 p n VDD G G E p n G S1 * 10 B E B B p n E E B OE D D3 * p n 6 D G CL CL Q3 Q3 12 Q3 p n VDD CONTROL TRUTH TABLE G MODE SELECT E SHIFT LEFT * INPUT 7 p n CLOCK* E X S0 S1 OUTPUT ENABLE 0 0 1 Reset 1 0 1 Shift Right (Q0 toward Q3) 0 1 1 Shift Left (Q3 toward Q0) 1 1 1 Parallel Load X X 0 Operations occur as shown above, but outputs assume high impedance X = Don’t Care 1 = High level 0 = Low level FIGURE 1. CD40104BMS 7-1313 ACTION * Level change CD40104BMS, CD40194BMS Logic Diagrams SHIFT RIGHT * INPUT 2 (Continued) B p n B VDD D D0 * 3 R p n CL CL G p n Q0 p n p n D CL CL CL Q0 15 CL VSS G p n p n E p n CL Q0 E CL R B p n VDD B D D1 * 4 p n D G p n RESET * 1 CL CL Q1 Q1 14 VSS Q1 G R E CL * p n CLOCK * 11 CL E ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK B p n B D D2 * 5 p n D S0 * 9 CL CL 13 Q2 G D Q2 Q2 p n D G G E p n G S1 * 10 B B E B p n E E B D D3 * 6 p n D G CL CL Q3 Q3 12 Q3 p n G CONTROL TRUTH TABLE E SHIFT LEFT * INPUT 7 MODE SELECT p n E CLOCK* S0 S1 RESET X 0 0 1 No Change 1 0 1 Shift Right (Q0 toward Q3) 0 1 1 Shift Left (Q3 toward Q0) 1 1 1 Parallel Load X X 0 Reset X X = Don’t Care 1 = High level 0 = Low level FIGURE 2. CD40194BMS 7-1314 ACTION * Level change CD40104BMS, CD40194BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 -5 -15 -10V -20 -25 -15V -30 0 AMBIENT TEMPERATURE (TA) = +25oC 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V FIGURE 5. TYPICAL P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -15 FIGURE 6. MINIMUM P-CHANNEL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 20 40 60 80 LOAD CAPACITANCE (CL) (pF) 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 -10 0 10 FIGURE 4. MINIMUM N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC PROPAGATION DELAY TIME (tPLH, tPHL) (ns) 15.0 0 FIGURE 3. TYPICAL N-CHANNEL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 200 150 100 10V FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE, (CLOCK TO Q) 15V 50 0 0 100 SUPPLY VOLTAGE (VDD) = 5V 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 7-1315 CD40104BMS, CD40194BMS Typical Performance Characteristics TYP. DYNAMIC POWER DISSIPATION (PD) (µW) 105 8 (Continued) AMBIENT TEMPERATURE (TA) = +25oC 6 4 2 SUPPLY VOLTAGE (VDD) = 5V 104 8 6 4 2 15V 10V 3 10 8 6 4 2 102 8 6 4 CL = 50pF CL = 15pF 2 10 2 4 68 0.1 2 4 68 2 4 68 2 10 102 FREQUENCY (fφ) (kHz) 1 4 68 103 2 4 68 104 FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY Chip Dimensions and Pad Layouts CD40104BMS CD40194BMS Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-1316