ONSEMI MC74HC390ADR2

MC74HC390A
Dual 4−Stage Binary Ripple
Counter with ÷ 2 and ÷ 5
Sections
High−Performance Silicon−Gate CMOS
http://onsemi.com
The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit counters, each
composed of a divide−by−two and a divide−by−five section. The
divide−by−two and divide−by−five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
Flip−flops internal to the counters are triggered by high−to−low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4−bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
16
1
MC74HC390AN
AWLYYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
16
1
HC390AG
AWLYWW
1
16
Features
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No 7A
Chip Complexity: 244 FETs or 61 Equivalent Gates
Pb−Free Packages are Available*
16
1
TSSOP−16
DT SUFFIX
CASE 948F
HC
390A
ALYWG
G
1
16
16
1
SOEIAJ−16
F SUFFIX
CASE 966
74HC390A
ALYWG
1
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 3
1
Publication Order Number:
MC74HC390A/D
MC74HC390A
CLOCK Aa
1
16
VCC
RESET a
2
15
CLOCK Ab
QAa
3
14
RESET b
CLOCK Ba
4
13
QAb
QBa
5
12
CLOCK Bb
QCa
6
11
QBb
QDa
7
10
QCb
GND
8
9
QDb
CLOCK A
1, 15
÷2
COUNTER
3, 13
QA
5, 11
CLOCK B
RESET
4, 12
÷5
COUNTER
QB
6, 10
QC
7, 9
QD
PIN 16 = VCC
PIN 8 = GND
2, 14
Figure 1. Pin Assignment
Figure 2. Logic Diagram
FUNCTION TABLE
Clock
A
B
Reset
Action
X
X
H
X
L
Reset
÷ 2 and ÷ 5
Increment
÷2
Increment
÷5
X
L
ORDERING INFORMATION
Package
Shipping †
MC74HC390AN
PDIP−16
500 Units / Rail
MC74HC390ANG
PDIP−16
(Pb−Free)
500 Units / Rail
MC74HC390AD
SOIC−16
48 Units / Rail
MC74HC390ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC390ADR2
SOIC−16
2500 Units / Reel
MC74HC390ADR2G
SOIC−16
(Pb−Free)
2500 Units / Reel
MC74HC390ADTR2
TSSOP−16*
2500 Units / Reel
MC74HC390ADTR2G
TSSOP−16*
2500 Units / Reel
MC74HC390AF
SOEIAJ−16
50 Units / Rail
MC74HC390AFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74HC390AFEL
SOEIAJ−16
2000 Units / Reel
MC74HC390AFELG
SOEIAJ−16
(Pb−Free)
2000 Units / Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
2
MC74HC390A
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
mA
Iout
DC Output Current, per Pin
± 25
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
260
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
0
VCC
V
– 55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Vin = VIH or VIL
VOL
Maximum Low−Level Output
Voltage
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
Vin = VIH or VIL
|Iout| v 20 mA
Vin = VIH or VIL
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
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3
V
MC74HC390A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4
40
160
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock A to QA
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock A to QC
(QA connected to Clock B)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
200
160
58
49
250
185
65
62
300
210
70
68
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QB
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QC
(Figures 1 and 3)
2.0
3.0
4.5
6.0
90
56
37
31
105
70
46
39
180
100
56
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock B to QD
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
ns
tPHL
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
44
39
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
−
10
10
10
pF
Cin
Maximum Input Capacitance
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
35
Power Dissipation Capacitance (Per Counter)*
* Used to determine the no−load dynamic power consumption: PD = CPD VCC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2f + I
http://onsemi.com
4
CC
pF
VCC . For load considerations, see Chapter 2 of the
MC74HC390A
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
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ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
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ÎÎÎÎ
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ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
trec
Minimum Recovery Time, Reset Inactive to Clock A or Clock B
(Figure 2)
2.0
3.0
4.5
6.0
25
15
10
9
30
20
13
11
40
30
15
13
ns
tw
Minimum Pulse Width, Clock A, Clock B
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
20
18
95
32
24
22
110
36
30
28
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
tf, tf
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
OUTPUTS
QA (Pins 3, 13)
Clock A is the clock input to the ÷ 2 counter; Clock B is
the clock input to the ÷ 5 counter. The internal flip−flops are
toggled by high−to−low transitions of the clock input.
Output of the ÷ 2 counter.
QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)
Outputs of the ÷ 5 counter. QD is the most significant bit.
QA is the least significant bit when the counter is connected
for BCD output as in Figure 4. QB is the least significant bit
when the counter is operating in the bi−quinary mode as in
Figure 5.
CONTROL INPUTS
Reset (Pins 2, 14)
Asynchronous reset. A high at the Reset input prevents
counting, resets the internal flip−flops, and forces QA
through QD low.
SWITCHING WAVEFORMS
CLOCK
tf
90%
50%
10% 10%
tr
tw
VCC
GND
tw
GND
tPHL
1/fmax
tPLH
Q
VCC
50%
RESET
Q
tPHL
90%
50%
10%
50%
trec
tTLH
50%
CLOCK
tTHL
Figure 3.
GND
Figure 4.
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5
VCC
MC74HC390A
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C L*
*Includes all probe and jig capacitance
Figure 5.
EXPANDED LOGIC DIAGRAM
1, 15
CLOCK A
D
4, 12
CLOCK B
D
D
Q
C
R
3, 13
Q
Q
C
R
5, 11
Q
Q
C
R
R
QB
Q
6, 10 Q
C
Q
7, 9 Q
D
C
D
QA
2, 14
RESET
TIMING DIAGRAM
(QA Connected to Clock B)
0
1
2
3
4
5
6
7
8
9
CLOCK A
RESET
QA
QB
QC
QD
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6
0
1
2
3
4
5
6
MC74HC390A
APPLICATIONS INFORMATION
Each half of the MC54/74HC390A has independent ÷ 2
and ÷ 5 sections (except for the Reset function). The ÷ 2 and
÷ 5 counters can be connected to give BCD or bi−quinary
(2−5) count sequences. If Output QA is connected to the
Clock B input (Figure 4), a decade divider with BCD output
is obtained. The function table for the BCD count sequence
is given in Table 1.
To obtain a bi−quinary count sequence, the input signals
connected to the Clock B input, and output QD is connected
to the Clock A input (Figure 5). QA provides a 50% duty
cycle output. The bi−quinary count sequence function table
is given in Table 2.
Table 1. BCD Count Sequence*
Table 2. Bi−Quinary Count Sequence**
Output
Count
QD
QC
0
L
L
1
L
L
2
L
L
3
L
L
4
L
H
5
L
H
6
L
H
7
L
H
8
H
L
9
H
L
*QA connected to Clock B input.
Output
QB
QA
Count
QA
QD
QC
QB
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
8
9
10
11
12
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
** QD connected to Clock A input.
CONNECTION DIAGRAMS
CLOCK A
CLOCK B
RESET
1, 15
4, 12
÷2
COUNTER
3, 13
5, 11
÷5
COUNTER
6, 10
7, 9
QA
CLOCK A
QB
CLOCK B
QC
1, 15
4, 12
QD
2, 14
RESET
Figure 6. BCD Count
÷2
COUNTER
÷5
COUNTER
3, 13
QA
5, 11
QB
6, 10
7, 9
2, 14
Figure 7. Bi-Quinary Count
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7
QC
QD
MC74HC390A
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
−T−
SEATING
PLANE
K
H
D
M
J
G
16 PL
0.25 (0.010)
T A
M
M
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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8
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74HC390A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
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9
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HC390A
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
CASE 966−01
ISSUE O
16
LE
9
Q1
M_
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.031
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74HC390A/D