MC74LCX240 Low−Voltage CMOS Octal Buffer With 5 V−Tolerant Inputs and Outputs (3−State, Inverting) http://onsemi.com The MC74LCX240 is a high performance, inverting octal buffer operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX240 inputs to be safely driven from 5 V devices. The MC74LCX240 is suitable for memory address driving and all TTL level bus oriented transceiver applications. Current drive capability is 24 mA at the outputs. The Output Enable (OE) input, when HIGH, disables the outputs by placing them in a HIGH Z condition. MARKING DIAGRAMS 20 20 1 SOIC−20 DW SUFFIX CASE 751D LCX240 AWLYYWWG 1 Features • • • • • • • • • • • Designed for 2.3 to 3.6 V VCC Operation 5 V Tolerant − Interface Capability With 5 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 mA) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V Machine Model >200 V Pb−Free Packages are Available* 20 20 1 LCX 240 ALYWG G TSSOP−20 DT SUFFIX CASE 948E 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 7 1 Publication Order Number: MC74LCX240/D MC74LCX240 1OE VCC 2OE 1O0 2D0 1O1 2D1 1O2 2D2 1O3 2D3 20 19 18 17 16 15 14 13 12 11 1D0 1D1 1D2 1 2 3 4 5 6 7 8 9 10 1OE 1D0 2O0 1D1 2O1 1D2 2O2 1D3 2O3 GND 1D3 1 2 18 4 16 6 14 8 12 1O0 1O1 1O2 1O3 Figure 1. Pinout: 20−Lead (Top View) 2OE 2D0 PIN NAMES Pins Function nOE 1Dn, 2Dn 1On, 2On Output Enable Inputs Data Inputs 3−State Outputs 2D1 2D2 2D3 19 17 3 15 5 13 7 11 9 2O0 2O1 2O2 2O3 Figure 2. LOGIC DIAGRAM TRUTH TABLE INPUTS H L Z X OUTPUTS 1OE 2OE 1Dn 2Dn 1On, 2On L L H L H L H X Z = = = = High Voltage Level Low Voltage Level High Impedance State High or Low Voltage Level and Transitions Are Acceptable; for ICC reasons, DO NOT FLOAT Inputs http://onsemi.com 2 MC74LCX240 MAXIMUM RATINGS Symbol Parameter VCC DC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current Value Condition Unit −0.5 to +7.0 V −0.5 ≤ VI ≤ +7.0 V −0.5 ≤ VO ≤ +7.0 Output in 3−State −0.5 ≤ VO ≤ VCC + 0.5 Note 1 V −50 VI < GND mA −50 VO < GND mA +50 VO > VCC mA V IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Output in HIGH or LOW State. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit 2.0 1.5 3.3 3.3 3.6 3.6 V 0 5.5 V 0 0 VCC 5.5 V HIGH Level Output Current, VCC = 3.0 V − 3.6 V −24 mA LOW Level Output Current, VCC = 3.0 V − 3.6 V 24 mA IOH HIGH Level Output Current, VCC = 2.7 V − 3.0 V −12 mA IOL LOW Level Output Current, VCC = 2.7 V − 3.0 V 12 mA TA Operating Free−Air Temperature −40 +85 °C Dt/DV Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V VCC Supply Voltage VI Input Voltage VO Output Voltage IOH IOL Operating Data Retention Only (HIGH or LOW State) (3−State) ORDERING INFORMATION Package Shipping† MC74LCX240DT TSSOP−20* 75 Units / Rail MC74LCX240DTR2 TSSOP−20* 2000 Tape & Reel MC74LCX240DTR2G TSSOP−20* 2000 Tape & Reel MC74LCX240DWR2 SOIC−20 1000 Tape & Reel MC74LCX240DWR2G SOIC−20 (Pb−Free) 1000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol Characteristic Condition Min 2.0 VIH HIGH Level Input Voltage (Note 2) 2.7 V ≤ VCC ≤ 3.6 V VIL LOW Level Input Voltage (Note 2) 2.7 V ≤ VCC ≤ 3.6 V VOH HIGH Level Output Voltage VCC − 0.2 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2. These values of VI are used to test DC electrical characteristics only. 2.2 3 Unit V 0.8 2.7 V ≤ VCC ≤ 3.6 V; IOH = −100 mA http://onsemi.com Max V V MC74LCX240 DC ELECTRICAL CHARACTERISTICS (Continued) TA = −40°C to +85°C Symbol VOL Characteristic LOW Level Output Voltage Max Unit 2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 mA Condition Min 0.2 V VCC = 2.7 V; IOL= 12 mA 0.4 VCC = 3.0 V; IOL = 16 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 II Input Leakage Current 2.7 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V ±5.0 mA IOZ 3−State Output Current 2.7 ≤ VCC ≤ 3.6 V; 0V ≤ VO ≤ 5.5 V; VI = VIH or V IL ±5.0 mA IOFF Power−Off Leakage Current ICC DICC Quiescent Supply Current Increase in ICC per Input VCC = 0 V; VI or VO = 5.5 V 10 mA 2.7 ≤ VCC ≤ 3.6 V; VI = GND or VCC 10 mA 2.7 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V ±10 mA 2.7 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 mA AC CHARACTERISTICS (tR = tF = 2.5 ns; CL = 50 pF; RL = 500 W) Limits TA = −40°C to +85°C VCC = 3.0 V to 3.6 V Symbol Parameter VCC = 2.7 V Waveform Min Max Max Unit tPLH tPHL Propagation Delay Input to Output 1 1.5 1.5 6.5 6.5 7.5 7.5 ns tPZH tPZL Output Enable Time to High and Low Level 2 1.5 1.5 8.0 8.0 9.0 9.0 ns tPHZ tPLZ Output Disable Time From High and Low Level 2 1.5 1.5 7.0 7.0 8.0 8.0 ns tOSHL tOSLH Output−to−Output Skew (Note 3) 1.0 1.0 ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition VOLP Dynamic LOW Peak Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V Min Typ 0.8 Max Unit V VOLV Dynamic LOW Valley Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V 0.8 V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit CIN Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF http://onsemi.com 4 MC74LCX240 2.7 V 1Dn, 2Dn 1.5 V 1.5 V 0V tPHL tPLH 1.5 V 1On, 2On VOH 1.5 V VOL WAVEFORM 1 − PROPAGATION DELAYS tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns 2.7 V 1.5 V 1OE, 2OE 0V tPZH tPHZ VCC VOH − 0.3 V 1.5 V 1On, 2On ≈0V tPZL tPLZ ≈ 3.0 V 1.5 V 1On, 2On VOL + 0.3 V GND WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 3. Waveforms VCC PULSE GENERATOR R1 DUT RT CL TEST RL SWITCH tPLH, tPHL Open tPZL, tPLZ 6V Open Collector/Drain tPLH and tPHL 6V tPZH, tPHZ GND CL = 50pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500W or equivalent RT = ZOUT of pulse generator (typically 50W) Figure 4. Test Circuit http://onsemi.com 5 6V OPEN GND MC74LCX240 PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 18X e A1 SEATING PLANE C T http://onsemi.com 6 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74LCX240 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE B 20X 0.15 (0.006) T U 2X 0.10 (0.004) S L/2 20 M T U S V S ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 11 J J1 B −U− L PIN 1 IDENT SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. K REF S M A −V− N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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