AMD AMMC004AWP

PRELIMINARY
AmMC0XXA
2, 4, or 8 Megabyte 5.0 Volt-only Flash Miniature Card
DISTINCTIVE CHARACTERISTICS
■ 2, 4, or 8 Mbytes of addressable Flash memory
■ 5.0 Volt-only, single power supply operation
— Write and read voltage: 5.0 V ± 10%
— No additional supply current required for VPP
■ Fast access time
— 100 or 150 ns access time
■ CMOS low power consumption
— Typical active read current:
70 mA (word mode)
— Typical active erase/write current:
100 mA (word mode)
— Typical standby current:
10 µA (8 Mbyte card)
■ High write endurance
— Guaranteed minimum 100,000 write/erase
cycles per card
— More than 1,000,000 cycles per card typical
■ Uniform sector architecture
— 64K byte individually useable sectors
■ Available in industrial temperature grade
(–40°C to +85°C)
■ Miniature Card standard form factor
— True interchangeability
— 60-pad connector
— Supports multiple technologies
— Sonic welded stainless steel case
— PCMCIA Type II adapter available
— Selectable byte- or word-wide configuration
— Small form factor (38 mm x 33 mm x 3.5 mm)
■ 60 connection bus
— 16-bit data bus
— 25-bit address bus
— Easy system integration
— Low cost implementation
— Low cost cards
■ Consumer-friendly mechanicals
— User can easily insert and remove card, upgrade
memory, and add applications
■ Voltage level keying
— Erase Suspend/Resume increases system level
performance
— Does not allow a 5 V card to plug into a 3 V
system and vice versa
— BUSY# and RESET# signals
— Single power supply design
■ Zero data retention power
— No power required to retain data
GENERAL DESCRIPTION
The Miniature Card is an expansion card that provides
a high-performance, small form factor solution for data
and file storage to the portable, handheld market,
which includes audio, digital film, wireless, and PDA
(Portable Digital Assistant) applications. The Miniature
Card provides a low cost, low power, high performance
interface for memory cards.
Miniature cards can be easily “snapped” into the back
of an electronic system and can be readily removed
and replaced by end users. AMD’s 5 V Flash Miniature
Cards are manufactured using AMD’s industry leading
5.0 volt-only, single-power-supply Am29F080B and
— System does not need a separate program
voltage supply; only one is necessary to read
and write
Am29F017B Flash Memory devices, ensuring high reliability and excellent performance. The Miniature Card
is less than 30% of the size of a PCMCIA memory card.
Applications include digital voice recorders, pocket
PCs and intelligent organizers, smart cellular telephones, voice and data messaging pagers, digital still
cameras and portable instrumentation equipment.
The Miniature Card specification will be defined by
PCMCIA as of October 1997. The participating association members include major Flash memory vendors
and leading consumer electronics OEMs. The goal of
the Miniature Card specification is to promote an open,
interoperable small-form-factor memory card standard.
For more information on the Miniature Card specifica-
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 20975 Rev: D Amendment/+1
Issue Date: May 1998
PRELIMINARY
tion, visit the PCMCIA web site at http://www.pccard.com.
AMD Flash Miniature Cards can be read in either a
byte-wide or word-wide mode, which allows for flexible
integration into various system platforms. Compatibility
is assured at the hardware interface and software interchange specification.
Miniature Card is also designed with low-cost and
rugged handling in mind. The card contains virtually
no control logic, which keeps cost and power consumption to a minimum. The Miniature Card is packaged in a sonic welded, stainless steel case that
guarantees durability, provides good ESD protection
and ease of handling.
The Miniature Card has extensive third-party support,
including socket and connector solutions, software
support from the major FTL software vendors, and
PCMCIA adapter solutions and programmer support.
Table 1.
AMD’s Miniature Flash cards can be used for both code
and data storage. Since fast random access is possible,
code can be directly executed from the card, reducing
the amount of system RAM required. In addition. AMD’s
Flash technology offers unsurpassed endurance, data
retention and reliability, eliminating the need for
complex error correction and defect management hardware and software. Each Flash sector provides a
minimum of 100,000 cycles, which translates into a
typical card life of one million or more cycles.
For more information, please contact your local AMD
s a l e s o f f i c e o r v i s i t o u r We b s i t e a t
http://www.amd.com/html/products/nvd/nvd.html.
DEFINITIONS
Table 1 lists the terms and definitions that may be used
in conjunction with Miniature Card specifications.
Miniature Card Definitions
Term
Meaning
AIS
Acronym for Attribute Information Structure. AIS is a Miniature Card specification for storing
Miniature Card attribute information.
ESD
Acronym for Electrostatic Discharge. ESD is part of the Miniature Card physical test.
FAT
Acronym for File Allocation Table. Using an FAT is a common method for managing files in a
DOS-based system.
Flash
A type of non-volatile memory that is both readable and writeable, but requires the media to
be erased before it is rewritten.
Host
Any system that incorporates a Miniature Card socket.
User Perception: Insertion of the Miniature Card when the host is off.
Insertion, Cold
Host State: The host would be either off or in sleep mode, no bus activity is occurring, the
host is non-operational by the user. The user inserts the Miniature Card and then presses a
button to turn the host on before the system is operational.
User Perception: Insertion of a Miniature Card when the host is running.
Insertion, Hot
Host State: The host would be in running mode, bus activity is occurring, the host is
operational by the user. The user inserts the card, the host recognizes it, and the host
continues to be operational. Note: Hot insertion may require buffering on the host system for
proper operation.
User Perception: Insertion of a Miniature Card when the host is running.
Insertion, Pseudo Hot
Host State: The host would be in running mode, bus activity is occurring, the host is
operational by the user. The user inserts the card, the host immediately powers off before the
Miniature Card makes contact with the host’s internal bus. The user would then need to press
a button to turn the host on for it to become operational.
Interface Signals
Miniature Card signals that make connection through the 60-pad connector area.
JEDEC
Acronym for Joint Electronic Device Engineering Council.
Miniature Card Backside
The side of the Miniature Card that contains the latching mechanism. The backside is
opposite the frontside.
Miniature Card Bottomside
The side of the Miniature Card that contains the interface signals. The bottomside is opposite
the topside.
2
AmMC0XXA
PRELIMINARY
Table 1.
Miniature Card Definitions (Continued)
Term
Meaning
Miniature Card Frontside
The side of the Miniature Card that contains power, insertion, ground, voltage keys, and
alignment notch. The frontside is opposite the backside.
Miniature Card Topside
The side of the Miniature Card that contains the Miniature Card label. The topside is opposite
the bottomside.
PC Card
A memory or I/O card compatible with the PC Card Standard.
PC Card Adapter
The hardware that connects the Miniature Card 60 contact bus to the PC Card 68 pin bus.
This hardware can be mechanically implemented by following the PC Card Type II
specification.
Power/Insertion Signals
The three signals on the frontside of the Miniature Card that provide ground, power and early
detection of insertion.
Pull-Ups
Resistors used to ensure that signals do not float when no device is driving them.
User Perception: Removal of a Miniature Card when the host is off.
Removal, Cold
Host State: The host would either be off or in sleep mode, no bus activity is occurring, the
host is non-operational by the user. User would turn off the host, then remove the Miniature
Card and then press a button to turn the host on for it to become operational again.
User Perception: Removal of the Miniature Card when the host is running.
Removal, Hot
Host State: The host would be in running mode, bus activity is occurring, the host is
operational by the user. User removes the card, the host recognizes the event, and the host
continues to be operational.
User Perception: Removal of the Miniature Card when the host is running.
Removal, Pseudo Hot
Host State: The host would be in running mode, bus activity is occurring, the host is
operational by the user. User removes the card, the host recognizes the event, the host
immediately powers off before the Miniature Card removes contact with the host’s internal
bus. The user would then need to press a button to turn the host on for it to be operational
again.
Sector
Usually 64 Kbytes, but depends on device used in the card. In word mode, a sector is 64
KWords.
Tuple
An element of the PC Card Standard CIS that provides card attribute information, and a link
to the next tuple in a string of tuples.
User Insertable
All Miniature Cards should be inserted into the host by the user without the need for any
special tools.
User Removable
This type of Miniature Card can be removed by the user without the need for any special tools.
It contains programs and data that users may want to switch often. The use of this type of
card is similar to a floppy disk.
User Non-Removable
This type of Miniature Card must be removed by the user with a special tool. It contains
memory upgrades or boot program that users switches only when they require an upgrade.
The use of this type of card is similar to a SIMM memory expansion or boot hard disk.
XIP
Acronym for eXecute-In-Place, which refers to code that executes directly from a Miniature
Card.
AmMC0XXA
3
PRELIMINARY
Write Protect Switch (optional)
Pad 60
Pad 31
Pad 30
Pad 1
VCC
3V/5V
Key
Alignment
Notch
CINS#
GND
20975D-1
Figure 1.
Miniature Card Connector (Card Bottom View)
Note: Refer to the Physical Dimensions section for more information. Also refer to the MCIF specification for detailed mechanical
information, available on the Web at http://www.mcif.org.
Table 2.
4
AMD Flash Miniature Cards and Flash Devices
Family Part Number
Density
No. of Flash Devices
AMD Flash Memory
AmMC002AWP
2 Mbyte
2
Am29F080B
AmMC004AWP
4 Mbyte
2
Am29F017B
AmMC008AWP
8 Mbyte
4
Am29F017B
AmMC0XXA
PRELIMINARY
BLOCK DIAGRAM
VCC
VCC
10K
10K
VCC
BUSY#
RY/BY#
10K
RESET#
RESET# to all Flash devices
WE#
WE# to all Flash devices
Write Protect
Switch
OE# to all Flash devices
OE#
D8–D15
D0–D7
A0–A24
VCC
100K
VCC
100K
A21
CEL#
CEL0#
CEH#
CEH0#
CEL1#
CEH1#
Decoder*
VSS VCC
VSS VCC
A0-A20*** D0-D7
A0-A20*** D8-D15
CE#
WE# S0**
OE#
RESET# RY/BY#
WE# S1**
OE#
RESET# RY/BY#
VSS VCC
VSS VCC
A0-A20*** D0-D7
A0-A20*** D8-D15
CE#
WE# S2**
OE#
RESET# RY/BY#
CE#
WE# S3**
OE#
RESET# RY/BY#
20975D-2
*
Decoder used on 8 Mbyte card only. Not used on 2 and 4 Mbyte cards.
** 2 Mbyte card: Two Am29F080B devices, S0 and S1
4 Mbyte card: Two Am29F017B devices, S0 and S1
8 Mbyte card: Four Am29F017B devices, S0...S3
*** A0–A19 on 2 Mbyte card; A0–A20 on 4 and 8 Mbyte cards.
Note: On the 2 Mbyte card, A20–A24 are not connected. On the 4 Mbyte cards, A21–A24 are not connected. On the 8 Mbyte
cards, A22-A24 are not connected. Connections not shown in this diagram are not connected internally.
AmMC0XXA
5
PRELIMINARY
MINIATURE CARD PAD ASSIGNMENTS
A0–A24
RESET#
Address A0 to A24 are the address bus lines that can
address up to 32 Mwords (64 Mbytes). The address
lines are word addressed. The Miniature Card specification does not require the Miniature Card to decode
the upper address lines. A 2 Mbyte Miniature Card that
does not decode the upper address lines would repeat
its address space every 2 Mbytes. Address 0h would
access the same physical location as 200000h,
400000h, 600000h, etc. On the 2 Mbyte cards, A20–
A24 are not connected. On the 4 Mbyte cards, A21–
A24 are not connected. On the 8 Mbyte cards, A22–
A24 are not connected.
RESET# controls card initialization. When RESET#
transitions from a low state to a high state, the Miniature Card resets to the Read state.
D0–D15
Data lines D0 through D15 constitute the data bus. The
data bus is composed of two bytes; the low byte is D0–
D7 and the high byte is D8–D15. These lines are
tristated when OE# is high.
OE#
OE# indicates to the card that the current bus cycle is
a read cycle. The output enable access time (tOE) is the
delay from the falling edge of OE# to valid data at the
output pins (assuming the addresses have been stable
for at least tACC – tOE time).
WE#
WE# indicates to the card that the current bus cycle is a
write cycle. The falling edge of WE# latches address information and the rising edge latches data/command information.
BUSY#
BUSY# is a signal generated by the card to indicate the
status of operations within the Miniature Card. When
BUSY# is high, the Miniature Card is ready to accept
the next command from the host. When BUSY# is low,
the Miniature Card is busy and unable to accept most
data operations from the host. In Flash Miniature Cards
the BUSY# signal is tied to the components’ RY/BY#
signal.
CD#
CD# is a grounded interface signal. After a Miniature
Card has been inserted, CD# will be forced low. The
card detect signal is located in the center of the second
row of interface signals, and should be one of the last
interface signals to connect to the host. Do not confuse
CD# with CINS#.
CINS#
CINS# is a grounded signal on the front of the Miniature
Card that is used for early detection of a card insertion.
CINS# makes contact on the host when the front of the
card is inserted into the socket, before the interface
signals connect.
BS8#
Voltage Sense 1 signal. This signal is left open or
not connected.
The BS8# (Bus size 8) signal indicates to the Miniature
Card that the host has an 8-bit bus. AMD Flash Miniature Cards ignore this signal. An 8-bit host must
connect its D0–D7 data lines to D8–D15 on the Miniature Card to retrieve the upper (odd) byte.
VS2#
GND
Voltage Sense 2 signal. This signal is left open or
not connected.
Ground
VS1#
CEL#
Vcc is used to supply power to the card.
CEL# enables the low byte of the data bus (D0–D7) on
the card.
NC
No connect
CEH#
CEH# enables the high byte of the data bus (D8–D15)
on the card.
6
VCC
RFU
Reserved for future use
AmMC0XXA
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM
MC
008
A
WP
-100
I
TEMPERATURE RANGE
Blank = Commercial (0°C to +70°C)
I
= Industrial (–40°C to +85°C)
SPEED OPTION
See Valid Combinations below
WRITE PROTECT SWITCH OPTION
WP = Switch installed
REVISION LEVEL
MEMORY CARD DENSITY
002 = 2 Megabyte Card
004 = 4 Megabyte Card
008 = 8 Megabyte Card
MINIATURE CARD
AMD
Valid Combinations
Valid Combinations
AmMC002AWP
AmMC004AWP
-100, -100I, -150
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AmMC008AWP
AmMC0XXA
7
PRELIMINARY
INTERFACE SIGNAL ASSIGNMENTS
Pad Number
Signal Name
Pad Number
Signal Name
Pad Number
Signal Name
1
A18
21
D12
41
A4
2
A16
22
D10
42
CEL#
3
A14
23
D9
43
A1
4
NC
24
D0
44
NC
5
CEH#
25
D2
45
NC
6
A11
26
D4
46
CD#
7
A9
27
RFU
47
A21
8
A8
28
D7
48
BUSY#
9
A6
29
NC
49
WE#
10
A5
30
NC
50
D14
11
A3
31
A19
51
RFU
12
A2
32
A17
52
D11
13
A0
33
A15
53
VS2#
14
NC
34
A13
54
D8
15
A24
35
A12
55
D1
16
A23
36
RESET#
56
D3
17
A22
37
A10
57
D5
18
OE#
38
VS1#
58
D6
19
D15
39
A7
59
RFU
20
D13
40
BS8#
60
A20
Note: NC = No Connect; RFU = Reserved for Future Use.
FLASH MINIATURE CARD OPERATIONS
Voltage Sensing
AMD Miniature Cards provide two voltage sense
signals for hosts that support multiple voltages. The
multivoltage host can sense the voltage level of the
Miniature Card and power up the card at that voltage.
See Table 3 for a description of the voltage sense
signals.
ensure the card can only be inserted into host systems
that can supply the proper voltage levels to the card.
Refer to Section 4.1.2 in the Miniature Card specification for more information on mechanical keying.
In addition to the voltage sense pins, there are also
mechanical voltage keys on the Miniature Card that
8
AmMC0XXA
Table 3.
Voltage Sense Signals
Miniature Card
Power-Up Voltage
VS1#
VS2#
5 Volt-only
Open
Open
PRELIMINARY
Data Accesses
The Miniature Card has a 16-bit data bus that can
accommodate word or byte accesses. By individually
asserting CEL# and CEH#, a host can access either
byte. However, byte swapping (moving the high byte
data to the low byte) is not supported.
Figure 2 shows the connections between the host and
Miniature Card. The host system address lines range
from A0-A25, whereas the Miniature Card address
lines range from A0–A24. On the host, A0 and the
byte/word line are sent to a decoder and output to
CEL# and CEH# on the Miniature Card. These two bits
enable a single device for byte accesses and two
devices for word accesses, as shown by the decoder
truth table in Figure 2. Again, the Miniature Card
address lines do not receive input from host address bit
A0. In this document, all address references are card
addresses, unless otherwise noted. Table 4 shows the
read/write modes for Miniature Cards.
Byte/Word
A0
Decoder
Decoder Truth Table
Input
Host Bus
Host
A25
A24
A23
A21
A22
A2
A1
A1
A0
Output
A0
B/W
CEL
CEH#
0
0
0
0
0
1
0
1
1
0
0
0
1
1
1
0
60-Pad Connector
Card
A24***
A23***
A22***
A21**
A20*
CEL#
CEH#
20975D-3
Card Bus
*
Not connected on 2 Mbyte card
** Not connected on 2 and 4 Mbyte card
*** Not connected
Figure 2.
Host/Card Address Connections
AmMC0XXA
9
PRELIMINARY
Table 4.
Miniature Card Read/Write Modes
CEH#
CEL#
WE#
OE#
D8–D15
D0–D7
Standby
H
H
X
X
High-Z
High-Z
Word Access
L
L
H
L
High Byte Data
Low Byte Data
Low Byte Access
H
L
H
L
High-Z
Low Byte Data
High Byte Access
L
H
H
L
High Byte Data
High-Z
Standby
H
H
X
X
High-Z
High-Z
Word Access
L
L
L
H
High Byte Data
Low Byte Data
Low Byte Access
H
L
L
H
High-Z
Low Byte Data
High Byte Access
L
H
L
H
High Byte Data
High-Z
Function
Read Mode
Write Mode
Notes:
1. Unlisted access combinations are invalid and may return unexpected results.
2. X indicates a Don’t Care value.
Erase Operations
The AMD Flash Miniature Card is organized as an array
of individual devices. On the 2 Mbyte Miniature Card,
each Am29F080B device contains sixteen 64 Kbyte sectors, for a total of 1 Mbyte of memory space per device.
On 4 and 8 Mbyte Miniature Cards, each Am29F017B
device contains thirty-two 64 Kbyte sectors, for a total of
2 Mbytes of memory space per device.
Flash technology allows any logical “1” data bit to be programmed to a logical “0”. The only way to reset bits to a
logical “1” is to erase that entire memory sector or
memory device. Once a memory sector or memory
device is erased, any address location may be programmed. Two or more devices may be erased concurrently when additional ICC current is supplied to the card.
However, erasing more than two devices concurrently is
not typical in battery-powered applications, but may take
place during procedures such as card testing.
Since erase commands operate on entire sectors or
devices, the host should track the affected memory
addresses; for example, by determining the sector size
and device size and calculating the corresponding
addresses.
Erase operations can be performed in several ways:
■ Erase a single sector or multiple sectors in a device
AMD Flash memor y device pair will require a
maximum of 120 mA supply current.
The common memory space data contents are altered
in a similar manner as writing to individual Flash memory
devices. An on-card address decoder activates the
appropriate Flash device in the memory array. Each
device internally latches address and data during write
cycles. Refer to Table 4.
Word-Wide Operations
The AMD Miniature Card provide the flexibility to operate
on data in a byte-wide or word-wide format. In word-wide
operations, the low bytes are controlled with CEL#. The
high bytes are controlled with CEH#. Refer to the block
diagram for more information.
Byte-Wide Operations
Byte-wide data is available for read and write operations (CEL# = 0, CEH# = 1). Even and odd bytes are
stored in separate memory devices (for example, S0
and S1) and are accessed by controlling CEL# and
CEH#. The even byte is the low order byte and the odd
byte is the high order byte of a 16-bit word.
Each memory sector or device pair must be addressed
separately for erase operations. Refer to the block
diagram for more information.
■ Erase a sector pair
Card Detection
■ Erase multiple device pairs *
Each CD# (output) pin should be detected by the host
system to determine if the memory card is adequately
seated in the socket. CD# and CINS# are internally tied
to ground. If both bits are not detected, the system
should indicate that the card must be re-inserted.
■ Erase the entire card *
* This operation is only feasible in solutions capable of
supplying more than the specified miniature card
supply current requirement (150 mA) per system. Each
10
AmMC0XXA
PRELIMINARY
Data Protection
Write Pulse “Glitch” Protection
An optional mechanical write protect switch provides
user-initiated write protection. When this switch is activated, WE# is internally forced high. The Flash memory
command register is disabled from accepting any write
commands. This prevents the card from responding to
any commands (for example, an Autoselect command).
See Figure 3.
Noise pulses of less than 5 ns (typical) on OE#, CE#,
or WE# will neither initiate a write cycle nor change the
command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH, or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
Power-Up Write Inhibit
Power-up of the device with CE# = WE# = VIL and OE#
= VIH will not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to the read mode on power-up.
Write Enabled
Read Mode
Write Disabled
20975D-4
Figure 3. Write Protect Switch
(Card Right Side View)
In addition to card-level data protection, AMD Flash
Miniature Cards offer several device-level data protection features.
Device-Level Data Protection
AMD Flash memory devices offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up, each device automatically
resets the internal state machine to the read mode. The
control register architecture allows alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
AMD Flash memory devices also incorporate the following features to prevent inadvertent write cycles
resulting from V C C power-up and power-dow n
transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC powerup and power-down, the AMD memory devices in
the Miniature Card lock out write cycles for VCC <
V LKO (see “DC Characteristics” on page 25 for voltages). When VCC < V LKO, the command register is
disabled, all internal program/erase circuits are disabled, and the device resets to the read mode.
These memory devices ignore all writes until VCC >
V LKO. The user must ensure that the control pins
are in the correct logical state when VCC > V LKO to
prevent unintentional writes.
Two Card Enable (CE#) pins are available on the
memory card. Both CE# pins must be active low for
word-wide read accesses. Only one CE# is required for
byte-wide accesses. The CE# pins select and determine when to apply power to the high-byte and lowbyte memory devices. The Output Enable (OE#) controls gating accessed data from the memory device
outputs.
The Miniature card automatically powers up in the
read/reset state. In this case, a command sequence is
not required to read data. Standard microprocessor
read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory
content occurs during the power transition. Refer to the
AC Read Characteristics and Waveforms for the specific timing parameters.
Output Disable
Data outputs from the card are disabled when OE# is
at a logic-high level. Under this condition, outputs are in
the high-impedance state.
Standby Operations
Byte-wide read accesses only require half of the
read/write output buffer (x16) to be active. In addition,
only one memory device is active within either the high
order or low order bank. Activation of the appropriate
half of the output buffer is controlled by the combination
of both CE# pins. The CE# pins also control power to
the high and low-order banks of memory. Outputs of
the memory bank not selected are placed in the high
impedance state. The individual memory device is activated by the address decoders. The other memory
devices operate in standby. An active memory device
continues to draw power until completion of a write or
erase operation if the card is de-selected in the process
of one of these operations.
AmMC0XXA
11
PRELIMINARY
Autoselect Operation
A host system or external card reader/writer can determine the on-card manufacturer and device I.D. codes.
Codes are available after writing the 90h command to
the command register of a memory device, as shown in
Tables 5 through 10. When the autoselect command is
issued to card address 00000h, the Miniature Card
retur ns the manufacturer I.D. If the autoselect
command is issued to card address 00001h, the Miniature Card provides the device I.D.
To t e r m i n a t e t h e Au t o S e l e c t o p e r a t i o n , t h e
Read/Reset command sequence must be written to the
same device. The Autoselect command operates only
if the card is not write protected.
Sector Group Protection
Sector group protection can be used to permanently
disable program and erase operations in any combination of sector groups on the Flash memory components
used in AMD Miniature Cards. Each sector group consists of four adjacent sectors within each device. The
pattern begins at SA0: SA0–3, SA4–7, SA8–11, and so
on. This protection must be performed prior to manufacturing the Miniature Cards. None of the sector
groups are protected on the standard Miniature Card
product offerings.
The host system must compensate for these protected
sector groups by determining their locations, then
ignoring those locations for reading and writing data. To
12
determine whether a sector group is protected, the
system would write the first three cycles of the Autoselect command, then on the fourth cycle, read at the
address (SA)02h, where SA is the sector address (see
Tables 11 and 12) within an individual device. A protected sector group produces “01h”, and an unprotected sector group produces “00h”.
Write Operations
Write and erase operations are valid only when VCC is
above 4.5 V. This activates the state machine of an
addressed memory device. The command register is a
latch which saves address, commands, and data information used by the state machine and memory array.
When Write Enable (WE#) and appropriate CE#
signals are at a logic-level low, and Output Enable
(OE#) is at a logic-high, the command register is
enabled for write operations. The falling edge of WE#
latches address information and the rising edge latches
data/command information.
Write or erase operations are performed by writing
appropriate data patterns to the command register of
accessed Flash memory devices.
The byte-wide commands are defined in Tables 6, 7, 9,
and 10; word-wide commands are defined in Tables 5
and 8. Note that the Erase Suspend (B0h) and Erase
Resume (30h) commands are valid only while the
Sector Erase operation is in progress.
AmMC0XXA
PRELIMINARY
Table 5.
Word Command Definitions for 2 Mbyte Cards
Bus Cycles (Notes 2–9)
Second
Third
Fourth
Fifth
Sixth
Embedded Command Sequence
(Note 1)
Cycles
First
Read
1
RA
RW
Reset
1
XXX
F0F0
Autoselect Manufacturer ID (Note 4)
4
555
AAAA
2AA
5555
555
9090
X00
0101
Autoselect Device ID (Note 4)
4
555
AAAA
2AA
5555
555
9090
X01
D5D5
Word Write
4
555
AAAA
2AA
5555
555
A0A0
PA
PW
Device Erase
6
555
AAAA
2AA
5555
555
8080
555
AAAA
2AA
5555
555
1010
Sector Erase
6
555
AAAA
2AA
5555
555
8080
555
AAAA
2AA
5555
SA
3030
Sector Erase Suspend (Note 7)
1
XXX
B0B0
Sector Erase Resume (Note 8)
1
XXX
3030
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Legend:
X = Don’t care
PW = Data to be programmed at location PA. Data is latched
on the rising edge of WE#.
RA = Address of the memory location to be read.
RW = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
SA = Address of the sector to be erased. Refer to Table 11 for
sector addresses.
Notes:
1. Write protect must not be enabled for proper operation of
all commands. No command required for reading array
data, and can thus be done with write protect enabled.
2. During word addressing, CEL# = 0, CEH# = 0, and
address is applied to Memory Device Pair 0 (S0 and S1).
For host-to-card address bit connections, see Figure 2.
7. The Erase Suspend command is valid only during a
sector erase operation. Refer to “Sector Erase Suspend”.
8. The Erase Resume command is valid only during the
Erase Suspend mode.
9. See Table 4 for read/write modes.
3. All values are in hexadecimal.
4. The last bus cycle in an autoselect command sequence is
a read operation.
5. Word = high byte + low byte.
6. Address bits A19–A11 = X = Don’t Care for all commands
except for Read Address (RA), Program Address (PA),
and Sector Address (SA).
AmMC0XXA
13
PRELIMINARY
Table 6.
Even Byte Command Definitions for 2 Mbyte Cards
Cycles
Bus Cycles (Notes 2–9)
Addr
Read
1
RA
RD
Reset
1
XXX
XXF0
Autoselect Manufacturer ID (Note 4)
4
555
XXAA
2AA
XX55
555
XX90
X00
XX01
Autoselect Device ID (Note 4)
4
555
XXAA
2AA
XX55
555
XX90
X01
XXD5
Byte Write
4
555
XXAA
2AA
XX55
555
XXA0
PA
PD
Device Erase
6
555
XXAA
2AA
XX55
555
XX80
555
XXAA
2AA
XX55
555
XX10
Sector Erase
6
555
XXAA
2AA
XX55
555
XX80
555
XXAA
2AA
XX55
SA
XX30
Sector Erase Suspend (Note 6)
1
XXX
XXB0
Sector Erase Resume (Note 7)
1
XXX
XX30
Embedded Command Sequence
(Note 1)
First
Data
Second
Third
Fourth
Addr
Data
Addr
Data
Addr
Data
Fifth
Sixth
Addr
Data
Addr
Data
Note for Table 6: During even (low) byte accesses, CEL# = 0, CEH# = 1, and address is applied to Memory Device 0 (S0) only.
Table 7. Odd Byte Command Definitions for 2 Mbyte Cards
Cycles
Bus Cycles (Notes 2–9)
Addr
Read
1
RA
RD
Reset
1
XXX
F0XX
2AA
55XX
555
F0XX
RA
RD
Autoselect Manufacturer ID (Note 4)
4
555
AAXX
2AA
55XX
555
90XX
X00
01XX
Autoselect Device ID (Note 4)
4
555
AAXX
2AA
55XX
555
90XX
X01
D5XX
Byte Write
4
555
AAXX
2AA
55XX
555
A0XX
PA
PDXX
Device Erase
6
555
AAXX
2AA
55XX
555
80XX
555
AAXX
2AA
55XX
555
10XX
Sector Erase
6
555
AAXX
2AA
55XX
555
80XX
555
AAXX
2AA
55XX
SA
30XX
Sector Erase Suspend (Note 6)
1
XXX
B0XX
Sector Erase Resume (Note 7)
1
XXX
30XX
Embedded Command Sequence
(Note 1)
First
Data
Second
Third
Fourth
Addr
Data
Addr
Data
Addr
Data
Fifth
Sixth
Addr
Data
Addr
Data
Note for Table 7: During odd (high) byte accesses, CEL#= 1, CEH# = 0, and address is applied to Memory Device 1 (S1) only.
Legend for Tables 6 and 7:
X = Don’t care
PW = Data to be programmed at location PA. Data is latched on
the rising edge of WE#.
RA = Address of the memory location to be read.
SA = Address of the sector to be erased. Refer to Table 11 for
sector addresses.
RW = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
Notes for Tables 6 and 7:
1. Write protect must not be enabled for proper operation of all
commands. No command required for reading array data,
and can thus be done with write protect enabled.
6. The Erase Suspend command is valid only during a sector
erase operation. Refer to “Sector Erase Suspend”.
2. For host-to-card address bit connections, see Figure 2.
7. The Erase Resume command is valid only during the Erase
Suspend mode.
3. All values are in hexadecimal.
8. See Table 4 for read/write modes.
4. The last cycle of an autoselect command sequence is a read
operation.
5. Address bits A19–A11 = X = Don’t Care for all commands
except for Read Address (RA), Program Address (PA), and
Sector Address (SA).
14
AmMC0XXA
PRELIMINARY
Table 8.
Word Command Definitions for 4 and 8 Mbyte Cards
Embedded Command Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–9)
Read
1
RA
RW
Reset
1
XXXX
F0F0
Autoselect Manufacturer ID (Note 4)
4
XXXX AAAA XXXX
Autoselect Device ID (Note 4)
4
Word Write
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr Data
Addr Data
Addr Data
Addr Data
Addr Data
5555
XXXX
9090
XX00
0101
XXXX AAAA XXXX
5555
XXXX
9090
XX01
3D3D
4
XXXX AAAA XXXX
5555
XXXX
A0A0
PA
PW
Device Erase
6
XXXX AAAA XXXX
5555
XXXX
8080
XXXX AAAA
2AAA
5555
XXXX
1010
Sector Erase
6
XXXX AAAA XXXX
5555
XXXX
8080
XXXX AAAA
2AAA
5555
SA
3030
Sector Erase Suspend (Note 7)
1
XXXX
B0B0
Sector Erase Resume (Note 8)
1
XXXX
3030
Legend:
X = Don’t care
PW = Data to be programmed at location PA. Data is latched
on the rising edge of WE#.
RA = Address of the memory location to be read.
RW = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
SA = Address of the sector to be erased. Refer to Table 12 for
sector addresses.
Notes:
1. Write protect must not be enabled for proper operation of
all commands. No command required for reading array
data, and can thus be done with write protect enabled.
6. Address bits A19–A11 = X = Don’t Care for all commands
except for Read Address (RA), Program Address (PA),
and Sector Address (SA).
2. During word addressing, CEL# = 0, CEH# = 0, and
address is applied to Memory Device Pair 0 (S0 and S1).
On 8 Mbyte cards, address for Memory Device Pair 1 =
(Addr) + 400000h, and address is applied to S2 and S3.
For host-to-card address bit connections, see Figure 2.
7. The Erase Suspend command is valid only during a
sector erase operation. Refer to “Sector Erase Suspend”.
3. All values are in hexadecimal.
8. The Erase Resume command is valid only during the
Erase Suspend mode.
9. See Table 4 for read/write modes.
4. The last bus cycle in an autoselect command sequence is
a read operation.
5. Word = high byte + low byte.
AmMC0XXA
15
PRELIMINARY
Embedded Command Sequence
(Note 1)
Cycles
Table 9. Even Byte Command Definitions for 4 and 8 Mbyte Cards
Bus Cycles (Notes 2–9)
First
Addr
Data
RA
RD
Second
Addr
Third
Data
Addr
Data
Fourth
Addr
Data
Fifth
Addr
Data
Sixth
Addr
Data
Read
1
Reset
1
XXXX XXF0
Autoselect Manufacturer ID (Note 4)
4
XXXX XXAA XXXX XX55 XXXX XX90 XX00 XX01
Autoselect Device ID (Note 4)
4
XXXX XXAA XXXX XX55 XXXX XX90 XX01 XX3D
Byte Write
4
XXXX XXAA XXXX XX55 XXXX XXA0
Device Erase
6
XXXX XXAA XXXX XX55 XXXX XX80 XXXX XXAA XXXX XX55 XXXX XX10
Sector Erase
6
XXXX XXAA XXXX XX55 XXXX XX80 XXXX XXAA XXXX XX55
Sector Erase Suspend (Note 6)
1
XXXX XXB0
Sector Erase Resume (Note 7)
1
XXXX XX30
PA
PD
SA
XX30
Note for Table 9: During high byte addressing, CEL# = 1, CEH# = 0, and address applied to Memory Device 1 (S1) = (Addr) + 200000h.
On 8 Mbyte cards, address for S3 = (Addr) + 400000h + 200000h.
Embedded Command Sequence
(Note 1)
Read
Odd Byte Command Definitions for 4 and 8 Mbyte Cards
Bus Cycles (Notes 2–9)
Cycles
Table 10.
Addr
Data
1
RA
RD
First
Second
Addr
Third
Data
Addr
Data
Fourth
Addr
Data
Reset
1
XXXX F0XX
Autoselect Manufacturer ID (Note 4)
4
XXXX AAXX XXXX 55XX XXXX 90XX XX00 01XX
Autoselect Device ID (Note 4)
4
XXXX AAXX XXXX 55XX XXXX 90XX XX01 3DXX
Byte Write
4
XXXX AAXX XXXX 55XX XXXX A0XX
PA
Fifth
Addr
Data
Sixth
Addr
Data
PD
Device Erase
6
XXXX AAXX XXXX 55XX XXXX 80XX XXXX AAXX XXXX 55XX XXXX 10XX
Sector Erase
6
XXXX AAXX XXXX 55XX XXXX 80XX XXXX AAXX XXXX 55XX
Sector Erase Suspend (Note 6)
1
XXXX B0XX
Sector Erase Resume (Note 7)
1
XXXX 30XX
SA
30XX
Note for Table 7: During low byte addressing, CEL# = 0, CEH# = 1, and address applied to Memory Device 0 (S0) = (Addr). On 8 Mbyte
cards, address for S2 = (Addr) + 400000h.
Legend for Tables 6 and 7:
X = Don’t care
PW = Data to be programmed at location PA. Data is latched on
the rising edge of WE#.
RA = Address of the memory location to be read.
SA = Address of the sector to be erased. Refer to Table 11 for
sector addresses.
RW = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
Notes for Tables 6 and 7:
1. Write protect must not be enabled for proper operation of all
commands. No command required for reading array data,
and can thus be done with write protect enabled.
6. The Erase Suspend command is valid only during a sector
erase operation. Refer to “Sector Erase Suspend”.
2. For host-to-card address bit connections, see Figure 2.
7. The Erase Resume command is valid only during the Erase
Suspend mode.
3. All values are in hexadecimal.
8. See Table 4 for read/write modes.
4. The last cycle of an autoselect command sequence is a read
operation.
5. Address bits A19–A11 = X = Don’t Care for all commands
except for Read Address (RA), Program Address (PA), and
Sector Address (SA).
16
AmMC0XXA
PRELIMINARY
Table 11.
Memory Sector Addresses for 2 Mbyte Card
Card Address Bits
Device 0 and/or 1 (Note 1)
Sector
A19
A18
A17
A16
Card Address Range
0
0
0
0
0
00000h–0FFFFh
1
0
0
0
1
10000h–1FFFFh
2
0
0
1
0
20000h–2FFFFh
3
0
0
1
1
30000h–3FFFFh
4
0
1
0
0
40000h–4FFFFh
5
0
1
0
1
50000h–5FFFFh
6
0
1
1
0
60000h–6FFFFh
7
0
1
1
1
70000h–7FFFFh
8
1
0
0
0
80000h–8FFFFh
9
1
0
0
1
90000h–9FFFFh
10
1
0
1
0
A0000h–AFFFFh
11
1
0
1
1
B0000h–BFFFFh
12
1
1
0
0
C0000h–CFFFFh
13
1
1
0
1
D0000h–DFFFFh
14
1
1
1
0
E0000h–EFFFFh
15
1
1
1
1
F0000h–FFFFFh
Notes:
1. For word addressing, devices 0 and 1 (S0 and S1) together form Memory Device Pair 0. Refer to the block diagram for device
connections.
2. Card address bits range from A0 to A19. Host address bits range from A0 to A20. Host address bit A0 is used for controlling
the CEL# and CEH# inputs to the card. Refer to Figure 2 for host-to-card address bit connections.
AmMC0XXA
17
PRELIMINARY
Table 12.
Memory Sector Addresses for 4 and 8 Mbyte Cards
Card Address Bits
Device 0 and/or 1
Device 2 and/or 3
Sector
A20
A19
A18
A17
A16
Card Address Range
(Note 2)
Card Address Range
(Notes 2, 3)
0
0
0
0
0
0
00000h–0FFFFh
200000h–20FFFFh
1
0
0
0
0
1
10000h–1FFFFh
210000h–21FFFFh
2
0
0
0
1
0
20000h–2FFFFh
220000h–22FFFFh
3
0
0
0
1
1
30000h–3FFFFh
230000h–23FFFFh
4
0
0
1
0
0
40000h–4FFFFh
240000h–24FFFFh
5
0
0
1
0
1
50000h–5FFFFh
250000h–25FFFFh
6
0
0
1
1
0
60000h–6FFFFh
260000h–26FFFFh
7
0
0
1
1
1
70000h–7FFFFh
270000h–27FFFFh
8
0
1
0
0
0
80000h–8FFFFh
280000h–28FFFFh
9
0
1
0
0
1
90000h–9FFFFh
290000h–29FFFFh
10
0
1
0
1
0
A0000h–AFFFFh
2A0000h–2AFFFFh
11
0
1
0
1
1
B0000h–BFFFFh
2B0000h–2BFFFFh
12
0
1
1
0
0
C0000h–CFFFFh
2C0000h–2CFFFFh
13
0
1
1
0
1
D0000h–DFFFFh
2D0000h–2DFFFFh
14
0
1
1
1
0
E0000h–EFFFFh
2E0000h–2EFFFFh
15
0
1
1
1
1
F0000h–FFFFFh
2F0000h–2FFFFFh
16
1
0
0
0
0
100000h–10FFFFh
300000h–30FFFFh
17
1
0
0
0
1
110000h–11FFFFh
310000h–31FFFFh
18
1
0
0
1
0
120000h–12FFFFh
320000h–32FFFFh
19
1
0
0
1
1
130000h–13FFFFh
330000h–33FFFFh
20
1
0
1
0
0
140000h–14FFFFh
340000h–34FFFFh
21
1
0
1
0
1
150000h–15FFFFh
350000h–35FFFFh
22
1
0
1
1
0
160000h–16FFFFh
360000h–36FFFFh
23
1
0
1
1
1
170000h–17FFFFh
370000h–37FFFFh
24
1
1
0
0
0
180000h–18FFFFh
380000h–38FFFFh
25
1
1
0
0
1
190000h–19FFFFh
390000h–39FFFFh
26
1
1
0
1
0
1A0000h–1AFFFFh
3A0000h–3AFFFFh
27
1
1
0
1
1
1B0000h–1BFFFFh
3B0000h–3BFFFFh
28
1
1
1
0
0
1C0000h–1CFFFFh
3C0000h–3CFFFFh
29
1
1
1
0
1
1D0000h–1DFFFFh
3D0000h–3DFFFFh
30
1
1
1
1
0
1E0000h–1EFFFFh
3E0000h–3EFFFFh
31
1
1
1
1
1
1F0000h–1FFFFFh
3F0000h–3FFFFFh
Notes:
1. For word addressing, devices 0 and 1 (S0 and S1) together form Memory Device Pair 0; devices 2 and 3 (S2 and S3) form
Memory Device Pair 1. Refer to the block diagram for device connections.
2. The 4 Mbyte card address bits range from A0 to A20. Host address bits range from A0 to A21. Host address bit A0 is used
for controlling the CEL# and CEH# inputs to the card. Refer to Figure 2 for host-to-card address bit connections.
3. The 8 Mbyte card address bits range from A0 to A21. A21 is used to select devices 2 and 3 (S2 and S3). Host address bits
range from A0 to A22. Host address bit A0 is used for controlling the CEL# and CEH# inputs to the card. Refer to Figure 2
for host-to-card address bit connections.
18
AmMC0XXA
PRELIMINARY
PROGRAM AND ERASE OPERATIONS
AMD Flash Memory devices include Embedded
Algorithms (Embedded Erase and Embedded Program) that allow the host to simply issue a command,
after which it is free to perform other tasks. The host
then only needs to monitor appropriate status bits to
determine when the operation is complete.
Embedded Erase Algorithm
When erasing a sector or device, the Embedded Erase
algorithm does not require the host to first entirely preprogram the device. Upon executing the Embedded
Erase command sequence, the addressed memory
sector or memory device automatically writes and verifies the entire memory device or memory sector for an
all “0” data pattern. The system is not required to
provide any controls or timing during these operations.
When the memory sector or memory device is automatically verified to contain an all “0” pattern, a
self-timed chip erase-and-verify begins. The erase and
verify operations are complete when the data on D7
(D15 on the odd byte) of the memory sector or memory
device is “1” (see Write Operation Status section), at
which time the device returns to the read mode. The
system is not required to provide any control or timing
during these operations. If a Reset command is issued
while the erase operation is in progress, the erase
operation will stop, and the data in that device will be
undefined. In that case, restart the erase on that sector
and allow it to complete.
When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin
has been achieved for the memory array (no erase
verify command is required). The margin voltages are
internally generated in the same manner as when the
standard erase verify command is used.
The Embedded Erase command sequence is a
command only operation that stages the memory
sector or memory device for automatic electrical
erasure of all bytes in the array. The automatic erase
begins on the rising edge of the WE# and terminates
when the data on D7 of the memory sector or memory
device is “1” (see Write Operation Status section) at
which time the device returns to the Read mode.
Please note that for the memory device or memory
sector erase operation, Data Polling may be performed
at any address in that device or sector.
Figure 4 and Table 13 illustrate the Embedded Erase
Algorithm, a typical command string and bus operations.
As described earlier, once the memory sector in a
device or memory device completes the Embedded
Erase operation, it returns to the Read mode and
addresses are no longer latched. Therefore, the device
requires that a valid address input to the device is
supplied by the system at this particular instant of time.
Otherwise, the system will never read a “1” on D7. A
system designer h as the follow ing choic es to
implement the Embedded Erase algorithm:
1. The host may keep the sector address (within any
of the sectors being erased) valid during the entire
Embedded Erase operation.
2. Once the system executes the Embedded Erase
command sequence, the host may remove the address from the device and perform other tasks. The
host is required to keep track of the valid sector address by loading it into a temporary register. When
the host comes back to Data Poll the device, it must
reassert the same address.
3. The host may monitor BUSY# (RY/BY#) to determine the status of the Embedded Algorithm in
progress. A “0” indicates that the device is busy; a
“1” indicates that the algorithm is complete.
Sector Erase
Sector erase is a six bus cycle operation. There are
two “unlock” write cycles. These are followed by
writing the “set-up” command. Two more “unlock”
write cycles are then followed by the sector erase
command. The sector address (any address location
within the desired sector) is latched on the falling edge
of WE# (or CE#), whichever occurs later, while the
command (data) is latched on the rising edge of the
WE# (or CE#) pulse, whichever occurs first. A
time-out of 100 µs from the rising edge of the last
sector erase command will initiate the sector erase
command(s)
Multiple sectors may be queued for concurrent erase
by writing the six bus cycle operations as described
above. This sequence is followed with writes of the
sector erase command 30h to addresses in other
sectors desired to be concurrently erased. A time-out
of 100 µs from the rising edge of the WE# (or CE#)
pulse for the last sector erase command will initiate the
sector erase. If another sector erase command is
written within the 100 µs time-out window the timer is
reset. Any command other than sector erase within the
time-out window will reset the device to the read mode,
ignoring the previous command string (refer to Write
Operation Status section for Sector Erase Timer operation). Loading the sector erase buffer may be done in
any sequence and with anysector number.
Sector erase does not require the user to program the
device prior to erase. The device automatically programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors, the remaining unselected sectors are not
affected. The system is not required to provide any
controls or timings during these operations. A Reset
command issued after the device has begun execution
stops the erase operation, but the data in the sector will
AmMC0XXA
19
PRELIMINARY
be undefined. In that case, restart the erase on that
sector and allow it to complete.
The automatic sector erase begins after the 100 µs
time out from the rising edge of the WE# (or CE#)
pulse for the last sector erase command pulse and
terminates when the data on D7 is “1” (see Write
Operation Status section) at which time the device
returns to read mode. Data Polling must be performed at an address within any of the sectors being
erased.
Figure 4 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Table 13.
Bus
Operation
Embedded Erase Algorithm
Command
Wait for VCC ramp
Standby
Write
Comments
Embedded Erase
command sequence
6 bus cycle operation
Data Poll or check
BUSY# (RY/BY#) to
verify erasure
Read
CE#) pulse. Data is internally latched on the rising
edge of the WE# pulse. The rising edge of WE# also
begins the programming operation. The system is not
required to provide further control or timing. The device
will automatically provide an adequate internally generated write pulse and verify margin. The automatic programming operation is completed when the data on D7
of the addressed memory sector or memory device is
equivalent to data written to this bit (see Write Operation Status section) at which time the device returns to
the Read mode (no write verify command is required).
Addresses are latched on the falling edge of WE#
during the Embedded Program command execution
and hence the system is not required to keep the
addresses stable during the entire Programming operation. However, once the device completes the
Embedded Program operation, it returns to the Read
mode and addresses are no longer latched. Therefore,
the device requires that a valid address input to the
device is supplied by the system at this particular
instant of time. Otherwise, the system will never read a
valid data on D7. A system designer has two choices to
implement the Embedded Programming algorithm:
1. The system (CPU) keeps the address valid during
the entire Embedded Programming operation, or
2. Once the system executes the Embedded Programming command sequence, the CPU takes away the
address from the device and becomes free to do
other tasks. In this case, the CPU is required to
keep track of the valid address by loading it into a
temporary register. When the CPU comes back for
perfor ming Data Polling, it should reasser t
the same address.
Start
Write Embedded Erase
Command Sequence
(See Tables 5–10)
Data Poll from Device
3. The host may monitor BUSY# (RY/BY#) to determine the status of the Embedded Algorithm in
progress. A “0” indicates that the device is busy; a
“1” indicates that the algorithm is complete.
or wait for BUSY#
(RY/BY#)
Erasure Complete
20975D-5
Figure 4. Embedded Erase Algorithm
Note: The latest release of the software drivers for AMD
Miniature Cards and devices may be downloaded from the
AMD web site at http://www.amd.com.
Embedded Program Algorithm
The Embedded Program setup is a four bus cycle operation that stages the addressed memory sector or
memory device for automatic programming.
However, since the Embedded Programming operation
takes only 8 µs typically, it may be easier for the CPU
to keep the address stable during the entire Embedded
Programming operation instead of reasserting the valid
address during Data Polling. Anyway, this has been left
to the system designer’s choice to go for either operation. Any commands written to the device during this
period will be ignored. Figure 5 and Table 14 illustrate
the Embedded Program Algorithm, a typical command
string, and bus operation.
Once the Embedded Program setup operation is performed, the next WE# (or CE#) pulse causes a transition to an active programming operation. Addresses
are internally latched on the falling edge of the WE# (or
20
AmMC0XXA
PRELIMINARY
Table 14.
Bus
Operation
Sector Erase Suspend
Embedded Program Algorithm
Command
Standby
Comments
Wait for VCC ramp
Write
Embedded Program
3 bus cycle operation
command sequence
Write
Program
Address/Data
1 bus cycle operation
Data Poll or check
BUSY# (RY/BY#) to
verify program
Read
Start
Write Embedded Write Command
Sequence per Tables 5– 10
When the Sector Erase Suspend command is written
during a Sector Erase operation, the chip will take between 0.1 µs to 10 µs to suspend the erase operation
and go into erase suspended read mode (pseudo-read
mode), during which the user can read from a sector
that is NOT being erased. A read from a sector being
erased may result in invalid data. The user must monitor D6 to determine if the chip has entered the pseudo-read mode, at which time D6 stops toggling. Note
that the user must keep track of what state the chip is
in since there is no external indication of whether the
chip is in pseudo-read mode or actual read mode. After
the user writes the Sector Erase Suspend command
and waits until D6 stops toggling, data reads from the
device may then be performed. Any further writes of
the Sector Erase Suspend command at this time will be
ignored.
Data Poll Device
or wait for BUSY# (RY/BY#)
N
Verify
Data
Y
N
Increment
Address
Last
Address
Y
Completed
20975D-6
Figure 5.
Sector Erase Suspend command allows the user to interrupt the chip and then do data reads (not program)
from a non-busy sector while it is in the middle of a Sector Erase operation (which may take up to several seconds). This command is applicable ONLY during the
Sector Erase operation and will be ignored if written
during the chip Erase or Programming operation. The
Erase Suspend command (B0h) will be allowed only
during the Sector Erase Operation that will include the
sector erase time-out period after the Sector Erase
commands (30h). Writing this command during the
time-out will result in immediate termination of the
time-out period. Any subsequent writes of the Sector
Erase command will be ignored as such, but instead
will be taken as the Erase Resume command. Note
that any other commands during the time out will reset
the device to read mode. The addresses are
don’t-cares in writing the Erase Suspend or Erase Resume commands.
Embedded Program Algorithm
To resume the operation of Sector Erase, the Resume
command (30H) should be written. Any further writes of
the Resume command at this point will be ignore.
Another Sector Erase Suspend command can be
written after the chip has resumed.
Reset Command
Write Operation Status
The device automatically powers up in the read/reset
state. A command sequence is not required to read
data in this case. Standard microprocessor cycles retrieve array data. This default state ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Characteristics section for the specific timing parameters.
Table 15 shows the status bit states for device program
and erase operations.
The reset operation is initiated by writing the read/reset
command sequence into the command register. Microprocessor read cycles retrieve array data from the
memory. The device remains enabled for reads until
the command register contents are altered.
Data Polling—D7 (D15 on Odd Byte)
The AMD Flash Miniature Card features Data Polling
as a method to indicate to the host system that the
Embedded algorithms are either in progress or completed (The host may alternatively monitor BUSY#
(RY/BY#).
While the Embedded Programming algorithm is in operation, an attempt to read the device will produce the
complement of expected valid data on D7 of the
addressed memory sector or memory device. Upon
completion of the Embedded Program algorithm an
AmMC0XXA
21
PRELIMINARY
attempt to read the device will produce valid data on D7.
The Data Polling feature is valid after the rising edge of
the fourth WE# pulse of the four write pulse sequence.
While the Embedded Erase algorithm is in operation,
D7 will read “0” until the erase operation is completed.
Upon completion of the erase operation, the data on D7
will read “1”.
The Data Polling feature is only active during the
Embedded Programming or Erase algorithms. Please
note that D7 may change asynchronously while Output
Enable (OE#) is asserted low. This means that the
device is driving status information on D7 at one instant
of time and then the byte’s valid data at the next instant
of time. Depending on when the system samples the
D7 output, it may read either the status or valid data.
Table 15.
Even if the device has completed the Embedded operation and D7 has a valid data, the data outputs on D0D6 may be still invalid since the switching time for data
bits (D0-D7) will not be the same. This happens since
the internal delay paths for data bits (D0-D7) within the
device are different. The valid data will be provided only
after a certain time delay (>tOE). Please refer to Figure
9 for a detailed timing diagram. See Figure 6 for the
Data Polling algorithm.
Toggle Bit—D6 (D14 on Odd Byte)
The toggle bit is used for entering the Erase Suspend
mode. Refer to the previous section entitled “Sector
Erase Suspend” and Table 15 for information on this
bit.
Hardware Sequence Flags
Status
D7
D6
D5
D3
D2
D7
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle
(Note 1)
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
D7
Toggle
(Note 2)
0
1
1
(Note 3)
D7
Toggle
1
0
1
0
Toggle
1
1
N/A
D7
Toggle
1
1
N/A
Byte Program in Embedded Program Algorithm
Embedded Erase Algorithm
Erase Suspend Read
(Erase Suspended Sector)
In Progress
Erase Suspended Mode
Byte Program in Embedded Program Algorithm
Exceeded
Time Limits
Program/Erase in Embedded Erase Algorithm
Erase Suspended Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Notes:
1. Performing successive read operations from the erase-suspended sector will cause D2 to toggle.
2. Performing successive read operations from any address will cause D6 to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the D2 bit.
However, successive reads from the erase-suspended sector will cause D2 to toggle.
BUSY# (RY/BY#—Ready/Busy)
The BUSY# signal indicates to the host the status of
operations within the Miniature Card. The BUSY#
signal is tied to the components’ RY/BY# pins.
The RY/BY# signal from AMD Flash devices in the
Miniature Card indicate that the Embedded Algorithms are either in progress or have been completed.
If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY# pin is low, the device will
not accept any additional program or erase commands with the exception of the Erase Suspend com-
22
mand. If a Flash device is placed in an Erase Suspend
mode, the RY/BY# output will be high. Refer to the
section “Sector Erase Suspend” for more information.
During programming, the RY/BY# pin is driven low after
the rising edge of the fourth WE# pulse. During an
erase operation, the RY/BY# pin is driven low after the
rising edge of the sixth WE# pulse. The RY/BY# pin
should be ignored while RESET# is at VIL.
AmMC0XXA
PRELIMINARY
WORD-WIDE PROGRAMMING AND
ERASING
Word-Wide Programming
START
DQ7 = Data?
The Word-Wide Programming sequence will be as
usual per Table 5 or 8. The Program word command is
A0A0H. Each byte is independently programmed. For
example, if the high byte of the word indicates the
successful completion of programming via one of its
write status bits such as D15, software polling should
continue to monitor the low byte for write completion
and data verification, or vice versa. During the
Embedded Programming operations the device executes programming pulses in 8 µs increments. Status
reads provide information on the progress of the byte
programming relative to the last complete write pulse.
Status information is automatically updated upon completion of each internal write pulse. Status information
does not change within the 8 µs write pulse width.
Yes
No
No
DQ5 = 1?
Yes
DQ7 = Data?
Yes
Word-Wide Sector Erasing
The Word-Wide Sector Erasing of a memory device pair
is similar to word-wide programming. The erase word
command is a six-bus-cycle command sequence (see
Tables 5 and 8). Each byte is independently erased and
verified. Word-wide erasure reduces total erase time
when compared to byte erasure. Each Flash memory
device in the card may erase at different rates. Therefore, each device (byte) must be verified separately.
No
FAIL
PASS
20975D-7
Note: D7 is rechecked even if D5 = 1 because D7 may
change simultaneously with D5.
Figure 6.
Data Polling Algorithm
AmMC0XXA
23
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . –40°C to +90°C
Commercial Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . . –40°C to +85°C
Case Temperature (TC). . . . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Voltage at All Pins (Note 1) . . . . . . . . –0.5 V to +7.0 V
Case Temperature (TC). . . . . . . . . . . .–40°C to +85°C
VCC (Note 1) . . . . . . . . . . . . . . . . . . . –2.0 V to +7.0 V
VCC Supply Voltages
Output Short Circuit Current (Note 2) . . . . . . 200 mA
AmMC0XXAWP-100, -150 . . . . . . . . +4.5 V to +5.5 V
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshoot VSS to –2.0 V for
periods of up to 20 ns. Maximum DC voltage on output
and I/O pins is VCC + 0.5 V. During voltage transitions,
outputs may overshoot to VCC + 2.0 V for periods up to
20ns.
Operating ranges define those limits between which the
functionality of the device is guaranteed.
2. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Conditions equal VOUT = 0.5 V or 5.0 V, VCC = VCCmax.
These values are chosen to avoid test problems caused
by tester ground degradation. This parameter is sampled
and not 100% tested, but guaranteed by characterization.
3. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device
reliability.
24
AmMC0XXA
PRELIMINARY
DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
ILI
Input Leakage Current
VIN = VSS to VCC, VCC = VCC max
±5
µA
ILO
Output Leakage Current
VIN = VSS to VCC, VCC = VCC max
±5
µA
ICCS
VCC Standby Current
CEL#, CEH#, RESET# = VIH
4
mA
VCC Supply Current
(Note 2)
RESET# = VIH;
CEL# and CEH# = VIL
Read
80
mA
ICC
Program
120
mA
ICC
VCC Standby Current
CE# = VCC ± 0.3 V
60
µA
VIL
Input Low Voltage
VCC = 5.0 V
–0.5
0.8
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.5
V
VOL
Output Low Voltage
IOUT = 12 mA
0.1 VCC
V
VOH
Output High Voltage
IOUT = –2.5 mA
VLKO
Low VCC Lock-Out Voltage
0.9 VCC
V
3.2
4.2
V
Notes:
1. VCC = 5.0 volts ± 10%
2. Supply current is a max RMS value. Read frequency = 5 MHz.
CONNECTOR DC SPECIFICATIONS
Parameter
Min
Interface Signal Resistance (Note 2)
Interface Signal Current (Notes 1, 2)
Max
Units
2.0
Ω
125
Power/Insertion Signal Resistance
mA
0.060
Power/Insertion Signal Current (Note 1)
500
Ω
mA
Notes:
1. This current is a minimum that the connector should withstand, and a maximum that the host should provide.
2. On the host, these specifications must be met for one conducting channel on connectors.
CARD AND PAD CAPACITANCE
Parameter Symbol
Parameter Description
Test Conditions
Max
Unit
CCARD
Card Input Capacitance
40
pF
CHOST
System Load Capacitance
120
pF
CI/O
I/O Capacitance D0–D15
40
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
AmMC0XXA
25
PRELIMINARY
AC CHARACTERISTICS
Read-only Operations
Parameter Symbol
Card Speed
Unit
Parameter Description
JEDEC
Standard
-100
-150
tAVAV
tRC
Read Cycle Time
Min
100
150
ns
tELQV
tCE
Chip Enable Access Time
Max
100
150
ns
tAVQV
tACC
Address Access Time
Max
100
150
ns
tGLQV
tOE
Output Enable Access Time
Max
40
50
ns
tELQX
tLZ
Chip Enable to Output in Low-Z
Min
0
0
ns
tEHQZ
tDF
Chip Disable to Output in High-Z
Max
20
30
ns
tGLQX
tOLZ
Output Enable to Output in Low-Z
Min
0
0
ns
tGHQZ
tDF
Output Disable to Output in High-Z
Max
20
30
ns
tAXQX
tOH
Output Hold from First of Address, CE#, or OE# Change
Min
0
0
ns
RESET# Pin Low to Read Mode*
Max
20
20
µs
tReady
* Not 100% tested.
26
AmMC0XXA
PRELIMINARY
AC CHARACTERISTICS
Write Operations (Erase/Program)
Parameter Symbols
Card Speed
JEDEC
Standard
-100
-150
Unit
tAVAV
tWC
Write Cycle Time
Min
100
150
ns
tWLWH
tWP
WE# pulse width
Min
45
50
ns
tELGL
tELWL
CE# setup time to WE# or OE# active
Min
0
0
ns
tAVGL
tAVWL
Address setup time to WE# or OE# active
Min
0
0
ns
Data setup time to WE# inactive
Min
45
50
ns
tWHDX
Data hold time from WE# inactive
Min
0
0
ns
tWHAX
Address hold time from WE# inactive
Min
0
0
ns
tWHEH
CE# hold time from WE# inactive
Min
0
0
ns
RESET# Pulse Width
Min
500
500
ns
Program/Erase Valid to RY/BY# Delay
Min
40
50
ns
Typ
8
8
µs
Max
300
300
µs
Typ
1
1
s
Max
1.5
1.5
s
tDVWH
tDS
tRP
tBUSY
Parameter Description
tWHWH1
Programming Operation
tWHWH2
Sector Erase Operation
AmMC0XXA
27
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010
SWITCHING WAVEFORMS
tAVAV
tAVQV
tAXQX
tAVGL
A0–A25
tELGL
tELQV
tEHQX
tELQNZ
CEL#/CEH#
tGLQV
tGHQZ
tGLQNZ
tGHQX
OE#
Valid Data
D0–D15
20975D-8
Figure 7. AC Waveforms for Read Operations
28
AmMC0XXA
PRELIMINARY
SWITCHING WAVEFORMS
tAVAV
tAVWL
tWHAX
A0–A25
tELWL
tWHEH
CEL#/CEH#
tWLWH
tDVWH
tWHDX
WE#
Valid Data
D0–D15
20975D-9
Figure 8.
CE#
AC Waveforms for Write Operations
tCH
tDF
tOE
OE#
tOEH
tCE
WE#
*
D7#
D7
tOH
D7=
Valid Data
High Z
tWHWH1 or tWHWH2
D0–D6=Invalid
D0–D6
D0–D7
Valid Data
*D7=Valid Data (The device has completed the Embedded operation).
Figure 9.
20975D-10
AC Waveforms for Data# Polling During Embedded Algorithm Operations
AmMC0XXA
29
PRELIMINARY
SWITCHING WAVEFORMS
CE#
The rising edge of the last WE# signal
WE#
Entire programming
or erase operations
RY/BY#
tBUSY
Figure 10.
20975D-11
RY/BY# Timing Diagram During Program/Erase Operations
RESET#
tRP
tReady
20975D-12
Figure 11.
30
RESET# Timing Diagram
AmMC0XXA
PRELIMINARY
AC CHARACTERISTICS—ALTERNATE CE# CONTROLLED WRITES
Write/Erase/Program Operations
Parameter Symbols
JEDEC
Standard
Card Speed
Parameter Description
-100
-150
Unit
tAVAV
tWC
Write Cycle Time
Min
100
150
ns
tAVEL
tAS
Address Setup Time
Min
10
10
ns
tELAX
tAH
Address Hold Time
Min
45
50
ns
tDVEH
tDS
Data Setup Time
Min
45
50
ns
tEHDX
tDH
Data Hold Time
Min
20
20
ns
tGLDV
tOEH
Output Enable Hold Time for Embedded Algorithm
Min
10
10
ns
Read Recovery Time before Write
Min
0
0
µs
tGHEL
tWLEL
tWS
WE# Setup Time before CE#
Min
0
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
0
ns
tELEH
tCP
CE# Pulse Width
Min
45
50
ns
tEHEL
tCPH
CE# Pulse Width HIGH (Note 2)
Min
20
20
ns
Typ
8
8
µs
Max
300
300
µs
tEHEH3
Embedded Programming Operation (Notes 2)
Embedded Erase Operation for each 64K byte
Memory Sector (Notes 1)
Typ
1
1
s
tEHEH4
Max
1.5
1.5
s
tVCS
VCC Setup Time to Write Enable LOW
Min
50
50
µs
Notes:
1. Rise/fall time ≤10 ns.
2. Card Enable Controlled Programming:
Flash Programming is controlled by the valid combination of the Card Enable (CE1#, CE2#) and Write Enable (WE#) signals.
For systems that use the Card Enable signal(s) to define the write pulse width, all setup, hold, and inactive write enable timing
should be measured relative to the Card Enable signal(s).
AmMC0XXA
31
PRELIMINARY
tWC
Addresses
Data# Polling
tAS
XXXXh
PA
PA
tAH
WE#
tWH
OE#
tGHEL
tCP
CE#
tWS
tEHEH3_or_4
tCPH
tDS
tDH
A0h
Data
PD
DQ7#
DOUT
VCC
tVCS
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the complement of the data written to the device.
4. DOUT is the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. Waveforms are for the x16 mode.
20975D-13
Figure 12.
32
Alternate CE# Controlled Write Operation Timings
AmMC0XXA
PRELIMINARY
AIS MEMORY MAP
The AIS (Attribute Information Structure) is an area of
memory used for storing information about the configuration of the Miniature Card. The AIS is recommended
to be stored in the first sector of the first device of the
Flash array. As this area is not explicitly protected, the
AIS information must be reloaded onto the card in the
event that the information is erased.
The AIS has five unique information areas:
1. Identification Data: This data includes Manufacturer
information (Manufacturer and card name).
2. Compatibility Data: This data specifies basic information about the card (memory size, access time,
memory type, power, etc.)
The AIS supports up to four different memory technologies on a card. Some of the information areas are
repeated in the memory map in order to specify different technologies (see Table 16). The Technology
Count field in the Identification Data section defines the
number of different technologies on a card. The first
memory technology is defined in the AIS memory map
from address 40h through 7Fh. The second memory
technology is defined from 80h through BFh. The third
memory technology is defined from C0h to DFh. The
fourth memory technology is defined from E0h to FFh.
The AIS is stored as bytes within the 16-bit Miniature
Card data word. The even byte D0–D7 stores the AIS
data, and the odd byte D8–D15 is reserved by the card
manufacturer for manufacturing information.
3. Burst Data (not applicable)
4. DRAM Data (not applicable)
5. Reserved Data: This data area is reserved for future
use.
Table 16.
Card Address
Miniature Card AIS Memory Assignments
Section
00h–0Fh
PC Card Compatibility Area*
10h–1Fh
Identification Data Identifies Card Type
20h–2Fh
Identification Data Identifies Card Type
30h–3Fh
Identification Data Identifies Card Type
40h–4Fh
Compatibility Data (Area 1)
50h–5Fh
Burst Data (not applicable)
60h–6Fh
DRAM Data (not applicable)
70h–7Fh
Reserved for future use
80h–8Fh
Compatibility Data (not applicable)
90h–9Fh
Burst Data (not applicable)
A0h–AFh
DRAM Data (not applicable)
B0h–BFh
Reserved for future use
C0h–CFh
Compatibility Data (not applicable)
D0h–DFh
Reserved for future use
E0h–EFh
Compatibility Data (not applicable)
F0h–FFh
Reserved for future use
Description
Reserved for PC Card Tuples
Memory Technology #1
(Memory Technology #2)
(Memory Technology #3)
(Memory Technology #4)
* For more information on PC Card Compatibility refer to Table 17 or the Miniature Card PC Compatibility Guide.
Note: “Not applicable” indicates the address space does not apply to AMD Flash Miniature Cards, but is defined by MCIF.
AmMC0XXA
33
PRELIMINARY
Table 17.
34
PC Card Compatibility Memory Assignments
Address
Values
Description
00h
01h
TPL_CODE CISTPL_DEVICE
01h
03h
TPL_LINK
02h
53
Device ID
03h
2MB = 7C, 4MB = FC; 8MB = 1E
04h
FF
End of CISTPL_DEVICE
05h
00h
CISTPL_NULL
06h
00h
CISTPL_NULL
07h
00h
CISTPL_NULL
08h
00h
CISTPL_NULL
09h
00h
CISTPL_NULL
0Ah
00h
CISTPL_NULL
0Bh
00h
CISTPL_NULL
0Ch
00h
CISTPL_NULL
0Dh
00h
CISTPL_NULL
0Eh
80h
TPL_CODE CISTPL_MINI
0Fh
F0h
TPL_LINK
AmMC0XXA
Device Size
PRELIMINARY
Identification Data
Compatibility Data
The Identification Data provides basic identification
information about the card. This data section is
required on all cards. Table 18 shows the Identification
Data for AMD’s 5 volt-only Miniature cards.
The compatibility data provides basic compatibility
across all cards. This data section is required on all
cards. The addresses in parentheses are specified for
cards with more than one memory technology on the
card. Table 19 shows the compatibility data for AMD
5-volt only Miniature Cards.
Table 18.
AMD Identification Data
Card Address
Value
Description
10h
99h
Miniature Card Identifier: Fixed value for a host to identify an inserted
Miniature Card
11h
11h
Level of Compliance: Defines the level of AIS supported. The
Miniature Cards described in this document are rev 1.1 compliant.
AIS Checksum: The modulo-256 sum of all even bytes from 10h–FFh.
A valid checksum sums to 00h (2’s complement).
12h
01h or FDh or F9h
2 Mbyte card: 99h + 01h = 00h
4 Mbyte card: 03h + FDh = 00h
8 Mbyte card: 07h + F9h = 00h
13h
41h
Manufacturer Name: 13h–26h. String of ASCII characters at
addresses 13h to 26h to identify the manufacturer of the Miniature
Card.
ASCII character “A”
14h
4Dh
ASCII character “M”
15h
44h
ASCII character “D”
16h
20h
ASCII character - SPACE
17h
49h
ASCII character - “I”
18h
4Eh
ASCII character - “N”
19h
43h
ASCII character - “C”
1Ah
00h
ASCII character - NULL
1Bh
00h
ASCII character - NULL
1Ch–26h
00h
Unused space in manufacturer name field
27h
35h
Card Name: (addresses 27h–3Ah). String of ASCII characters to
identify the card name.
ASCII character “5”
28h
56h
ASCII character “V”
29h
4Dh
ASCII character “M”
2Ah
43h
ASCII character “C”
2Bh
20h
ASCII character - SPACE
2Ch
53h
ASCII character “S”
2Dh
65h
ASCII character “e”
2Eh
72h
ASCII character “r”
2Fh
69h
ASCII character “i”
30h
65h
ASCII character “e”
31h
73h
ASCII character “s”
AmMC0XXA
35
PRELIMINARY
Table 18.
AMD Identification Data (Continued)
Card Address
Value
32h
00h
ASCII character - NULL
33h–3Ah
00h
Unused space in card name field
3Bh
01h
Technology Count: Defines the number of different memory
technologies on the Miniature Card.
Technology count set to 1
3Ch–3Fh
00h
Reserved space set to 00h; for future use
Table 19.
Description
AMD Compatibility Data
Card Address
Value
Description
40h
00h
Defines the type of memory technology; Flash = 000 binary
41h
01h
Device JEDEC Manufacturer ID
42h
D5h or 3Dh
43h
01h or 03h or 07h
44h
00h
N/A
45h
00h
N/A
46h
0Ah
5.0 Volt Access Time: 100 ns
47h
00h
N/A
48h
00h
N/A
49h
8Ch
Typical read/write current at 5.0 Volts (word mode): 80mA read, 120 mA
write
4Ah
0Ah
Typical standby current: 1 mA
4Bh–4Fh, 8Ch–8Fh,
CCh–CFh, ECh–EFh
00h
Reserved for future use
80h–8Bh, C0–CBh,
E0h–EBh
00h
These addresses are designated for other memory technologies, which
are not used in AMD Flash Miniature Cards.
100h
18h
TPL_CODE CISTPL_JEDEC_C
101h
02h
TPL_LINK
102h
01h
Manufacturer ID
Device JEDEC Component ID: Am29F080B = D5h, Am29F017B = 3Dh
Memory array size: 01 = 2 Mbyte, 03 = 4 Mbyte, 07 = 8 Mbyte
Device ID
2Mbyte card: D5
103h
D5 = 2M; 3D = 4M,8M 4Mbyte card: 3D
8Mbyte card: 3D
104h
1Eh
TPL_CODE CISTPL_DEVICEGEO
105h
06h
TPL_LINK
106h
02h
DGTPL_BUS: Bus Width
107h
01h
DGTPL_EBS:11h = 64K Byte Erase Block size
108h
01h
DGTPL_RBS: Read Byte Size
109h
01h
DGTPL_WBS: Write Byte Size
10Ah
01h
DGTPL_PART: Number of partition
10Bh
01h
FL DEVICE INTERLEAVE: No interleave.
Note: All reserved bytes must be set to 00h. All reserved fields (bits) within bytes must be set to 0 (binary). All unused fields must
be set to 00h.
36
AmMC0XXA
PRELIMINARY
PHYSICAL DIMENSIONS
Top View
33.00 mm
1.299 in.
.118 in.
3.212 mm
.118 in.
3.00 mm
.217 in.
5.50 mm
.118 in.
3.00 mm
center line
.244 in.
6.21 mm
.161 in.
.150 in. 4.09 mm
3.81 mm
38.00 mm
1.496 in.
.217 in.
5.50 mm
.118 in.
3.00 mm
AmMC0XXA
37
PRELIMINARY
PHYSICAL DIMENSIONS
Bottom View
0.600
0.245
Write Protect Switch Location
Right Side View
0.245
Write Protect Switch Location
38
AmMC0XXA
PRELIMINARY
REVISION SUMMARY FOR AMMC0XXA
Global
command, separated Read and Reset commands, moved
RA, RW, RD, PA, PW, PD, X, SA definitions to legend. Moved
Erase Suspend and Erase Resume definitions from table to
notes.
Changed all Am29F016 references to Am29F017B.
Added -100 (100 ns) speed option and specifications.
Distinctive Characteristics
Revised low power consumption specifications. Added industrial temperature range bullet. Deleted “Small Form Factor”
bullets. Revised text to indicate that the Miniature Card specification will be defined by PCMCIA.
Table 12, Memory Sector Addresses for 4 and 8
Mbyte Cards
Added Note 3 to include 8 Mbyte cards.
Embedded Erase Algorithm
Removed last paragraph.
General Description
Deleted references to the elastomeric connector.
Absolute Maximum Ratings
Table 1, Miniature Card Definitions
Revised storage and ambient temperature ratings.
Deleted references to the elastomeric connector.
Operating Ranges
Ordering Information
Added industrial temperature range.
Added industrial temperature range. Added Valid Combinations table. Deleted NP option from part number. Added WP
as part of required base part number.
Figure 2, Host/Card Address Connections
Clarified drawing by designating host bus and card bus.
Added A21 address pin. Redesignated NC connections.
Miniature Card Pad Assignments
BUSY#: Revised to indicate that the Miniature Card cannot
accept most operations when BUSY# is low. CD#: Deleted
last sentence.
DC Characteristics
Revised ICC specifications. Added frequency specification to
Note 2.
AC Characteristics, Write (Erase/Program)
Operations
Deleted t ELQV, tAVQV, t GLQV, t ELQX , t EHOZ, t GLOX , tGHQZ ,
tAXQX, tWHGL, tGLQNZ.
Table 19, AMD Compatibility Data
Sector Group Protection
Added two tuples of data to list, covering addresses 100h–
10Bh. Changed address 46h data to 0Ah, corresponding to
an access time of 100 ns.
Added section.
Revision D+1
Tables 5–9, Command Definitions
Sector Erase Suspend
Revised for easier reference: removed “H” designators from
table (now indicated in notes), removed 4-cycle Reset/Read
Removed the statement requiring the address of a sector not
being erased to obtain valid D6 status.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
AmMC0XXA
39