FUJITSU MBM29LV016B

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20855-4E
FLASH MEMORY
CMOS
16M (2M × 8) BIT
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ FEATURES
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded programTM Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector protect command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
• In accordance with CFI (Common Flash Memory Interface)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ PACKAGE
40-pin plastic TSOP (I)
40-pin plastic TSOP (I)
Marking Side
Marking Side
(FPT-40P-M06)
2
(FPT-40P-M07)
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ GENERAL DESCRIPTION
The MBM29LV016T/B is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each. The
MBM29LV016T/B is offered in a 40-pin TSOP packages. The device is designed to be programmed in-system
with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations.
The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV016T/B offers access times of 80 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29LV016T/B is pin and command set compatible with JEDEC standard E2PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV016T/B is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV016T/B is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
comleted, the device internally resets to the read mode.
The MBM29LV016T/B also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV016T/B memory electrically erases all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte at a time using
the EPROM programming mechanism of hot electron injection.
3
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors.
• Individual-sector, multiple-sector, or bulk-erase capability.
• Individual or multiple-sector protection is user definable.
Sector
Sector Size
(× 8) Address Range
SA0
64 Kbytes
00000H to 0FFFFH
SA1
64 Kbytes
10000H to 1FFFFH
SA2
64 Kbytes
20000H to 2FFFFH
SA3
64 Kbytes
30000H to 3FFFFH
SA4
64 Kbytes
40000H to 4FFFFH
SA5
64 Kbytes
50000H to 5FFFFH
SA6
64 Kbytes
60000H to 6FFFFH
SA7
64 Kbytes
70000H to 7FFFFH
SA8
64 Kbytes
80000H to 8FFFFH
SA9
64 Kbytes
90000H to 9FFFFH
SA10
64 Kbytes
A0000H to AFFFFH
SA11
64 Kbytes
B0000H to BFFFFH
SA12
64 Kbytes
C0000H to CFFFFH
SA13
64 Kbytes
D0000H to DFFFFH
SA14
64 Kbytes
E0000H to EFFFFH
SA15
64 Kbytes
F0000H to FFFFFH
SA16
64 Kbytes
100000H to 10FFFFH
SA17
64 Kbytes
110000H to 11FFFFH
SA18
64 Kbytes
120000H to 12FFFFH
SA19
64 Kbytes
130000H to 13FFFFH
SA20
64 Kbytes
140000H to 14FFFFH
SA21
64 Kbytes
150000H to 15FFFFH
SA22
64 Kbytes
160000H to 16FFFFH
SA23
64 Kbytes
170000H to 17FFFFH
SA24
64 Kbytes
180000H to 18FFFFH
SA25
64 Kbytes
190000H to 19FFFFH
SA26
64 Kbytes
1A0000H to 1AFFFFH
SA27
64 Kbytes
1B0000H to 1BFFFFH
SA28
64 Kbytes
1C0000H to 1CFFFFH
SA29
64 Kbytes
1D0000H to 1DFFFFH
SA30
64 Kbytes
1E0000H to 1EFFFFH
SA31
32 Kbytes
1F0000H to 1F7FFFH
SA32
8 Kbytes
1F8000H to 1F9FFFH
SA33
8 Kbytes
1FA000H to 1FBFFFH
SA34
16 Kbytes
1FC000H to 1FFFFFH
MBM29LV016T Top Boot Sector Architecture
4
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Sector
Sector Size
(× 8) Address Range
SA0
16 Kbytes
00000H to 03FFFH
SA1
8 Kbytes
04000H to 05FFFH
SA2
8 Kbytes
06000H to 07FFFH
SA3
32 Kbytes
08000H to 0FFFFH
SA4
64 Kbytes
10000H to 1FFFFH
SA5
64 Kbytes
20000H to 2FFFFH
SA6
64 Kbytes
30000H to 3FFFFH
SA7
64 Kbytes
40000H to 4FFFFH
SA8
64 Kbytes
50000H to 5FFFFH
SA9
64 Kbytes
60000H to 6FFFFH
SA10
64 Kbytes
70000H to 7FFFFH
SA11
64 Kbytes
80000H to 8FFFFH
SA12
64 Kbytes
90000H to 9FFFFH
SA13
64 Kbytes
A0000H to AFFFFH
SA14
64 Kbytes
B0000H to BFFFFH
SA15
64 Kbytes
C0000H to CFFFFH
SA16
64 Kbytes
D0000H to DFFFFH
SA17
64 Kbytes
E0000H to EFFFFH
SA18
64 Kbytes
F0000H to FFFFFH
SA19
64 Kbytes
100000H to 10FFFFH
SA20
64 Kbytes
110000H to 11FFFFH
SA21
64 Kbytes
120000H to 12FFFFH
SA22
64 Kbytes
130000H to 13FFFFH
SA23
64 Kbytes
140000H to 14FFFFH
SA24
64 Kbytes
150000H to 15FFFFH
SA25
64 Kbytes
160000H to 16FFFFH
SA26
64 Kbytes
170000H to 17FFFFH
SA27
64 Kbytes
180000H to 18FFFFH
SA28
64 Kbytes
190000H to 19FFFFH
SA29
64 Kbytes
1A0000H to 1AFFFFH
SA30
64 Kbytes
1B0000H to 1BFFFFH
SA31
64 Kbytes
1C0000H to 1CFFFFH
SA32
64 Kbytes
1D0000H to 1DFFFFH
SA33
64 Kbytes
1E0000H to 1EFFFFH
SA34
64 Kbytes
1F0000H to 1FFFFFH
MBM29LV016B Bottom Boot Sector Architecture
5
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ PRODUCT LINE UP
Part No.
MBM29LV016T/MBM29LV016B
+0.3 V
–0.3 V
-80
—
—
+0.6 V
—
-90
-12
Max. Address Access Time (ns)
80
90
120
Max. CE Access Time (ns)
80
90
120
Max. OE Access Time (ns)
30
35
50
VCC = 3.0 V
Ordering Part No.
VCC = 3.0 V
–0.3 V
■ BLOCK DIAGRAM
RY/BY
Buffer
DQ0 to DQ7
RY/BY
VCC
VSS
WE
RESET
Input/Output
Buffers
Erase Voltage
Generator
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
OE
STB
Low VCC Detector
A0 to A20
6
Timer for
Program/Erase
Address
Latch
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ CONNECTION DIAGRAMS
TSOP (I)
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
N.C.
RY/BY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(Marking Side)
MBM29LV016T/MBM29LV016B
Standard Pinout
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
N.C.
DQ3
DQ2
DQ1
DQ0
OE
VSS
CE
A0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A0
CE
VSS
OE
DQ0
DQ1
DQ2
DQ3
N.C.
VCC
VCC
DQ4
DQ5
DQ6
DQ7
A10
A19
A20
VSS
A17
FPT-40P-M06
A1
A2
A3
A4
A5
A6
A7
A18
RY/BY
N.C.
RESET
WE
A8
A9
A11
A12
A13
A14
A15
A16
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
MBM29LV016T/MBM29LV016B
Reverse Pinout
FPT-40P-M07
7
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ LOGIC SYMBOL
Table 1 MBM29LV016T/B Pin Configuration
Pin
Function
Address Inputs
A0 to A20
21
Data Inputs/Outputs
DQ0 to DQ7
A0 to A20
8
DQ0 to DQ7
CE
OE
CE
Chip Enable
OE
Output Enable
WE
Write Enable
WE
RESET
RY/BY
Table 2
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/
Temporary Sector Unprotection
N.C.
Pin Not Connected Internally
VSS
Device Ground
VCC
Device Power Supply
MBM29LV016T/B User Bus Operation
Operation
CE
OE
WE
A0
A1
A6
A9
A10
Auto-Select Manufacture Code (1)
L
L
H
L
L
L
VID
L
Code
H
Auto-Select Device Code (1)
L
L
H
H
L
L
VID
L
Code
H
Read (3)
L
L
H
A0
A1
A6
A9
A10
DOUT
H
Standby
H
X
X
X
X
X
X
X
HIGH-Z
H
Output Disable
L
H
H
X
X
X
X
X
HIGH-Z
H
Write (Program/Erase)
L
H
L
A0
A1
A6
A9
A10
DIN
H
Enable Sector Protection (2), (4)
L
VID
L
H
L
VID
X
X
H
Verify Sector Protection (2), (4)
L
L
H
L
H
L
VID
L
Code
H
Temporary Sector Unprotection (5)
X
X
X
X
X
X
X
X
X
VID
Reset (Hardware)/Standby
X
X
X
X
X
X
X
X
HIGH-Z
L
Legend: L = VIL, H = VIH, X = VIL or VIH.
DQ0 to DQ7 RESET
= pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 6.
2. Refer to the section on Sector Protection.
3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. VCC = 3.3 V ±10%
5. It is also used for the extended sector protection.
8
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29LV016
T
-80
PTN
PACKAGE TYPE
PTN = 40-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PTR = 40-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
SPEED OPTION
See Product Selector Guide
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29LV016
16 Mega-bit (2M × 8-Bit) CMOS Flash Memory
3.0 V-only Read, Write, and Erase
9
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29LV016T/B have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC - tCE time.) See Figure 5.1 for timing specifications.
Standby Mode
There are two ways to implement the standby mode on the MBM29LV016T/B devices, one using both the CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC
Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from
either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA max. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV016T/B data.
This mode can be used effectively with an application requested low power consumption such as handy terminals.
To activate this mode, MBM29LV016T/B automatically switch itself to low power mode when MBM29LV016T/B
addresses remain stably during access time of 150 ns. It is not necessary to control CE, WE, and OE on the
mode. Under the mode, the current consumed is typically 1 µA (CMOS level).
Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, A6, and A10. (See Table 3.1.)
10
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV016T/B are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 6. (Refer to Autoselect Command section.)
Byte 0 (A0 = VIL) represents the manufacture’s code (Fujitsu = 04H) and A0 = VIH represents the device identifier
code (MBM29LV016T = C7H, MBM29LV016B = 4CH). All identifiers for manufactures and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect,
A1 must be VIL. (See Tables 3.1 and 3.2.)
The device code is C7H (for top boot block) or 4CH (for bottom boot block).
In order to determine which sectors are write protected, A1 must be at VIH while running through the sector
addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 = 1).
Table 3.1 MBM29LV016T/B Sector Protection Verify Autoselect Code
A13 to A20
A10
A6
A1
A0
Code (HEX)
X
VIL
VIL
VIL
VIL
04H
MBM29LV016T
X
VIL
VIL
VIL
VIH
C7H
MBM29LV016B
X
VIL
VIL
VIL
VIH
4CH
Sector
Addresses
VIL
VIL
VIH
VIL
01H*1
Type
Manufacture’s Code
Device Code
Sector Protection
*1: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
Table 3.2 Expanded Autoselect Code Table
Type
Code
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
04H
0
0
0
0
0
1
0
0
MBM29LV016T
C7H
1
1
0
0
0
1
1
1
MBM29LV016B
4CH
0
1
0
0
1
1
0
0
01H
0
0
0
0
0
0
0
1
Manufacture’s Code
Device Code
Sector Protection
11
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Table 4
12
Sector Address Tables (MBM29LV016T)
Sector
Address
A20
A19
A18
A17
A16
A15
A14
A13
(× 8) Address Range
SA0
0
0
0
0
0
X
X
X
00000H to 0FFFFH
SA1
0
0
0
0
1
X
X
X
10000H to 1FFFFH
SA2
0
0
0
1
0
X
X
X
20000H to 2FFFFH
SA3
0
0
0
1
1
X
X
X
30000H to 3FFFFH
SA4
0
0
1
0
0
X
X
X
40000H to 4FFFFH
SA5
0
0
1
0
1
X
X
X
50000H to 5FFFFH
SA6
0
0
1
1
0
X
X
X
60000H to 6FFFFH
SA7
0
0
1
1
1
X
X
X
70000H to 7FFFFH
SA8
0
1
0
0
0
X
X
X
80000H to 8FFFFH
SA9
0
1
0
0
1
X
X
X
90000H to 9FFFFH
SA10
0
1
0
1
0
X
X
X
A0000H to AFFFFH
SA11
0
1
0
1
1
X
X
X
B0000H to BFFFFH
SA12
0
1
1
0
0
X
X
X
C0000H to CFFFFH
SA13
0
1
1
0
1
X
X
X
D0000H to DFFFFH
SA14
0
1
1
1
0
X
X
X
E0000H to EFFFFH
SA15
0
1
1
1
1
X
X
X
F0000H to FFFFFH
SA16
1
0
0
0
0
X
X
X
100000H to 10FFFFH
SA17
1
0
0
0
1
X
X
X
110000H to 11FFFFH
SA18
1
0
0
1
0
X
X
X
120000H to 12FFFFH
SA19
1
0
0
1
1
X
X
X
130000H to 13FFFFH
SA20
1
0
1
0
0
X
X
X
140000H to 14FFFFH
SA21
1
0
1
0
1
X
X
X
150000H to 15FFFFH
SA22
1
0
1
1
0
X
X
X
160000H to 16FFFFH
SA23
1
0
1
1
1
X
X
X
170000H to 17FFFFH
SA24
1
1
0
0
0
X
X
X
180000H to 18FFFFH
SA25
1
1
0
0
1
X
X
X
190000H to 19FFFFH
SA26
1
1
0
1
0
X
X
X
1A0000H to 1AFFFFH
SA27
1
1
0
1
1
X
X
X
1B0000H to 1BFFFFH
SA28
1
1
1
0
0
X
X
X
1C0000H to 1CFFFFH
SA29
1
1
1
0
1
X
X
X
1D0000H to 1DFFFFH
SA30
1
1
1
1
0
X
X
X
1E0000H to 1EFFFFH
SA31
1
1
1
1
1
0
X
X
1F0000H to 1F7FFFH
SA32
1
1
1
1
1
1
0
0
1F8000H to 1F9FFFH
SA33
1
1
1
1
1
1
0
1
1FA000H to 1FBFFFH
SA34
1
1
1
1
1
1
1
X
1FC000H to 1FFFFFH
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Table 5
Sector Address Tables (MBM29LV016B)
Sector
Address
A20
A19
A18
A17
A16
A15
A14
A13
(× 8) Address Range
SA0
0
0
0
0
0
0
0
X
00000H to 03FFFH
SA1
0
0
0
0
0
0
1
0
04000H to 05FFFH
SA2
0
0
0
0
0
0
1
1
06000H to 07FFFH
SA3
0
0
0
0
0
1
0
X
08000H to 0FFFFH
SA4
0
0
0
0
1
X
X
X
10000H to 1FFFFH
SA5
0
0
0
1
0
X
X
X
20000H to 2FFFFH
SA6
0
0
0
1
1
X
X
X
30000H to 3FFFFH
SA7
0
0
1
0
0
X
X
X
40000H to 4FFFFH
SA8
0
0
1
0
1
X
X
X
50000H to 5FFFFH
SA9
0
0
1
1
0
X
X
X
60000H to 6FFFFH
SA10
0
0
1
1
1
X
X
X
70000H to 7FFFFH
SA11
0
1
0
0
0
X
X
X
80000H to 8FFFFH
SA12
0
1
0
0
1
X
X
X
90000H to 9FFFFH
SA13
0
1
0
1
0
X
X
X
A0000H to AFFFFH
SA14
0
1
0
1
1
X
X
X
B0000H to BFFFFH
SA15
0
1
1
0
0
X
X
X
C0000H to CFFFFH
SA16
0
1
1
0
1
X
X
X
D0000H to DFFFFH
SA17
0
1
1
1
0
X
X
X
E0000H to EFFFFH
SA18
0
1
1
1
1
X
X
X
F0000H to FFFFFH
SA19
1
0
0
0
0
X
X
X
100000H to 1FFFFFH
SA20
1
0
0
0
1
X
X
X
110000H to 11FFFFH
SA21
1
0
0
1
0
X
X
X
120000H to 12FFFFH
SA22
1
0
0
1
1
X
X
X
130000H to 13FFFFH
SA23
1
0
1
0
0
X
X
X
140000H to 14FFFFH
SA24
1
0
1
0
1
X
X
X
150000H to 15FFFFH
SA25
1
0
1
1
0
X
X
X
160000H to 16FFFFH
SA26
1
0
1
1
1
X
X
X
170000H to 17FFFFH
SA27
1
1
0
0
0
X
X
X
180000H to 18FFFFH
SA28
1
1
0
0
1
X
X
X
190000H to 19FFFFH
SA29
1
1
0
1
0
X
X
X
1A0000H to 1AFFFFH
SA30
1
1
0
1
1
X
X
X
1B0000H to 1BFFFFH
SA31
1
1
1
0
0
X
X
X
1C0000H to 1CFFFFH
SA32
1
1
1
0
1
X
X
X
1D0000H to 1DFFFFH
SA33
1
1
1
1
0
X
X
X
1E0000H to 1EFFFFH
SA34
1
1
1
1
1
X
X
X
1F0000H to 1FFFFFH
13
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29LV016T/B feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL, A0 = A6 = VIL, and A1 = VIH. The sector addresses (A20, A19, A18, A17, A16, A15, A14, and A13)
should be set to the sector to be protected. Tables 4 and 5 define the sector address for each of the thirty five
(35) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and
is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse.
See figures 13 and 21 for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A20, A19, A18, A17, A16, A15, A14, and A13)
while (A10, A6, A1, A0) = (0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector.
Otherwise the devices will read 00H for unprotected sector. In this mode, the lower order addresses, except for
A0, A1, A6, and A10 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer
and device codes.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses (A20, A19, A18, A17, A16, A15,
A14, and A13) are the sector address will produce a logical “1” at DQ0 for a protected sector. See Tables 3.1 and
3.2 for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29LV016T/B devices in
order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12
V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses.
Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again.
See figure 15 and 22.
14
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Table 6
Command
Sequence
(Notes 1, 2, 3)
MBM29LV016T/B Standard Command Definitions
Second
Bus Fifth Bus
Bus
First Bus
Third Bus Fourth
Sixth Bus
Bus
Read/Write
Write Write Cycle
Write
Cycle
Write
Cycle
Write
Cycle
Write Cycle
Cycle
Cycles
Req'd Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
(Note 5)
1
XXXH F0H
Read/Reset
(Note 5)
3
555H AAH 2AAH 55H
Autoselect
3
Byte Program
(Notes 3, 4)
—
—
—
—
—
—
—
—
—
—
555H F0H
RA
RD
—
—
—
—
555H AAH 2AAH 55H
555H
90H
—
—
—
—
—
—
4
555H AAH 2AAH 55H
555H A0H
PA
PD
—
—
—
—
Chip Erase
6
555H AAH 2AAH 55H
555H
80H
555H AAH 2AAH 55H
555H
10H
Sector Erase
(Note 3)
6
555H AAH 2AAH 55H
555H
80H
555H AAH 2AAH 55H
SA
30H
Sector Erase
Suspend
1
XXXH B0H
—
—
—
—
—
—
—
—
—
—
Sector Erase
Resume
1
XXXH 30H
—
—
—
—
—
—
—
—
—
—
Notes: 1. Address bits A11 to A20 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA).
2. Bus operations are defined in Table 2.
3. RA =Address of the memory location to be read.
PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA =Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, and A13 will
uniquely select any sector.
4. RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA. Data is latched on the rising edge of WE.
5. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to
read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the sector Erase operation is in progress. Moreover, both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ0 to DQ7 bits are ignored.
15
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Table 7
MBM29LV016T/B Extended Command Definitions
Bus
Write
Cycles
Req'd
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Fast Mode Set
3
555H
AAH
2AAH
55H
555H
20H
—
—
Fast Program *1
2
XXXH
A0H
PA
PD
—
—
—
—
Fast Mode Reset
2
XXXH
90H
XXXH
F0H *3
—
—
—
—
CFI *2
2
55H
98H
—
—
—
—
—
—
Extended Sector
Protection
4
XXXH
60H
SPA
60H
SPA
40H
SPA
SD
Command
Sequence
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read Cycle
SPA: Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD: Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected
sector addresses.
*1: This command is valid while Fast Mode.
*2: Addresses from system set to A0 to A6. The other address are “DON’T CARES”.
*3: The data “00H” is also acceptable.
Read/Reset Command
The read or reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.(See Figures 5.1 and 5.2.)
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address X001H returns the device code (MBM29LV016T = C7H, MBM29LV016B = 4CH). (See Tables
3.1 and 3.2.)
All manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit.
Sector state (protection or unprotection) will be informed address X0002H.
Scanning the sector addresses (A20, A19, A18, A17, A16, A15, A14, A13) while (A10, A6, A1, A0) = (0, 0, 1, 0) will produce
a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin
mode on the protected sector. (See Table 2.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
16
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device (exceed timing limits), or result
in an apparent success according to the data polling algorithm but a read from read/reset mode will show that
the data is still “0”. Only erase operations can convert “0”s to “1”s.
Figure 17 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Chip Erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30H) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last Sector
Erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 µs, otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs
from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling
edge of the WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the
17
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector
Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous
command string. Resetting the devices once execution has begun will corrupt the data in that sector. In that
case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section
for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any
number of sectors (0 to 34).
Sector erase does not require the user to program the devices prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase
Time] × Number of Sector Erase.
Figure 18 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when
writing the Erase Suspend or Erase Resume commands.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of
the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the Toggle Bit (DQ6)
which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
18
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Extended Command
(1) Fast Mode
MBM29LV016T/B has Fast Mode function. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence by writing Fast mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in normal command. (Do
not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this
mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 23
Extended algorithm.) The VCC active current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program Setup command (A0H) and data write cycles (PA/PD). (Refer to the
Figure 23 Extended algorithm.)
(3) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation
handshake which allows specific vender-specified software algorithms to be used for entire families of device.
This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software
support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98H) into the command register. Following the command
write, a read cycle from specific address retrives device information. Refer to the CFI code table. To terminate
operation, it is necessary to write the Read/Reset command sequence into the register.
(4) Extended Sector Protection
In addition to normal sector protection, the MBM29LV016T/B has Extended Sector Protection as extended
function. This function enable to protect sector by forcing VID on RESET pin and write a command sequence.
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET
pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With
this condition, the operation is initated by writing the Setup command (60H) into the command register. Then,
the sector addresses pins (A20, A19, A18, A17, A16, A15, A14, and A13) and (A10, A6, A1, A0) = (0, 0, 1, 0) should be
set to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended sector
protect command (60H). A sector is typically protected in 150 µs. To verify programming of the protection cicuitry,
the sector addresses pins (A20, A19, A18, A17, A16, A15, A14, and A13) and (A10, A6, A1, A0) = (0, 0, 1, 0) should be
set and write a command (40H). Following the command write, a logical “1” at device output DQ0 will produce
for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended sector
protect command (60H) again. To terminate the opetation, it is necessary to set RESET pin to VIH.
19
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Write Operation Status
Table 8
Hardware Sequence Flags
Status
Embedded Program Algorithm
Embedded/Erase Algorithm
In
Progress
Erase Suspend Read
Erase Suspended Sector)
Erase
Erase Suspend Read
Suspend
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Embedded Program Algorithm
Exceeded
Time
Limits
Embedded/Erase Algorithm
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle
Data
Data
Data
Data
Data
DQ7
Toggle
(Note 1)
0
0
1
(Note 2)
DQ7
Toggle
1
0
1
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
3. DQ0 and DQ1 are reserve pins for future use.
4. DQ4 is Fujitsu internal use only.
20
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
DQ7
Data Polling
The MBM29LV016T/B devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the
device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 19.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV016T/B data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation
and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out. (See Table 8.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29LV016T/B also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the device will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 50 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See Figure 10 and Figure 20 for the Toggle Bit I timing specifications and diagrams.
21
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the device under
this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 2.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the
DQ5 bit will indicate a “1” Please note that this is not a device failure condition since the device was incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial Sector Erase command sequence the sector erase time-out will begin. DQ3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial Sector Erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional Sector Erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the
second status check, the command may not have been accepted.
See Table 8: Hardware Sequence Flags.
DQ2
Toggle Bit II
This Toggle Bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress.
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode. (DQ2 toggles
while DQ6 does not.) See also above Table 9 and Figure 16.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the devices are in the
erase mode, DQ2 toggles if this bit is read from the erasing sector.
22
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Table 9
Toggle Bit Status
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
Toggle
DQ7
Toggle (Note 1)
1 (Note 2)
Mode
Program
Erase-Suspend Program
Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the address being programmed while in the erase-suspend program mode will indicate logic
“1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
RY/BY
Ready/Busy Pin
The MBM29LV016T/B provide a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29LV016T/B are placed in an Erase Suspend
mode, the RY/BY output will be high, by means of connecting with a pull up resistor to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. See Figure 11 and 12 for a detailed timing diagram. The RY/BY pin is
pulled high in stadby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
RESET
Hardware Reset Pin
The MBM29LV016T/B devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode tREADY after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices requires an additional tRH before it will allow read access. When the RESET pin is low, the device will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
23
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Data Protection
The MBM29LV016T/B are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the Read mode. Subsequent writes will be ignored
until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when VCC is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
24
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Table 10
Description
Query-unique ASCII string
“QRY”
Primary OEM Command
Set
02h:AMD/FJ standard type
MBM29LV016T/B Common Flash Interface Code
A0 to A6
10H
11H
12H
13H
DQ0 to DQ7
Description
51H
52H
Erase Block Region 1
Information
59H
02H
14H
00H
15H
16H
17H
18H
19H
1AH
40H
00H
00H
00H
00H
00H
VCC Min. (write/erase)
D7 to D4 : volt
D3 to D0 : 100 m volt
1BH
27H
VCC Max. (write/erase)
D7 to D4 : volt
D3 to D0 : 100 m volt
1CH
36H
VPP Min. voltage
VPP Max. voltage
Typical time-out per single
byte/word write 2N µs
Typical time-out for Min. size
buffer write 2N µs
Typical time-out per
individual block erase 2N ms
Typical time-out for full chip
erase 2N ms
Max. time-out for byte/word
write 2N times typical
Max. time-out for buffer
write 2N times typical
Max. time-out per individual
block erase 2N times typical
Max. time-out for full chip
erase 2N times typical
1DH
1EH
00H
00H
1FH
04H
20H
00H
21H
0AH
22H
00H
23H
05H
24H
00H
25H
04H
26H
00H
Device size = 2N byte
27H
15H
Flash Device Interface
description
28H
29H
2AH
2BH
00H
00H
00H
00H
2CH
04H
Address for Primary
Extended Table
Alternate OEM Command
Set (00H = not applicable)
Address for Alternate OEM
Extended Table
Max. number of byte in
multi-byte write = 2N
Number of Erase Block
Regions within device
Erase Block Region 2
Information
Erase Block Region 3
Information
Erase Block Region 4
Information
Query-unique ASCII string
“PRI”
Major version number,
ASCII
Minor version number,
ASCII
Address Sensitive Unlock
0 = Required
1 = Not Required
Erase Suspend
0 = Not Supported
1 = To Read Only
2 = To Read & Write
Sector Protection
0 = Not Supported
X = Number of sectors in
per group
Sector Temporary
Unprotection
00 = Not Supported
01 = Supported
Reserve
A0 to A6
2DH
2EH
2FH
30H
DQ0 to DQ7
00H
00H
40H
00H
31H
01H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
40H
41H
42H
00H
20H
00H
00H
00H
80H
00H
1EH
00H
00H
01H
50H
52H
49H
43H
31H
44H
30H
45H
00H
46H
02H
47H
01H
48H
01H
49H
4AH
4BH
4CH
XXH
XXH
XXH
XXH
25
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. –55°C to +125°C
Ambient Temperature with Power Applied .................................................................. –40°C to +85°C
Voltage with respect to Ground All pins except A9, OE, and RESET (Note 1) ............ –0.5 V to +VCC +0.5 V
VCC (Note 1) ................................................................................................................ –0.5 V to +5.5 V
A9, OE, and RESET (Note 2) ...................................................................................... –0.5 V to +13.0 V
Notes: 1. Minimum DC voltage on input or l/O pins are –0.5 V. During voltage transitions, inputs may negative
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are VCC
+0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE, and RESET pins are –0.5 V. During voltage transitions, A9, OE,
and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A9, OE, and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of
up to 20 ns. Voltage difference between input voltage and supply voltage (VIN - VCC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Ambient Temperature (TA)
MBM29LV016T/B-80 .................................................................................–20°C to +70°C
MBM29LV016T/B-90/-12...........................................................................–40°C to +85°C
VCC Supply Voltages
MBM29LV016T/B-80 .................................................................................+3.0 V to +3.6 V
MBM29LV016T/B-90/-12...........................................................................+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is quaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when operated within
these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
26
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ MAXIMUM OVERSHOOT
20 ns
20 ns
+0.6 V
–0.5 V
–2.0 V
20 ns
Figure 1
Maximum Negative Overshoot Waveform
20 ns
VCC +2.0 V
VCC +0.5 V
+2.0 V
20 ns
20 ns
Figure 2
Maximum Positive Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE, and RESET.
Figure 3
Maximum Positive Overshoot Waveform 2
27
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
VIN = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
ILIT
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max.,
A9, OE, RESET = 12.5 V
—
35
µA
CE = VIL, OE = VIH, f = 10 MHz
—
30
mA
ICC1
VCC Active Current (Note 1)
CE = VIL, OE = VIH, f = 5 MHz
—
15
mA
ICC2
VCC Active Current (Note 2)
CE = VIL, OE = VIH
—
35
mA
ICC3
VCC Current (Standby)
VCC = VCC Max., CE = VCC ±0.3 V,
RESET = VCC ±0.3 V
—
5
µA
ICC4
VCC Current during Reset
(Standby, RESET)
VCC = VCC Max.,
RESET = VSS ±0.3 V
—
5
µA
ICC5
VCC = VCC Max.,
RESET = VCC ±0.3 V,
VCC Current
(Automatic Sleep Mode) (Note 3) CE = VSS ±0.3 V, VIN = VCC ±0.3 V
or VSS ±0.3 V
—
5
µA
VIL
Input Low Level
—
–0.5
0.6
V
VIH
Input High Level
—
2.0
VCC + 0.3
V
VID
Voltage for Autoselect,
Sector Protection and
Temporary Sector Unprotection
(A9, OE, RESET) (Note 4)
—
11.5
12.5
V
VOL
Output Low Voltage Level
IOL = 4.0 mA, VCC = VCC Min.
—
0.45
V
IOH = –2.0 mA, VCC = VCC Min.
2.4
—
V
VCC – 0.4
—
V
2.3
2.5
V
VOH1
Output High Voltage Level
VOH2
VLKO
Notes: 1.
2.
3.
4.
28
IOH = –100 µA
Low VCC Lock-Out Voltage
—
The lCC current listed includes both the DC operating current and the frequency dependent component.
lCC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
(VID - VCC) do not exceed 9 V.
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
Symbols
Description
JEDEC
Standard
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
tELQV
Test Setup
-80
(Note)
-90
(Note)
-12
(Note)
Unit
—
Min.
80
90
120
ns
Address to Output Delay
CE = VIL
OE = VIL
Max.
80
90
120
ns
tCE
Chip Enable to Output Delay
OE = VIL
Max.
80
90
120
ns
tGLQV
tOE
Output Enable to Output Delay
—
Max.
30
35
50
ns
tEHQZ
tDF
Chip Enable to Output HIGH-Z
—
Max.
25
30
30
ns
tGHQZ
tDF
Output Enable to Output HIGH-Z
—
Max.
25
30
30
ns
tAXQX
tOH
Output Hold Time From Address,
CE or OE, Whichever Occurs First
—
Min.
0
0
0
ns
—
tREADY
RESET Pin Low to Read Mode
—
Max.
20
20
20
µs
Note: Test Conditions: Output Load:
1 TTL gate and 30 pF (MBM29LV016T/B-80/-90)
1 TTL gate and 100 pF (MBM29LV016T/B-12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29LV016T/B-80/-90)
CL = 100 pF including jig capacitance (MBM29LV016T/B-12)
Figure 4
Test Conditions
29
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
• Write (Erase/Program) Operations
Parameter Symbols
MBM29LV016T/B
Description
JEDEC
Standard
tAVAV
tWC
Write Cycle Time
tAVWL
tAS
tWLAX
Unit
-80
-90
-12
Min.
80
90
120
ns
Address Setup Time
Min.
0
0
0
ns
tAH
Address Hold Time
Min.
45
45
50
ns
tDVWH
tDS
Data Setup Time
Min.
35
45
50
ns
tWHDX
tDH
Data Hold Time
Min.
0
0
0
ns
—
tOES
Output Enable Setup Time
Min.
0
0
0
ns
Min.
0
0
0
ns
tOEH
Output
Enable Hold
Time
Read
—
Toggle and Data Polling
Min.
10
10
10
ns
tGHWL
tGHWL
Read Recover Time Before Write
(OE High to WE Low)
Min.
0
0
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
(OE High to CE Low)
Min.
0
0
0
ns
tELWL
tCS
CE Setup Time
Min.
0
0
0
ns
tWLEL
tWS
WE Setup Time
Min.
0
0
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
0
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
0
0
ns
tWLWH
tWP
Write Pulse Width
Min.
35
45
50
ns
tELEH
tCP
CE Pulse Width
Min.
35
45
50
ns
tWHWL
tWPH
Write Pulse Width High
Min.
25
25
30
ns
tEHEL
tCPH
CE Pulse Width High
Min.
25
25
30
ns
tWHWH1
tWHWH1
Programming Operation
Typ.
8
8
8
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
Typ.
1
1
1
sec
—
tEOE
Delay Time from Embedded Output Enable
Max.
30
35
50
ns
—
tVCS
VCC Setup Time
Min.
50
50
50
µs
—
tVLHT
Voltage Transition Time (Note 2)
Min.
4
4
4
µs
—
tWPP
Write Pulse Width (Note 2)
Min.
100
100
100
µs
—
tOESP
OE Setup Time to WE Active (Note 2)
Min.
4
4
4
µs
—
tCSP
CE Setup Time to WE Active (Note 2)
Min.
4
4
4
µs
—
tRB
Recover Time From RY/BY
Min.
0
0
0
ns
—
tRH
RESET Hold Time Before Read
Min.
200
200
200
ns
(Continued)
30
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
(Continued)
Parameter Symbols
MBM29LV016T/B
Description
JEDEC
Standard
—
tBUSY
Program/Erase Valid to RY/BY Delay
—
tVIDR
—
tRP
Unit
-80
-90
-12
Max.
90
90
90
ns
Rise Time to VID (Note 2)
Min.
500
500
500
ns
RESET Pulse Width
Min.
500
500
500
ns
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Protection operation.
31
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ SWITCHING WAVEFORMS
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Change
from H to L
May
Change
from L to H
Will Be
Change
from L to H
“H” or “L”:
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
tRC
Addresses
Addresses Stable
tACC
CE
tOE
tDF
OE
tOEH
WE
tCE
Outputs
HIGH-Z
Figure 5.1
32
tOH
Output Valid
AC Waveforms for Read Operations
HIGH-Z
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
tRC
Addresses
Addresses Stable
tACC
tRH
RESET
tOH
HIGH-Z
Outputs
Figure 5.2
Output Valid
AC Waveforms for Hardware Reset/Read Operations
33
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
3rd Bus Cycle
Data Polling
555H
Addresses
PA
tWC
tAS
PA
tRC
tAH
CE
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
tDS
A0H
Data
Notes: 1.
2.
3.
4.
5.
PD
DQ7
DOUT
tOH
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
Figure 6
34
tDF
tDH
AC Waveforms for Alternate WE Controlled Program Operations
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
3rd Bus Cycle
Addresses
Data Polling
PA
555H
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
Data
Notes: 1.
2.
3.
4.
5.
A0H
tDH
PD
DQ7
DOUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
Figure 7
AC Waveforms for Alternate CE Controlled Program Operations
35
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Addresses
555H
tWC
555H
2AAH
tAS
555H
2AAH
SA*
tAH
CE
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAH
Data
30H for Sector Erase
55H
80H
AAH
55H
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.
Figure 8
36
AC Waveforms for Chip/Sector Erase Operations
10H
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
CE
tCH
tDF
tOE
OE
tOEH
WE
tCE
*
DQ7
DQ7 =
Valid Data
DQ7
Data
High-Z
tWHWH1 or 2
DQ0 to DQ6
Data
DQ0 to DQ6 = Output Flag
DQ0 to DQ6
High-Z
Valid Data
tEOE
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 9
AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
tDH
DQ6
Data
DQ6 = Toggle
*
DQ6 = Toggle
DQ6 =
Stop Toggling
DQ0 to DQ7
Data Valid
tOE
* : DQ6 stops toggling. (The device has completed the Embedded operation.)
Figure 10
AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
37
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
Figure 11
RY/BY Timing Diagram during Program/Erase Operations
WE
RESET
tRP
tRB
RY/BY
tREADY
Figure 12
38
RESET, RY/BY Timing Diagram
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
A20, A19, A18
A17, A16, A15
A14, A13
SAX
SAY
A0
A1
A6
12 V
3V
A9
tVLHT
12 V
3V
OE
tOESP
tVLHT
tWPP
tVLHT
tVLHT
WE
tCSP
CE
01H
Data
tOE
tVLHT
VCC
SAX : Sector Address for initial sector
SAY : Sector Address for next sector
Figure 13
AC Waveforms for Sector Protection Timing Diagram
39
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
VCC
tVCS
RESET
tVLHT
tVIDR
Add
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE
TIME-OUT
WE
Data
60H
60H
40H
01H
tOE
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 150 µs (min)
Figure 14
40
Extended Sector Protection Timing Diagram
60H
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
VCC
tVIDR
tVCS
tVLHT
VID
3V
3V
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection period
Figure 15
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Temporary Sector Unprotection Timing Diagram
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE
Note: DQ2 is read from the erase-suspended sector.
Figure 16
DQ2 vs. DQ6
41
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
EMBEDDED PROGRAM TM ALGORITHM
Start
Write Program Command
Sequence
(See Below)
Data Polling Device
No
Verify Byte
?
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
Figure 17
42
Embedded ProgramTM Algorithm
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
EMBEDDED PROGRAM TM ALGORITHM
Start
Write Erase Command
Sequece
(See Below)
Data Polling or Toggle Bit
from Device
No
Data = FFH
?
Yes
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
Sector Address/30H
Figure 18
Embedded EraseTM Algorithm
43
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Start
Read Byte
(DQ0 to DQ7)
Addr. = VA
DQ7 = Data?
Yes
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
= Any of the sector addresses
within the sector not being
protected during sector erase or
multiple sector erases
operation.
No
No
DQ5 = 1?
Yes
Read Byte
(DQ0 to DQ7)
Addr. = VA
DQ7 = Data?
*
Yes
No
Fail
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 19
44
Data Polling Algorithm
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Start
Read Byte
(DQ0 to DQ7)
Addr. = “H” or “L”
No
DQ6 = Toggle
?
Yes
No
DQ5 = 1?
Yes
Read Byte
(DQ0 to DQ7)
Addr. = “H” or “L”
DQ6 = Toggle
?*
No
Yes
Fail
Pass
* : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ5 changing to “1”.
Figure 20
Toggle Bit Algorithm
45
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Start
Setup Sector Addr.
(A20, A19, A18, A17,
A16, A15, A14, A13)
PLSCNT = 1
OE = VID, A9 = VID
A6 = CE = VIL, RESET = VIH
A0 = VIL, A1 = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector
( A1 = VIH, A0 = VIL,
Addr. = SA, A6 = VIL)*
No
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
Data = 01H?
Yes
Protect Another Sector?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Protection
Completed
Figure 21
46
Sector Protection Algorithm
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Start
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
(Note 2)
Notes: 1. All protected sectors are unprotected.
2. All previously protected sectors are protected once again.
Figure 22
Temporary Sector Unprotection Algorithm
47
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
FAST MODE ALGORITHM
Start
555H/AAH
Set Fast Mode
2AAH/55H
555H/20H
XXXH/A0H
Program Address/Program Data
Data Polling Device
Verify Byte?
No
In Fast Program
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
XXXH/90H
Reset Fast Mode
XXXH/F0H
Figure 23
48
Embedded ProgramTM Algorithm for Fast Mode
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXH/60H
PLSCNT = 1
To Sector Protection
Write 60H to Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
Wait to 150 µs
Increment PLSCNT
To Verify Sector Protection
Write 40H to Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
Setup Next Sector Address
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
No
PLSCNT = 25?
Yes
Data = 01H?
Yes
Remove VID from RESET
Write Reset Command
Protect Other Sector
?
No
Device Failed
Remove VID from RESET
Write Reset Command
Yes
Sector Protection
Completed
Figure 24
Extended Sector Protection Algorithm
49
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
10
sec
Excludes programming time
prior to erasure
8
300
µs
Excludes system-level
overhead
—
16.8
50
sec
Excludes system-level
overhead
100,000
—
—
cycles
Min.
Typ.
Max.
Sector Erase Time
—
1
Byte Programming Time
—
Chip Programming Time
Erase/Program Cycle
—
■ TSOP (I) PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
TBD
TBD
pF
COUT
Output Capacitance
VOUT = 0
TBD
TBD
pF
CIN2
Control Pin Capacitance
VIN = 0
TBD
TBD
pF
Note: Test conditions TA = 25°C, f = 1.0 MHz
50
Test Setup
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
■ PACKAGE DIMENSIONS
40-pin plastic TSOP(I)
(FPT-40P-M06)
LEAD No.
1
Details of "A" part
40
0.15(.006)
MAX
0.35(.014)
MAX
INDEX
"A"
0.15(.006)
20
0.25(.010)
21
0.15±0.05
(.006±.002)
20.00±0.20
(.787±.008)
18.40±0.20
(.724±.008)
0.50(.0197)
TYP
0.10(.004)
19.00±0.20
(.748±.008)
C
0.05(.002)MIN
(STAND OFF)
10.00±0.20
(.394±.008)
0.50±0.10
(.020±.004)
+0.10
+.004
1.10 –0.05 .043 –.002
(Mounting height)
9.50(.374)
REF.
0.20±0.10
0.10(.004)
(.008±.004)
M
Dimensions in mm (inches).
1994 FUJITSU LIMITED F40007S-1C-1
40-pin plastic TSOP(I)
(FPT-40P-M07)
LEAD No.
1
Details of "A" part
40
0.15(.006)
MAX
0.35(.014)
MAX
INDEX
"A"
0.15(.006)
20
19.00±0.20
(.748±.008)
0.15±0.05
(.006±.002)
0.25(.010)
21
0.10(.004)
18.40±0.20
(.724±.008)
0.50±0.10
(.020±.004)
0.20±0.10
(.008±.004)
0.10(.004)
9.50(.374)
REF.
M
0.05(.002)MIN
(STAND OFF)
0.50(.0197)
TYP
10.00±0.20
(.394±.008)
+0.10
+.004
1.10 –0.05 .043 –.002
(Mounting height)
20.00±0.20
(.787±.008)
C
1994 FUJITSU LIMITED F40008S-1C-1
Dimensions in mm (inches).
51
MBM29LV016T-80/-90/-12/MBM29LV016B-80/-90/-12
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9811
 FUJITSU LIMITED Printed in Japan
52
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inhereut chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.