MC10EP105, MC100EP105 3.3V / 5VECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAM* • 275 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • MCxxx EP105 with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V Open Input Default State AWLYYWW LQFP–32 FA SUFFIX CASE 873A • • Safety Clamp on Inputs xxx A WL YY WW 32 1 = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2002 September, 2002 – Rev. 8 1 Package Shipping MC10EP105FA LQFP–32 250 Units/Tray MC10EP105FAR2 LQFP–32 2000 Tape & Reel MC100EP105FA LQFP–32 250 Units/Tray MC100EP105FAR2 LQFP–32 2000 Tape & Reel Publication Order Number: MC10EP105/D MC10EP105, MC100EP105 D0b D1a D1a D1b D1b D2a D2a D2b 24 23 22 21 20 19 18 D0a 17 25 16 D2b D0a 26 15 D3a D1a D0a 27 14 D3a D1a D1b VEE 28 13 VCC Q0 29 12 D3b D2a D2a D2b D2b Q0 30 11 D3b VCC 31 10 VEE VCC 32 9 NC 1 2 3 4 5 6 7 8 Q0 D0b D0b MC10EP105 MC100EP105 Q0 D0a D0b Q1 Q1 D1b Q2 Q2 D3a Q3 D3a D3b Q3 D3b VCC Q1 Q1 Q2 Q2 Q3 Q3 VCC VEE Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32–Lead LQFP Pinout (Top View) Figure 2. Logic Diagram PIN DESCRIPTION PIN TRUTH TABLE FUNCTION Dna*, Dnb*, Dna*, Dnb* ECL Data Inputs Qn, Qn ECL Data Outputs VCC Positive Supply VEE Negative Supply NC No Connect Dna Dnb Dna L L H H L H L H H H L L Dnb Qn Qn H L H L L L L H H H H L * Pins will default LOW when left open. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model > 4 kV > 100 V > 2 kV Oxygen Index: 28 to 34 UL–94 V–0 @ 0.125 in Moisture Sensitivity (Note 1) Flammability Rating Level 2 Transistor Count 444 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC10EP105, MC100EP105 MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V –6 V VI PECL Mode In Input ut Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 –6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature Range –65 to +150 °C θJA Thermal Resistance (Junction–to–Ambient) 0 LFPM 500 LFPM 32 LQFP 32 LQFP 80 55 °C/W °C/W θJC Thermal Resistance (Junction–to–Case) std bd 32 LQFP 12 to 17 °C/W Tsol Wave Solder < 2 to 3 sec @ 248°C 265 °C VI ≤ VCC VI ≥ VEE 2. Maximum Ratings are those values beyond which device damage may occur. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 58 75 45 59 75 45 60 75 mA Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single–Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single–Ended) 1365 1690 1460 1755 1490 1815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH VOL 150 0.5 150 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V. 4. All loading with 50 Ω to VCC–2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 58 75 45 59 75 45 60 75 mA Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single–Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single–Ended) 3065 3390 3130 3455 3190 3515 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 8) 2.0 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH VOL 150 0.5 150 0.5 0.5 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V. 7. All loading with 50 Ω to VCC–2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC10EP105, MC100EP105 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 9) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 58 75 45 59 75 45 60 75 mA Output HIGH Voltage (Note 10) –1135 –1010 –885 –1070 –945 –820 –1010 –885 –760 mV VOL Output LOW Voltage (Note 10) –1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560 mV VIH Input HIGH Voltage (Single–Ended) –1210 –885 –1145 –820 –1085 –760 mV VIL Input LOW Voltage (Single–Ended) –1935 –1610 –1870 –1545 –1810 –1485 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 11) 0.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH VEE+2.0 0.0 VEE+2.0 0.0 150 0.5 VEE+2.0 150 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 Ω to VCC–2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 45 59 75 45 62 75 45 64 75 mA VOH Output HIGH Voltage (Note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single–Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single–Ended) 1355 1675 1355 1675 1355 1675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 14) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 0.5 150 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V. 13. All loading with 50 Ω to VCC–2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 59 75 45 62 75 45 64 75 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single–Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single–Ended) 3055 3375 3055 3375 3055 3375 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 17) 2.0 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 0.5 150 0.5 0.5 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V. 16. All loading with 50 Ω to VCC–2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP105, MC100EP105 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 18) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 45 59 75 45 62 75 45 64 75 mA Output HIGH Voltage (Note 19) –1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV Output LOW Voltage (Note 19) –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV VIH Input HIGH Voltage (Single–Ended) –1225 –880 –1225 –880 –1225 –880 mV VIL Input LOW Voltage (Single–Ended) –1945 –1625 –1945 –1625 –1945 –1625 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 20) 0.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH VOL VEE+2.0 0.0 VEE+2.0 0.0 150 0.5 VEE+2.0 150 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 Ω to VCC–2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. AC CHARACTERISTICS VCC = 0 V; VEE = –3.0 V to –5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21) –40°C Symbol Characteristic fmax Maximum Frequency (See Figure 3 Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential tSKEW Min Typ 25°C Max Min >3 175 85°C Max Min Typ >3 250 325 Within Device Skew Device to Device Skew (Note 22) 10 tJITTER Cycle–to–Cycle Jitter (See Figure 3 Fmax/JITTER) VPP Input Voltage Swing (Differential) tr tf Output Rise/Fall Times (20% – 80%) Q Typ 200 >3 275 350 50 10 0.2 <1 150 800 1200 100 150 200 225 ps 50 15 50 ps 0.2 <1 0.2 <1 ps 150 800 1200 150 800 1200 mV 120 170 220 150 200 250 ps 9 800 8 700 7 600 6 500 5 400 4 300 3 0 ÉÉ ÉÉ ÉÉ 2 (JITTER) 0 1000 2000 3000 FREQUENCY (MHz) Figure 3. Fmax/Jitter http://onsemi.com 5 JITTEROUT ps (RMS) VOUTpp (mV) 10 900 ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ GHz 375 1000 100 Unit 300 21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC–2.0 V. 22. Skew is measured between outputs under identical transitions. 200 Max 1 4000 5000 MC10EP105, MC100EP105 Q D Driver Device Receiver Device D Q 50 Ω 50 Ω VTT VTT = VCC – 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1504 – Metastability and the ECLinPS Family AN1568 – Interfacing Between LVDS and ECL AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8009 – ECLinPS Plus Spice I/O Model Kit AND8020 – Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 6 MC10EP105, MC100EP105 PACKAGE DIMENSIONS A 32 –T–, –U–, –Z– LQFP FA SUFFIX 32–LEAD PLASTIC PACKAGE CASE 873A–02 ISSUE A 4X A1 0.20 (0.008) AB T-U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 AE DETAIL Y 9 4X –Z– 9 V1 0.20 (0.008) AC T-U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T-U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M R M N D J 0.20 (0.008) SEATING PLANE SECTION AE–AE W K X DETAIL AD Q GAUGE PLANE H 0.250 (0.010) C E http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12 REF 0.090 0.160 0.400 BSC 1 5 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12 REF 0.004 0.006 0.016 BSC 1 5 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MC10EP105, MC100EP105 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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