ONSEMI 74FST3126

74FST3126
4−Bit Bus Switch
The ON Semiconductor 74FST3126 is a quad, high performance
switch. The device is CMOS TTL compatible when operating between
4 and 5.5 Volts. The device exhibits extremely low RON and adds
nearly zero propagation delay. The device adds no noise or ground
bounce to the system.
The device consists of four independent 1−bit switches with
separate Output/Enable (OE) pins. Port A is connected to Port B when
OE is high. If OE is low, the switch is high Z.
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MARKING
DIAGRAMS
•
•
•
•
•
•
•
•
14
14
Features
OE1
1A
1B
OE2
2A
2B
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SOIC−14
D SUFFIX
CASE 751A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
14
14
FST
3126
ALYW
1
TSSOP−14
DT SUFFIX
CASE 948G
1
VCC
OE4
4A
4B
OE3
3A
3B
16
16
S3126
ALYW
1
QSOP−16
QS SUFFIX
CASE 492
Figure 1. Pin Assignment for
SOIC and TSSOP
NC
OE1
1A
1B
OE2
2A
2B
GND
FST3126
AWLYWW
1
RON t 4 W Typical
Less Than 0.25 ns−Max Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
Pin−For−Pin Compatible With QS3126, FST3126, CBT3126
All Popular Packages: QSOP−16, TSSOP−14, SOIC−14
All Devices in Package TSSOP are Inherently Pb−Free*
A
Location
L, WL
Y
W, WW
Week
VCC
OE4
4A
4B
OE3
3A
3B
NC
1
=
Assembly
=
=
=
Wafer Lot
Year
Work
PIN NAMES
Pin
OE1, OE2, OE3, OE4
1A, 2A, 3A, 4A
Bus A
1B, 2B, 3B, 4B
Bus B
NC
Figure 2. Pin Assignment
for QSOP
Description
Bus Switch Enables
Not Connected
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 2
1
Publication Order Number:
74FST3126/D
74FST3126
OE1
1A
OE2
2A
OE3
3A
OE4
4A
1
2
3
1B
4
5
6
2B
10
9
8
3B
13
12
11
4B
Figure 3. Logic Diagram
TRUTH TABLE
Inputs
Outputs
OE
A, B
L
Z
H
A=B
ORDERING INFORMATION
Package
Shipping †
74FST3126D
SOIC−14
55 Units / Rail
74FST3126DR2
SOIC−14
2500 Units / Tape & Reel
74FST3126DT
TSSOP*
(Pb−Free)
96 Units / Rail
74FST3126DTR2
TSSOP*
(Pb−Free)
2500 Units / Tape & Reel
74FST3126QS
QSOP−16
96 Units / Rail
74FST3126QSR
QSOP−16
2500 Units / Tape & Reel
Device Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74FST3126
MAXIMUM RATINGS
Symbol
Value
Unit
DC Supply Voltage
*0.5 to )7.0
V
VI
DC Input Voltage
*0.5 to )7.0
V
VO
DC Output Voltage
*0.5 to )7.0
V
VI t GND
*50
mA
VO t GND
*50
mA
128
mA
VCC
Parameter
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IO
DC Output Sink Current
ICC
DC Supply Current per Supply Pin
$100
mA
IGND
DC Ground Current per Ground Pin
$100
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance (Note 1)
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILatchup
SOIC
TSSOP
QSOP
_C
_C
125
170
200
_C/W
Level 1
Oxygen Index: 28 to 34
ESD Withstand Voltage
Latchup Performance
260
)150
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
u2000
u200
V
Above VCC and Below GND at 85_C (Note 4)
$500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
TA
Operating Free−Air Temperature
Dt/DV
Input Transition Rise or Fall Rate
Min
Max
Unit
4.0
5.5
V
(Note 5)
0
5.5
V
(HIGH or LOW State)
0
VCC
V
*40
)85
_C
0
0
5
DC
ns/V
Operating, Data Retention Only
Switch Control Input
Switch I/O
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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3
74FST3126
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VIK
Clamp Diode Resistance
VIH
High−Level Input Voltage
VIL
Low−Level Input Voltage
Conditions
IIN = *18mA
VCC
TA = *40_C to )85_C
(V)
Min
Typ*
4.5
4.0 to 5.5
Max
Unit
*1.2
V
2.0
V
4.0 to 5.5
0.8
V
Input Leakage Current
0 v VIN v 5.5 V
5.5
$1.0
mA
IOZ
OFF−STATE Leakage Current
0 v A, B v VCC
5.5
$1.0
mA
RON
Switch On Resistance (Note 6)
VIN = 0 V, IIN = 64 mA
4.5
4
7
W
VIN = 0 V, IIN = 30 mA
4.5
4
7
VIN = 2.4 V, IIN = 15 mA
4.5
8
15
11
20
II
VIN = 2.4 V, IIN = 15 mA
4.0
ICC
Quiescent Supply Current
VIN = VCC or GND, IOUT = 0
5.5
3
mA
DICC
Increase In ICC per Input
One input at 3.4 V, Other inputs at VCC or GND
5.5
2.5
mA
*Typical values are at VCC = 5.0 V and TA = 25_C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch.
AC ELECTRICAL CHARACTERISTICS
Limits
TA = *40_C to )85_C
VCC = 4.5 to 5.5 V
Symbol
Parameter
Conditions
Figures
Min
Max
VCC = 4.0 V
Min
Max
Unit
0.25
0.25
ns
tPHL,
tPLH
Prop Delay Bus to Bus
(Note 7)
VI = OPEN
4 and 5
tPZH,
tPZL
Output Enable Time
VI = 7 V for tPZL
VI = OPEN for tPZH
4 and 5
1.0
4.5
5.0
ns
tPHZ,
tPLZ
Output Disable Time
VI = 7 V for tPLZ
VI = OPEN for tPHZ
4 and 5
1.5
5.7
6.2
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter
Conditions
Typ
Max
Unit
CIN
Control Pin Input Capacitance
VCC = 5.0 V
3
pF
CI/O
Input/Output Capacitance
VCC = 5.0 V, OE = 0 V
5
pF
8. TA = )25_C, f = 1 MHz, Capacitance is characterized but not tested.
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4
74FST3126
AC Loading and Waveforms
VI
500 W
FROM
OUTPUT
UNDER
TEST
CL*
500 W
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*CL = 50 pF
Figure 4. AC Test Circuit
tf = 2.5 nS
90 %
SWITCH
INPUT
tf = 2.5 nS
90 %
1.5 V
3.0 V
1.5 V
10 %
10 %
tPLH
GND
tPLH
VOH
1.5 V
OUTPUT
1.5 V
VOL
Figure 5. Propagation Delays
tf = 2.5 nS
tf = 2.5 nS
ENABLE
INPUT
90 %
90 %
1.5 V
1.5 V
10 %
10 %
tPZL
OUTPUT
3.0 V
GND
tPZL
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZL
VOH
1.5 V
OUTPUT
Figure 6. Enable/Disable Delays
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5
VOH − 0.3 V
74FST3126
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
B
M
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
SEATING
PLANE
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
0.25 (0.010)
8
S
DETAIL E
K
A
−V−
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
H
DETAIL E
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
74FST3126
PACKAGE DIMENSIONS
QSOP−16
QS SUFFIX
CASE 492−01
ISSUE O
−A−
Q
R
H x 45_
U
RAD.
0.013 X 0.005
DP. MAX
−B−
MOLD PIN
MARK
RAD.
0.005−0.010
TYP
G
L
0.25 (0.010)
M
P
T
DETAIL E
V
K
C
INCHES
DIM MAX
MIN
A
0.189
0.196
B
0.150
0.157
C
0.061
0.068
D
0.008
0.012
F
0.016
0.035
G
0.025 BSC
H
0.008
0.018
J 0.0098 0.0075
K
0.004
0.010
L
0.230
0.244
M
0_
8_
N
0_
7_
P
0.007
0.011
Q
0.020 DIA
R
0.025
0.035
U
0.025
0.035
V
0_
8_
MILLIMETERS
MAX
MIN
4.80
4.98
3.81
3.99
1.55
1.73
0.20
0.31
0.41
0.89
0.64 BSC
0.20
0.46
0.249
0.191
0.10
0.25
5.84
6.20
0_
8_
0_
7_
0.18
0.28
0.51 DIA
0.64
0.89
0.64
0.89
0_
8_
−T−
D 16 PL
0.25 (0.010)
N 8 PL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER
THAN THE TOP PACKAGE BY 4 MILS (NOTE:
LEAD SIDE ONLY). BOTTOM PACKAGE
DIMENSION SHALL FOLLOW THE DIMENSION
STATED IN THIS DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE
MOLD FLASH OR PROTRUSIONS. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 6 MILS
PER SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY
I.D.
SEATING
PLANE
M
T B
S
A
S
M
J
F
DETAIL E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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PUBLICATION ORDERING INFORMATION
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7
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For additional information, please contact your local
Sales Representative
74FST3126/D