ONSEMI 74FST3861

74FST3861
10−Bit Bus Switch
The ON Semiconductor 74FST3861 is a 10−bit, high performance
bus switch. The device is CMOS TTL compatible when operating
between 4.0 and 5.5 Volts. The device exhibits extremely low RON and
adds nearly zero propagation delay. The device adds no noise or
ground bounce to the system.
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Features
•
•
•
•
•
•
•
•
MARKING
DIAGRAMS
RON t 4 W Typical
Less Than 0.25 ns−Max Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
Pin−For−Pin Compatible With QS3861, FST3861, CBT3861
All Popular Packages: SOIC−24, TSSOP−24, QSOP−24
All Devices in Package TSSOP are Inherently Pb−Free*
NC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
24
24
1
24
24
TSSOP−24
DT SUFFIX
CASE 948H
24
H
Disconnect
FST3861
AWLYYWW
1
QSOP−24
QS SUFFIX
CASE 492B
A
Location
L, WL
Y, YY
W, WW
Week
Input
A Port = B Port
1
24
TRUTH TABLE
L
FST
3861
ALYW
1
Figure 1. 24−Lead
Pinout
Operation
1
SOIC−24
DW SUFFIX
CASE 751E
SO24−7/SO24−8/SO24−9
OE
FST3861
AWLYWW
1
=
Assembly
=
=
=
Wafer Lot
Year
Work
PIN NAMES
Pin
NOTE:
H = HIGH Voltage Level
L = LOW Voltage Level
Description
OE
Bus Switch Enables
NC
No Connect
A1 to A10
Bus A
B1 to B10
Bus B
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
74FST3861/D
74FST3861
A1
A10
OE
2
22
11
13
B1
B10
23
Figure 2. Logic Diagram
ORDERING INFORMATION
Device Order Number
Shipping †
Package
74FST3861DW
SOIC−24
48 Units / Rail
74FST3861DWR2
SOIC−24
2500 Units / Tape & Reel
74FST3861DT
TSSOP−24*
(Pb−Free)
96 Units / Rail
74FST3861DTR2
TSSOP−24*
(Pb−Free)
2500 Units / Tape & Reel
74FST3861QS
QSOP−24
96 Units / Rail
74FST3861QSR
QSOP−24
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MAXIMUM RATINGS
Symbol
VCC
Value
Unit
DC Supply Voltage
Parameter
*0.5 to )7.0
V
VI
DC Input Voltage
*0.5 to )7.0
V
VO
DC Output Voltage
*0.5 to )7.0
V
VI t GND
*50
mA
VO t GND
*50
mA
128
mA
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IO
DC Output Sink Current
ICC
DC Supply Current per Supply Pin
$100
mA
IGND
DC Ground Current per Ground Pin
$100
mA
TSTG
Storage Temperature Range
*65 to )150
°C
260
°C
)150
°C
125
170
200
°C/W
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILatchup
ESD Withstand Voltage
SOIC
TSSOP
QSOP
Level 1
Oxygen Index: 28 to 34
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Latchup Performance
UL 94 V−0 @ 0.125 in
u2000
u200
N/A
V
Above VCC and Below GND at 85°C (Note 4)
$500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
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2
74FST3861
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
Min
Max
Unit
4.0
5.5
V
(Note 5)
0
5.5
V
(HIGH or LOW State)
0
5.5
V
*40
)85
°C
ns/V
0
DC
5
Operating, Data Retention Only
VI
Input Voltage
VO
Output Voltage
TA
Operating Free−Air Temperature
Dt/DV
Input Transition Rise or Fall Rate
Switch I/O
Switch Control Input
VCC = 5.0 V $ 0.5 V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ*
4.5
Max
Unit
*1.2
V
VIK
Clamp Diode Resistance
VIH
High−Level Input Voltage
4.0 to 5.5
VIL
Low−Level Input Voltage
4.0 to 5.5
0.8
V
$1.0
mA
II
IIN = *18mA
TA = *405C to )855C
VCC
(V)
2.0
V
Input Leakage Current
0 v VIN v 5.5 V
5.5
IOZ
OFF−STATE Leakage Current
0 v A, B v VCC
5.5
$1.0
mA
RON
Switch On Resistance (Note 6)
VIN = 0 V, IIN = 64 mA
4.5
4
7
W
VIN = 0 V, IIN = 30 mA
4.5
4
7
VIN = 2.4 V, IIN = 15 mA
4.5
8
15
VIN = 2.4 V, IIN = 15 mA
4.0
11
20
ICC
Quiescent Supply Current
VIN = VCC or GND, IOUT = 0
5.5
3
mA
DICC
Increase In ICC per Input
One input at 3.4 V, Other inputs at VCC or GND
5.5
2.5
mA
*Typical values are at VCC = 5.0 V and TA = 25°C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
TA = *405C to )855C
CL = 50 pF, RU = RD = 500 W
VCC = 4.5−5.5 V
Symbol
Parameter
Conditions
Min
Max
VCC = 4.0 V
Min
Max
Unit
0.25
0.25
ns
tPHL,
tPLH
Prop Delay Bus to Bus (Note 7)
VI = OPEN
tPZH,
tPZL
Output Enable Time, IOE to Bus A, B
VI = OPEN for tPZH
1.0
5.1
5.6
ns
tPHZ,
tPLZ
Output Disable Time, IOE to Bus A, B
VI = OPEN for tPHZ
1.0
5.5
5.5
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter
Conditions
Typ
Max
Unit
CIN
Control Pin Input Capacitance
VCC = 5.0 V
3
pF
CI/O
A/B Port Input/Output Capacitance
VCC, OE = 5.0 V
5
pF
8. TA = )25°C, f = 1 MHz, Capacitance is characterized but not tested.
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3
74FST3861
AC Loading and Waveforms
VI
500 W
FROM
OUTPUT
UNDER
TEST
CL*
500 W
NOTES:
1. Input driven by 50 W source terminated in 50 W.
2. CL includes load and stray capacitance.
*CL = 50 pF
Figure 3. AC Test Circuit
tf = 2.5 nS
90 %
SWITCH
INPUT
tf = 2.5 nS
90 %
1.5 V
3.0 V
1.5 V
10 %
10 %
tPLH
GND
tPLH
VOH
1.5 V
OUTPUT
1.5 V
VOL
Figure 4. Propagation Delays
tf = 2.5 nS
tf = 2.5 nS
ENABLE
INPUT
90 %
90 %
1.5 V
1.5 V
10 %
10 %
tPZL
OUTPUT
3.0 V
GND
tPZL
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZL
VOH
1.5 V
OUTPUT
Figure 5. Enable/Disable Delays
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4
VOH − 0.3 V
74FST3861
PACKAGE DIMENSIONS
SOIC−24
D SUFFIX
CASE 751E−04
ISSUE E
−A−
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
−B−
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
X 45 _
C
−T−
SEATING
PLANE
22X
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
M
K
G
DIM
A
B
C
D
F
G
J
K
M
P
R
TSSOP−24
DT SUFFIX
CASE 948H−01
ISSUE A
24X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
2X
24
L/2
13
B
−U−
L
PIN 1
IDENT.
12
1
0.15 (0.006) T U
S
S
S
A
−V−
C
0.10 (0.004)
−T− SEATING
PLANE
ÇÇÇ
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
G
D
H
N
K
0.25 (0.010)
K1
J1
SECTION N−N
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE −W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
7.70
7.90
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
M
−W−
N
DETAIL E
F
DETAIL E
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5
INCHES
MIN
MAX
0.303
0.311
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
74FST3861
PACKAGE DIMENSIONS
QSOP−24
QS SUFFIX
CASE 492B−01
ISSUE O
−A−
Q
R
H x 45_
U
L
MOLD PIN
MARK
RAD.
0.013 X 0.005
DP. MAX
−B−
RAD.
0.005−0.010
TYP
G
P
0.25 (0.010)
DETAIL E
T
M
V
N 8 PL
J
K
C
24 PL
−T−
D
0.25 (0.010)
M
SEATING
PLANE
M
T B
S
A
F
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
INCHES
DIM MAX
MIN
A
0.337
0.344
B
0.150
0.157
C
0.061
0.068
D
0.008
0.012
F
0.016
0.035
G
0.025 BSC
H
0.008
0.018
J 0.0098 0.0075
K
0.004
0.010
L
0.230
0.244
M
0_
8_
N
0_
7_
P
0.027
0.037
Q
0.035 DIA
R
0.035
0.045
U
0.035
0.045
V
0_
8_
MILLIMETERS
MAX
MIN
8.56
8.74
3.81
3.99
1.55
1.73
0.20
0.31
0.41
0.89
0.64 BSC
0.20
0.46
0.249
0.191
0.10
0.25
5.84
6.20
0_
8_
0_
7_
0.69
0.94
0.89 DIA
0.89
1.14
0.89
1.14
0_
8_
DETAIL E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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For additional information, please contact your local
Sales Representative
74FST3861/D