ONSEMI MC74HC157ADT

MC74HC157A
Quad 2-Input Data
Selectors / Multiplexers
High–Performance Silicon–Gate CMOS
The MC74HC157A is identical in pinout to the LS157. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device routes 2 nibbles (A or B) to a single port (Y) as
determined by the Select input. The data is presented at the outputs in
noninverted form. A high level on the Output Enable input sets all four
Y outputs to a low level.
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 82 FETs or 20.5 Equivalent Gates
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MARKING
DIAGRAMS
16
PDIP–16
N SUFFIX
CASE 648
16
1
1
16
SO–16
D SUFFIX
CASE 751B
16
1
16
1
1
A
WL
YY
WW
5
A1
11
A2
4
14
A3
7
9
3
B0
NIBBLE
B INPUTS
12
6
B1
Y0
Y1
Y2
DATA
OUTPUTS
Y3
10
B2
13
B3
SELECT
OUTPUT
ENABLE
PIN 16 = VCC
PIN 8 = GND
1
15
FUNCTION TABLE
Inputs
Output
Enable
Select
Outputs
Y0 – Y3
H
L
L
X
L
H
L
A0 – A3
B0 – B3
 Semiconductor Components Industries, LLC, 2000
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
SELECT
1
16
A0
2
15
B0
3
14
VCC
OUTPUT
ENABLE
A3
Y0
4
13
B3
A1
5
12
Y3
B1
6
11
A2
Y1
7
10
B2
GND
8
9
Y2
ORDERING INFORMATION
Device
X = don’t care
A0 – A3, B0 – B3 = the levels of the
respective Data–Word Inputs.
March, 2000 – Rev. 8
HC
157A
ALYW
TSSOP–16
DT SUFFIX
CASE 948F
2
A0
NIBBLE
A INPUTS
HC157A
AWLYWW
1
16
LOGIC DIAGRAM
MC74HC157AN
AWLYYWW
1
Package
Shipping
MC74HC157AN
PDIP–16
2000 / Box
MC74HC157AD
SOIC–16
48 / Rail
MC74HC157ADR2
SOIC–16
2500 / Reel
MC74HC157ADT
TSSOP–16
96 / Rail
MC74HC157ADTR2
TSSOP–16
2500 / Reel
Publication Order Number:
MC74HC157A/D
MC74HC157A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = VCC – 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Minimum High–Level Output
Voltage
Vin = VIH
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
Maximum Low–Level Output
Voltage
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 µA
Vin = VIL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
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2
V
MC74HC157A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
IOZ
Maximum Three–State
Leakage Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
4.0
40
160
µA
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 4)
2.0
3.0
4.5
6.0
105
65
21
18
130
85
26
22
160
115
32
27
ns
tPLH,
tPHL
Maximum Propagation Delay, Select to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
70
22
19
140
90
28
24
165
115
33
28
ns
tPLH,
tPHL
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 4)
2.0
3.0
4.5
6.0
100
60
20
17
125
80
25
21
150
110
30
26
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
33
pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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3
MC74HC157A
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
The data present on these pins is in its noninverted form. For
the Output Enable input at a high level, the outputs are at a
low level.
Nibble A inputs. The data present on these pins is
transferred to the outputs when the Select input is at a low
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.
CONTROL INPUTS
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
Nibble B inputs. The data present on these pins is
transferred to the outputs when the Select input is at a high
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.
OUTPUTS
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at
these outputs when the Output Enable input is at a low level.
SWITCHING WAVEFORMS
tr
tr
tf
90%
50%
10%
INPUT A OR B
GND
90%
50%
10%
OUTPUT Y
tTLH
tTLH
tTHL
Figure 1. HC157A
GND
tPHL
tPLH
tPHL
90%
50%
10%
VCC
90%
50%
10%
SELECT
tPLH
OUTPUT Y
tf
VCC
tTHL
Figure 2. Y versus Select, Noninverted
tr
tf
VCC
90%
50%
10%
OUTPUT
ENABLE
GND
tPHL
tPLH
90%
50%
10%
OUTPUT Y
tTHL
tTLH
Figure 3. HC157A
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
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4
MC74HC157A
EXPANDED LOGIC DIAGRAM
2
A0
B0
A1
B1
NIBBLE
OUTPUTS
5
7
6
Y1
11
A3
B3
SELECT
Y0
DATA
OUTPUTS
A2
B2
OUTPUT ENABLE
4
3
9
10
Y2
14
12 Y3
13
15
1
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5
MC74HC157A
PACKAGE DIMENSIONS
PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A
–
16
9
1
8
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
0.250 0.270
6.85
6.35
0.145 0.175
4.44
3.69
0.015 0.021
0.53
0.39
0.040 0.070
1.77
1.02
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.008 0.015
0.38
0.21
0.110 0.130
3.30
2.80
0.295 0.305
7.74
7.50
10°
0°
10°
0°
0.020 0.040
1.01
0.51
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A
–
16
9
1
8
–B
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 8 PL
0.25 (0.010)
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
http://onsemi.com
6
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
MC74HC157A
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
DETAIL E
H
D
G
http://onsemi.com
7
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HC157A
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MC74HC157A/D