MC100LVEL59 3.3VECL Triple 2:1 Multiplexer Description The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and random logic applications. http://onsemi.com Features • • • • • • Individual or Common Select Controls 500 ps Typical Propagation Delays ESD Protection: >2 kV HBM SO−20 WB DW SUFFIX CASE 751D The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors • • Q Output will Default LOW with Inputs Open or at VEE • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity; • Pb Pkg Level 1 Pb−Free Pkg Level 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−O @ 0.125 in, Oxygen Index 28 to 34 Transistor Count = 182 devices • • Pb−Free Packages are Available* MARKING DIAGRAM* 20 100LVEL59 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 4 1 Publication Order Number: MC100LVEL59/D MC100LVEL59 VCC Q0 Q0 VCC Q1 Q1 VCC Q2 Q2 VEE 20 19 18 17 16 15 14 13 12 11 9 10 1 1 0 2 COM_SEL D0a 1 3 D0b 4 0 1 5 SEL0 D1a 6 D1b 7 0 8 SEL1 D2a D2b SEL2 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: 20−Lead SOIC (Top View) Table 1. PIN DESCRIPTION Pins Function D0a−D2a D0b−D2b SEL0−SEL2 COM_SEL Q0−Q2; Q0−Q2 VCC VEE ECL Input Data a ECL Input Data b ECL Individual Select Input ECL Common Select Input ECL Differential Outputs Positive Supply Negative Supply Table 2. TRUTH TABLE SEL Data H L a b Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm 20 SOIC 20 SOIC 140 100 °C/W °C/W qJC Thermal Resistance (Junction to Case) Standard Board 20 SOIC 30 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C VI VCC VI VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 MC100LVEL59 Table 4. LVPECL DC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V (Note 1) −40°C Symbol Characteristic Min 25°C Typ Max 27 32 Min 85°C Typ Max 27 32 Min Typ Max Unit 27 32 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage 1490 1825 1490 1825 1490 1825 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. Table 5. LVNECL DC CHARACTERISTICS VCC= 0.0 V; VEE= −3.3 V (Note 3) −40°C Symbol Characteristic Min 25°C Typ Max 27 32 Min 85°C Typ Max 27 32 Min Typ Max Unit 27 32 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 4) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 4) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage −1810 −1475 −1810 −1475 −1810 −1475 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. http://onsemi.com 3 MC100LVEL59 Table 6. AC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V or VCC= 0.0 V; VEE= −3.3 V (Note 5) −40°C Symbol Characteristic Min fmax Maximum Toggle Frequency tPLH tPHL Propagation Delay tskew Output−Output Skew tJITTER Cycle−to−Cycle Jitter tr tf Output Rise/Fall Times Q (20% − 80%) DATA to Q/Q SEL to Q/Q COM_SEL to Q/Q Typ 25°C Max Min TBD 340 340 340 Typ Max 340 340 340 690 690 690 340 340 340 Max 100 TBD 540 200 ps ps ps TBD 200 Unit GHz 690 690 690 100 TBD 540 Typ TBD 100 200 Min TBD 690 690 690 Any Dn, Dm to Q 85°C 540 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. VEE can vary ±0.3 V. Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 4 MC100LVEL59 ORDERING INFORMATION Package Package† MC100LVEL59DW SOIC−20 38 Units / Rail MC100LVEL59DWG SOIC−20 (Pb−Free) 38 Units / Rail MC100LVEL59DWR2 SOIC−20 1000 / Tape & Reel MC100LVEL59DWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 5 MC100LVEL59 PACKAGE DIMENSIONS SO−20 WB DW SUFFIX CASE 751D−05 ISSUE G A 20 q X 45 _ E h H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 SEATING PLANE C T DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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