FAN5355 1A / 0.8A, 3MHz Digitally Programmable Regulator Features Description The FAN5355 device is a high-frequency, ultra-fast transient response, synchronous step-down DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors. The FAN5355 supports up to 800mA or 1A load current. 93% Efficiency at 3MHz 800mA or 1A Output Current 2 I C™-Compatible Interface up to 3.4Mbps 6-bit VOUT Programmable from 0.75V to 1.975V 2.7V to 5.5V Input Voltage Range 3MHz Fixed-Frequency Operation Excellent Load and Line Transient Response Small Size, 1μH Inductor Solution The FAN5355 operates at 3MHz (nominal) fixed switching frequency using either its internal oscillator or external SYNC frequency. ±2% PWM DC Voltage Accuracy 35ns Minimum On-Time High-Efficiency, Low-Ripple, Light-Load PFM Smooth Transition between PWM and PFM 37μA Operating PFM Quiescent Current 2 Pin-Selectable or I C™ Programmable Output Voltage On-the-Fly External Clock Synchronization 10-lead MLP (3 x 3mm) or 12-bump CSP Packages Applications Cell Phones, Smart Phones ® ® 3G, WiFi , WiMAX™, and WiBro Data Cards ® Netbooks , Ultra-Mobile PCs SmartReflex™-Compliant Power Supply Split Supply DSPs and μP Solutions OMAP™, XSCALE™ ® Mobile Graphic Processors (NVIDIA , ATI) LPDDR2 and Memory Modules The device is ideal for mobile phones and similar portable applications powered by a single-cell Lithium-Ion battery. With 2 an output-voltage range adjustable via I C™ interface from 0.75V to 1.975V, the device supports low-voltage DSPs and processors, core power supplies, and memory modules in smart phones, PDAs, and handheld computers. During light-load conditions, the regulator includes a PFM mode to enhance light-load efficiency. The regulator transitions smoothly between PWM and PFM modes with no In hardware shutdown, the current glitches on VOUT. consumption is reduced to less than 200nA. The serial interface is compatible with Fast/Standard and 2 High-Speed mode I C specifications, allowing transfers up to 3.4Mbps. This interface is used for dynamic voltage scaling with 12.5mV voltage steps for reprogramming the mode of operation (PFM or Forced PWM), or to disable/enable the output voltage. The chip's advanced protection features include short-circuit protection and current and temperature limits. During a sustained over-current event, the IC shuts down and restarts after a delay to reduce average power dissipation into a fault. During startup, the IC controls the output slew rate to minimize input current and output overshoot at the end of soft start. The IC maintains a consistent soft-start ramp, regardless of output load during startup. The FAN5355 is available in 10-lead MLP (3x3mm) and 12-bump CSP packages. I2C is a trademark of Philips Corporation. Wi-Fi® is a registered trademark of Wi-Fi Alliance Corporation. WiMax™ is a trademark of WIMAX Forum Corporation. WiBro® is a registered trademark of Telecommunications Technology Association. Netbooks® is a registered trademark of Netbooks, Inc. SmartReflex and OMAP are trademarks of Texas Instruments. XSCALE is a trademark of Intel Corporation. NVIDIA is a registered trademark of NVIDIA Corporation. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator May 2010 Slave Address LSB (1) Order Number Output Current VOUT Programming Power-up Defaults Option A1 A0 mA Min. Max. FAN5355UC00X FAN5355MP00X FAN5355UC02X 00 00 02 0 0 1 0 0 0 800 800 800 1.5375 1.5375 FAN5355UC03X FAN5355UC06X 03 06 0 0 0 0 1000 1000 0.7500 0.7500 0.7500 0.7500 1.1875 1.4375 1.5375 1.9750 VSEL0 VSEL1 Package (2) 1.05 1.05 1.05 1.35 1.35 1.20 WLCSP-12, 2.23x1.46mm MLP-10, 3x3mm WLCSP-12, 2.23x1.46mm 1.00 1.80 1.20 1.80 WLCSP-12, 2.23x1.46mm WLCSP-12, 2.23x1.46mm Notes: 1. The “X” designator specifies tape and reel packaging. 2. VOUT is limited to the maximum voltage for all VSEL codes greater than the maximum VOUT listed. Typical Application AVIN PVIN Q1 VIN CIN EN VSEL MODULATOR VCCIO VOUT SW SYNC Q2 L OUT COUT SDA SCL PGND AGND VOUT Figure 1. Typical Application Component Description Vendor Parameter (3) L Min. Typ. Max. Units 0.7 1.0 1.2 μH L1 (LOUT) 1μH nominal Murata LQM31P or FDK MIPSA2520 COUT 0603 (1.6x0.8x0.8) 10μF X5R or better Murata or equivalent GRM188R60G106ME47D (4) C 5.6 10.0 12.0 μF CIN 0603 (1.6x0.8x0.8) 4.7μF X5R or better Murata or equivalent GRM188R60J475KE19D C(4) 3.0 4.7 5.6 μF DCR (series R) 100 mΩ Table 1. Recommended External Components Notes: 3. Minimum L incorporates tolerance, temperature, and partial saturation effects (L decreases with increasing current). 4. Minimum C is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to frequency, dielectric, and voltage bias effects. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 2 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Ordering Information Top View Bottom View Top View Figure 2. WLCSP-12, 2.23x1.46mm Figure 3. MLP10, 3x3mm Pin Definitions Pin # Name (5) Description WLCSP MLP A1, B1 9 PGND A2 10 SW A3 1 PVIN Power Input Voltage. Connect to input power source. The connection from this pin to CIN should be as short as possible. B2 N/A SYNC Sync. When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency on this pin. In PWM mode, when this pin is statically LOW or statically HIGH, or when its frequency is outside of the specified capture range, the regulator’s frequency is controlled by its internal 3MHz clock. B3 2 AVIN Analog Input Voltage. Connect to input power source as close as possible to the input bypass capacitor. C1 8, PAD AGND Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. C2 7 EN C3 3 SDA D1 6 VOUT Output Voltage Monitor. Tie this pin to the output voltage. This is a signal input pin to the control circuit and does not carry DC current. D2 5 VSEL Voltage Select. When HIGH, VOUT is set by VSEL1. When LOW, VOUT is set by VSEL0. This behavior can be overridden through I2C register settings. This pin should not be left floating. D3 4 SCL SCL. I2C interface serial clock. Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The connection from this pin to the bottom of CIN should be as short as possible. Switching Node. Connect to output inductor. Enable. When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is minimized. This pin should not be left floating. SDA. I2C interface serial data. Note: 5. All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum 2 quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I C control is unused, tie SDA and SCL to AVIN. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 3 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC ESD Parameter Min. Max. AVIN, SW, PVIN Pins -0.3 6.5 Other Pins -0.3 Electrostatic Discharge Protection Level Units V (6) AVIN + 0.3 V Human Body Model per JESD22-A114 3.5 KV Charged Device Model per JESD22-C101 1.5 KV TJ Junction Temperature –40 +150 °C TSTG Storage Temperature –65 +150 °C +260 °C TL Lead Soldering Temperature, 10 Seconds Note: 6. Lesser of 6.5V or AVIN+0.3V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VIN f VCCIO Parameter Min. Max. Units Supply Voltage 2.7 5.5 V Frequency Range 2.7 3.3 MHz SDA and SCL Voltage Swing(7) 2.5 V TA Ambient Temperature –40 +85 °C TJ Junction Temperature –40 +125 °C Note: 2 7. The I C interface operates with tHD;DAT = 0 as long as the pull-up voltage for SDA and SCL is less than 2.5V. If voltage 2 swings greater than 2.5V are required (for example if the I C bus is pulled up to VIN), the minimum tHD;DAT must be 2 increased to 80ns. Most I C masters change SDA near the midpoint between the falling and rising edges of SCL, which provides ample tHD;DAT . Dissipation Ratings(8) Package (9) RθJA Power Rating at TA ≤ 25°C Derating Factor > TA = 25ºC Molded Leadless Package (MLP) 49ºC/W 2050mW 21mW/ºC Wafer-Level Chip-Scale Package (WLCSP) 110ºC/W 900mW 9mW/ºC Notes: 8. 9. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max) - TA ] / θJA. This thermal data is measured with high-K board (four-layer board according to JESD51-7 JEDEC standard). © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 4 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Absolute Maximum Ratings VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1. Symbol Parameter Conditions Min. Typ. Max. Units 5.5 V Power Supplies VIN Input Voltage Range IQ Quiescent Current ISD Shutdown Supply Current VUVLO Under-Voltage Lockout Threshold VUVHYST Under-Voltage Lockout Hysteresis 2.7 IO = 0mA, PFM Mode 37 IO = 0mA, 3MHz PWM Mode 4.8 EN = GND 0.1 2.0 EN = VIN, EN_DCDC bit = 0, SDA = SCL = VIN 0.1 2.0 VIN Rising VIN Falling 50 μA mA μA 2.40 2.60 V 2.00 2.15 2.30 V 200 250 300 mV ENABLE, VSEL, SDA, SCL, SYNC VIH HIGH-Level Input Voltage VIL LOW-Level Input Voltage IIN Input Bias Current 1.2 V Input tied to GND or VIN 0.01 VIN = 3.6V, CSP Package 145 VIN = 3.6V, MLP Package 165 VIN = 2.7V, MLP Package 200 0.4 V 1.00 μA Power Switch and Protection RDS(ON)P ILKGP P-Channel MOSFET On Resistance P-Channel Leakage Current VDS = 6V 1 VIN = 3.6V, CSP Package RDS(ON)N N-Channel MOSFET On Resistance 95 VIN = 2.7V, MLP Package 101 N-Channel Leakage Current VDS = 6V RDIS Discharge Resistor for Power-Down Sequence Options 03 and 06 P-MOS Current Limit μA 75 VIN = 3.6V, MLP Package ILKGN ILIMPK mΩ mΩ 1 μA 60 120 Ω 2.7V ≤ VIN ≤ 4.2V, Options 00 and 02 1150 1350 1600 2.7V ≤ VIN ≤ 5.5V, Options 00 and 02 1050 1350 1600 2.7V ≤ VIN ≤ 4.2V, Options 03 and 06 1350 1550 1800 2.7V ≤ VIN ≤ 5.5V, Options 03 and 06 1250 1550 1800 mA TLIMIT Thermal Shutdown 150 °C THYST Thermal Shutdown Hysteresis 20 °C Frequency Control Oscillator Frequency 2.65 3.00 3.35 MHz fSYNC fSW Synchronization Range 2.7 3.0 3.3 MHz DSYNC Synchronization Duty Cycle 20 80 % Continued on the following page… © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 5 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Electrical Specifications VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1. Symbol Parameter Conditions Min. IOUT(DC) = 0, Forced PWM, VOUT = 1.35V Typ. Max. Units –1.5 1.5 % 2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 800mA, Forced PWM –2 2 % 2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 800mA, PFM Mode –1.5 3.5 % IOUT(DC) = 0, Forced PWM, VOUT = 1.20V –1.5 1.5 % 2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.4375, IOUT(DC) = 0 to 800mA, Forced PWM –2 2 % 2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.4375, IOUT(DC) = 0 to 800mA, PFM Mode –1.5 3.5 % IOUT(DC) = 0, Forced PWM, VOUT = 1.20V Output Regulation Option 00 Option 02 VOUT VOUT Accuracy Option 03 Option 06 –1.5 1.5 % 2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 1A, Forced PWM –2 2 % 2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375, IOUT(DC) = 0 to 1A, PFM Mode –1.5 3.5 % IOUT(DC) = 0, Forced PWM, VOUT = 1.800V –1.5 1.5 % 2.7V ≤ VIN ≤ 5.5V, VOUT from 1.185 to 1.975, IOUT(DC) = 0 to 1A, Forced PWM –2 2 % 2.7V ≤ VIN ≤ 5.5V, VOUT from 1.185 to 1.975, IOUT(DC) = 0 to 1A, PFM Mode –1.5 3.5 % ΔVOUT ΔILOAD Load Regulation IOUT(DC) = 0 to 800mA, Forced PWM –0.5 %/A ΔVOUT ΔVIN Line Regulation 2.7V ≤ VIN ≤ 5.5V, IOUT(DC) = 300mA 0 %/V VRIPPLE Output Ripple Voltage PWM Mode, VOUT = 1.35V 2.2 mVPP PFM Mode, IOUT(DC) = 10mA 20 mVPP Continued on the following page… © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 6 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Electrical Specifications (Continued) VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1. Symbol Parameter Conditions Min. Differential Nonlinearity Monotonicity Assured by Design Typ. Max. Units 0.8 LSB 6-Bit DAC Timing I2CEN EN HIGH to I2C Start tV(L-H) VOUT LOW to HIGH Settling μs 250 RLOAD = 75Ω, Transition from 1.0 to 1.5375V VOUT Settled to within 2% of Set Point μs 7 Soft Start tSS VSLEW Regulator Enable to Regulated VOUT Option 06 RLOAD > 5Ω, to VOUT = 1.8000V 170 210 μs All Other Options RLOAD > 5Ω, to VOUT = Power-up Default 140 180 μs (10) Soft-start VOUT Slew Rate 18.75 V/ms Note: 10. Option 03 and 06 slew rates are 35.5V/ms during the first 16μs of soft start. AVIN PVIN Q1 7-bit DAC EN VSEL SYNC SDA I2C INTERFACE AND LOGIC SCL VIN CIN REF FPWM VOUT SW SOFT START Q2 MODULATOR L OUT COUT EN_REG PGND CLK VOUT AGND 3 MHz Osc Figure 4. Block Diagram © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 7 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Electrical Specifications (Continued) Guaranteed by design. Symbol Parameter Conditions fSCL SCL Clock Frequency tBUF Bus-Free Time between STOP and START Conditions tHD;STA START or Repeated-START Hold Time tLOW tHIGH SCL LOW Period SCL HIGH Period tSU;STA Repeated-START Setup Time tSU;DAT Data Setup Time (7) tHD;DAT Data Hold Time tRCL SCL Rise Time tFCL tRDA tRCL1 tFDA tSU;STO CB SCL Fall Time SDA Rise Time Rise Time of SCL After a Repeated START Condition and After ACK Bit SDA Fall Time Stop Condition Setup Time Min. Max. Units 100 400 3400 1700 kHz kHz kHz kHz 4.7 μs Fast Mode 1.3 μs Standard Mode Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode 4 600 160 4.7 1.3 160 320 4 600 60 120 4.7 600 160 250 100 10 μs ns ns Capacitive Load for SDA and SCL © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 Typ. Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode 8 0 0 0 0 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 10 20 4 600 160 μs ns ns ns μs ns ns ns μs ns ns ns ns ns 3.45 900 70 150 1000 300 80 160 300 300 40 80 1000 300 80 160 300 300 80 160 μs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 400 μs ns ns pF www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator I2C Timing Specifications tF tSU;STA tBUF SDA tR SCL TSU;DAT tHD;STO tHIGH tLOW tHD;STA tHD;DAT tHD;STA REPEATED START START STOP START 2 Figure 5. I C Interface Timing for Fast and Slow Modes tFDA tRDA REPEATED START tSU;DAT STOP SDAH tSU;STA tRCL1 SCLH tFCL tRCL tSU;STO tHIGH tLOW tHD;STA tHD;DAT REPEATED START note A = MCS Current Source Pull-up = RP Resistor Pull-up Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. 2 Figure 6. I C Interface Timing for High-Speed Mode © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 9 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Timing Diagrams Unless otherwise specified, Auto-PWM/PFM, VIN = 3.6V, TA = 25°C, and recommended components as specified in Table 1. Efficiency 100 % 100 % 90% 90% 80% 80% 70% Eff iciency Efficiency 70% Auto PWM/PFM 60% Forced PWM 50% 40% Forced PWM 50% 40% 30% 30% VIN = 3.6V VOUT = 1.05V 20% VIN = 3.6V VOUT = 1.35V 20% 10% 10% 0% 0% 1 10 I LOAD 100 1 100 0 10 I Ou tput Curre nt (mA) Figure 7. Efficiency vs. Load at VOUT = 1.05V LOAD 100 100 0 Ou tput Curre nt (mA) Figure 8. Efficiency vs. Load at VOUT = 1.35V 100 % 100% 90% 90% 80% 80% Auto PWM/PFM 70% 60% Auto PWM/PFM 70% Forced PWM Efficiency Efficiency Auto PWM/PFM 60% 50% 40% VIN = 3.6V VOUT = 1.5V 30% Forced PWM 60% 50% 40% VIN = 3.6V VOUT = 1.8V 30% 20% 20% 10% 10% 0% 0% 1 10 I LOAD 10 0 100 0 1 Figure 9. Efficiency vs. Load at VOUT = 1.50V © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 10 I Ou tpu t Curre nt (mA) LOAD 100 1000 Output Current (mA) Figure 10. Efficiency vs. Load at VOUT = 1.80V 10 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Typical Performance Characteristics 1.064 1.364 1.062 1.362 1.060 1.360 1.058 VOUT (V) VOUT (V) Unless otherwise specified, Auto-PWM/PFM, VIN = 3.6V, TA = 25°C, and recommended components as specified in Table 1. Auto PWM/PFM 1.056 Forced PWM 1.054 1.358 Auto PWM/PFM 1.356 Forced PWM 1.354 1.052 1.352 1.050 1.350 1.348 1.048 1 10 100 1 1000 10 Figure 11. Load Regulation at VOUT = 1.05V 0.10% 1.814 0.05% Output Voltage (V) 1.812 1.810 VOUT (V) 1000 Figure 12. Load Regulation at VOUT = 1.35V 1.816 1.808 Auto PWM/PFM 1.806 Forced PWM 1.804 0.00% -0.05% -0.10% -0.15% 1.802 -0.20% 1.800 -0.25% 1.798 VIN = 2.7V VIN = 3.6V VIN = 5.5V -0.30% 1 10 100 1000 -40 -20 0 I LOAD Output Current (mA) 20 40 60 80 Temperature (C) Figure 13. Load Regulation at VOUT = 1.80V Figure 14. % VOUT Shift vs. Temperature (Normalized) 70 6.0 Shutdown Current (µA) 65 Quiescent Current (μA) 100 I LOAD Output Current (mA) I LOAD Output Current (mA) 60 55 50 VSEL = 1.8V VSEL = 0V 45 40 5.0 VSEL = 1.8V 4.0 VSEL = 0V 3.0 2.0 1.0 35 30 2.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.5 4.0 4.5 5.0 5.5 V IN Input Voltage (V) VIN Input Voltage (V) Figure 15. Quiescent Current, ILOAD = 0, EN = 1.8V © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 3.0 Figure 16. Shutdown Current, ILOAD = 0, EN = 0 11 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Typical Performance Characteristics Unless otherwise specified, VIN = 3.6V, VOUT = 1.35V, and load step tR = tF < 100ns. Load Transient Response Figure 17. 50mA to 400mA to 50mA, Forced PWM Figure 18. 50mA to 400mA to 50mA, Auto PWM/PFM Figure 19. 400mA to 750mA to 400mA, Auto PWM/PFM Figure 20. 0mA to 125mA to 0mA, Auto PWM/PFM © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 12 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Typical Performance Characteristics (Continued) Unless otherwise specified, VIN = 3.6V. VSEL Transitions Figure 21. Single-Step, RLOAD = 6.2Ω Figure 22. Single-Step, RLOAD = 6.2Ω Figure 23. Single-Step, RLOAD = 50Ω Figure 24. Single-Step, RLOAD = 50Ω © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 13 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Typical Performance Characteristics (Continued) Unless otherwise specified, VIN = 3.6V. VSEL Transitions Figure 25. Single-Step from Forced PWM (MODE1=0), RLOAD = 50Ω Figure 26. Single-Step, RLOAD = 6.2Ω IL VOUT VSEL Figure 27. Single–Step from Auto PWM/PFM (MODE1=1), RLOAD = 50Ω © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 Figure 28. Multi-Step, Controlled DAC Step (9.6mV/µs) DEF_Slew 6 (110), 800mA Load 14 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Typical Performance Characteristics (Continued) RLOAD is switched with N-channel MOSFET from VOUT to GND. VIN = 3.6V, initial VOUT = 1.35V, initial ILOAD = 0mA. Short Circuit and Over-Current Fault Response Figure 29. Metallic Short Applied at VOUT Figure 30. Metallic Short Applied at VOUT Figure 31. RLOAD = 660mΩ Figure 32. RLOAD = 660mΩ © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 15 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Typical Performance Characteristics (Continued) Unless otherwise specified, VIN = 3.6V. Figure 34. SW-Node Jitter, External Synchronization (Infinite Persistence), ILOAD = 200mA Figure 33. SW-Node Jitter (Infinite Persistence), ILOAD = 200mA PSRR Attenuation (dB) 70 60 IOUT=500mA IOUT=150mA 50 IOUT=20mA 40 30 20 10 (10) 0.1 1.0 10.0 100.0 1,000.0 Frequency (KHz) Figure 36. VIN Ripple Rejection (PSRR) Figure 35. Soft Start, RLOAD = 50Ω © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 16 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Typical Performance Characteristics (Continued) Overview Power-Up, EN, and Soft-Start The FAN5355 is a synchronous buck regulator that typically operates at 3MHz with moderate to heavy load currents. At light load currents, the converter operates in power-saving PFM mode. The regulator automatically transitions between fixed-frequency PWM and variable-frequency PFM mode to maintain the highest possible efficiency over the full range of load current. All internal circuits remain de-biased and the IC is in a very low quiescent-current state until the following are true: 1. 2. 2 At that point, the IC begins a soft-start cycle, its I C interface is enabled, and its registers are loaded with their default values. The FAN5355 uses a very fast non-linear control architecture to achieve excellent transient response with minimum-sized external components. During the initial soft start, VOUT ramps linearly to the set point programmed in the VSEL register selected by the VSEL pin. The soft start features a fixed output-voltage slew rate of 18.75V/ms and achieves regulation approximately 90μs after EN rises. PFM mode is enabled during soft start until the output is in regulation, regardless of the MODE bit settings. This allows the regulator to start into a partially charged output without discharging it; in other words, the regulator does not allow current to flow from the load back to the battery. 2 The FAN5355 integrates an I C-compatible interface, allowing transfers up to 3.4Mbps. This communication interface can be used to: 1. 2. 3. 4. 5. VIN is above its rising UVLO threshold, and EN is HIGH. Dynamically re-program the output voltage in 12.5mV increments. Reprogram the mode of operation to enable or disable PFM mode. Control voltage transition slew rate. Control the frequency of operation by synchronizing to an external clock. Enable / disable the regulator. As soon as the output has reached its set point, the control forces PWM mode for about 85μs to allow all internal control circuits to calibrate. Symbol Description tSSDLY 2 For more details, refer to the I C Interface and Register Description sections. tREG Output Voltage Programming Option (11) 00, 02, 03 06 tPOK VOUT Equation VOUT = 0.75 + NVSEL • 12.5mV (1) VOUT = 1.1875 + NVSEL • 12.5mV (2) Time from EN to start of soft-start ramp VOUT ramp start Opt 03, 06 to regulation Opt 00, 02 PWROK (CONTROL2[5]) rising from end of tREG and regulator stays in PWM mode during this time Value (μs) 75 16 +(VSEL–0.7) X 53 (VSEL–0.1) X 53 10 Table 2. Soft-Start Timing (see Figure 37) where NVSEL is the decimal value of the setting of the VSEL register that controls VOUT. Note: 11. Option 02 maximum voltage is 1.4375V (see Table 3). Figure 37. Soft-Start Timing © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 17 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Circuit Description VSEL Value Dec Binary Hex 0 000000 00 1 000001 01 2 000010 02 3 000011 03 4 000100 04 5 000101 05 6 000110 06 7 000111 07 8 001000 08 9 001001 09 10 001010 0A 11 001011 0B 12 001100 0C 13 001101 0D 14 001110 0E 15 001111 0F 16 010000 10 17 010001 11 18 010010 12 19 010011 13 20 010100 14 21 010101 15 22 010110 16 23 010111 17 24 011000 18 25 011001 19 26 011010 1A 27 011011 1B 28 011100 1C 29 011101 1D 30 011110 1E 31 011111 1F 32 100000 20 33 100001 21 34 100010 22 35 100011 23 36 100100 24 37 100101 25 38 100110 26 39 100111 27 40 101000 28 41 101001 29 42 101010 2A 43 101011 2B 44 101100 2C 45 101101 2D 46 101110 2E 47 101111 2F 48 110000 30 49 110001 31 50 110010 32 51 110011 33 52 110100 34 53 110101 35 54 110110 36 55 110111 37 56 111000 38 57 111001 39 58 111010 3A 59 111011 3B 60 111100 3C 61 111101 3D 62 111110 3E 63 111111 3F 00, 03 0.7500 0.7625 0.7750 0.7875 0.8000 0.8125 0.8250 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 VOUT 02 0.7500 0.7625 0.7750 0.7875 0.8000 0.8125 0.8250 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 1.4375 The EN_DCDC bit, VSELx[7] can be used to enable the regulator in conjunction with the EN pin. Setting EN_DCDC with EN HIGH begins the soft-start sequence described above. 06 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 1.6125 1.6250 1.6375 1.6500 1.6625 1.6750 1.6875 1.7000 1.7125 1.7250 1.7375 1.7500 1.7625 1.7750 1.7875 1.8000 1.8125 1.8250 1.8375 1.8500 1.8625 1.8750 1.8875 1.9000 1.9125 1.9250 1.9375 1.9500 1.9625 1.9750 2 EN_DCDC Bit EN Pin IC REGULATOR 0 1 1 0 0 1 0 1 OFF ON OFF ON OFF ON OFF OFF Table 4. EN_DCDC Behavior Light-Load (PFM) Operation The FAN5355 offers a low-ripple, single-pulse PFM mode to save power and improve efficiency when the load current is very low. PFM operation features: Smooth transitions between PFM and PWM modes Single-pulse operation for low ripple Predictable PFM entry and exit currents. PFM begins after the inductor current has become discontinuous, crossing zero during the PWM cycle in 32 consecutive cycles. PFM exit occurs when discontinuous current mode (DCM) operation cannot supply sufficient current to maintain regulation. During PFM mode, the inductor current ripple is about 40% higher than in PWM mode. The load current required to exit PFM mode is thereby about 20% higher than the load current required to enter PFM mode, providing sufficient hysteresis to prevent “mode chatter.” While PWM ripple voltage is typically less than 4mVPP, PFM ripple voltage can be up to 30mVPP during very light load. To prevent significant undershoot when a load transient occurs, the initial DC set point for the regulator in PFM mode is set 10mV higher than in PWM mode. This offset decays to about 5mV after the regulator has been in PFM mode for ~100μs. The maximum instantaneous voltage in PFM is 30mV above the set point. PFM mode can be disabled by writing to the mode control bits: CONTROL1[3:0] (see Table 10 for details). Some vendors provide both “Light PFM” (LPFM) and “Fast PFM” (FPFM) modes, while the FAN5355 provides only one PFM mode. The FAN5355’s single PFM mode features the fast transient recovery of FPFM, but does this with the low quiescent current consumption similar to LPFM mode. 18 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Software Enable Table 3. VSEL vs. VOUT Multi-Step Mode: The nominal internal oscillator frequency is 3MHz. The regulator runs at its internal clock frequency until these conditions are met: 1. EN_SYNC bit, CONTROL1[5], is set; and 2. A valid frequency appears on the SYNC pin. The internal DAC is stepped at a rate defined by DEFSLEW, CONTROL2[2:0], ranging from 000 to 110. This mode minimizes the current required to charge COUT and thereby minimizes the current drain from the battery when transitioning. The PWROK bit, CONTROL2[5], remains LOW until about 1.5μs after the DAC completes its ramp. Applies to Options 03 and 06 only. fSYNC Valid CONTROL2 PLL_MULT fSYNC Divider Min. Typ. Max. 00 1 1.80 3.00 4.00 01 2 0.90 1.50 2.00 10 3 0.60 1.00 1.33 11 4 0.45 0.75 1.00 VHIGH VOUT VLOW Table 5. SYNC Frequency Validation for fOSC(INTERNAL)=3.0MHz VSEL tPOK(L-H) If the EN_SYNC is set and SYNC fails validation, the regulator continues to run at its internal oscillator frequency. The regulator is functional if fSYNC is valid, as defined in Table 5, but its performance is compromised if fSYNC is outside the fSYNC window in the Electrical Specifications. Single-Step Mode: When CONTROL1[3:2] = 00 and the VSEL line is LOW, the converter operates according to the MODE0 bit, CONTROL1[0], with synchronization disabled regardless of the state of the EN_SYNC and HW_nSW bits. Used if DEFSLEW, CONTROL2[2:0] = 111. The internal DAC is immediately set to the higher voltage and the regulator performs the transition as quickly as its current-limit circuit allows, while avoiding excessive overshoot. Output Voltage Transitions Figure 39 shows single-step transition timing. tV(L-H) is the time it takes the regulator to settle to within 2% of the new set point and is typically 7μs for a full-range transition (from 000000 to 111111). The PWROK bit, CONTROL2[5], goes LOW until the transition is complete and VOUT settled. This typically occurs ~2μs after tV(L-H). PWROK Figure 38. Multi-Step VOUT Transition The IC regulates VOUT to one of two set point voltages, as determined by the VSEL pin and the HW_nSW bit. VSEL Pin HW_nSW Bit VOUT Set Point PFM 0 1 x 1 1 0 VSEL0 VSEL1 VSEL1 Allowed Per MODE1 Per MODE1 It is good practice to reduce the load current before making positive VSEL transitions. This reduces the time required to make positive load transitions and avoids current-limit-induced overshoot. Table 6. VOUT Set Point and Mode Control MODE_CTRL, CONTROL1[3:2] = 00 VHIGH If HW_nSW = 0, VOUT transitions are initiated through the following sequence: 1. Write the new setpoint in VSEL1. 2. Write desired transition rate in DEFSLEW, CONTROL2[2:0], and set the GO bit in CONTROL2[7]. 98% VHIGH VOUT VLOW If HW_nSW = 1, VOUT transitions are initiated either by changing the state of the VSEL pin or by writing to the VSEL register selected by the VSEL pin. VSEL PWROK Positive Transitions tPOK(L-H) Figure 39. Single-Step VOUT Transition When transitioning to a higher VOUT, the regulator can perform the transition using multi-step or single-step mode. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 tV(L-H) All positive VOUT transitions inhibit PFM until the transition is complete, which occurs at the end of tPOK(L-H). 19 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Switching-Frequency Control and Synchronization When moving from VSEL=1 to VSEL=0, the regulator enters PFM mode, regardless of the condition of the SYNC pin or MODE bits, and remains in PFM until the transition is completed. Reverse current through the inductor is blocked, and the PFM minimum frequency control inhibited, until the new set point is reached, at which time the regulator resumes control using the mode established by MODE_CTRL. The transition time from VHIGH to VLOW is controlled by the load current and output capacitance as: t V (H−L ) = COUT • VHIGH − VLOW ILOAD The FAN5355’s serial interface is compatible with standard, 2 fast, and HS mode I C bus specifications. The FAN5355’s SCL line is an input and its SDA line is a bi-directional opendrain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first. SDA and SCL are normally pulled up to a system I/O power 2 supply (VCCIO), as shown in Figure 1. If the I C interface is not used, SDA and SCL should be tied to AVIN to minimize quiescent current consumption. (3) Addressing VHIGH FAN5355 has four user-accessible registers: Address VOUT VSEL0 VSEL1 CONTROL1 CONTROL2 VLOW VSEL PWROK tV(L-H) tPOK(L-H) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 2 Table 7. I C Register Addresses Figure 40. Negative VOUT Transition Slave Address In Table 8, A1 and A0 are according to the Ordering Information table on page 2. Protection Features Current Limit / Auto-Restart The regulator includes cycle-by-cycle current limiting, which prevents the instantaneous inductor current from exceeding the current-limit threshold. 6 1 0 Table 8. The IC enters “fault” mode after sustained over-current. If current limit is asserted for more than 32 consecutive cycles (about 20μs), the IC returns to shut-down state and remains in that condition for ~80μs. After that time, the regulator attempts to restart with a normal soft-start cycle. If the fault has not cleared, it shuts down ~10μs later. 5 4 3 2 1 0 0 1 0 A1 A0 R/ W 2 I C Slave Address Bus Timing As shown in Figure 41, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the next SCL rising edge. If the fault is a short circuit, the initial current limit is ~30% of the normal current limit, which produces a very small drain on the system power source. Data change allowed Thermal Protection SDA When the junction temperature of the IC exceeds 150°C, the device turns off all output MOSFETs and remains in a low quiescent-current state until the die cools to 130°C before commencing a normal soft-start cycle. TH SCL TSU Figure 41. Data Transfer Timing Under-Voltage Lockout (UVLO) The IC turns off all MOSFETs and remains in a very low quiescent-current state until VIN rises above the UVLO threshold. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 7 Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a “START” condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 42. 20 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator I2C Interface Negative Transitions The master then generates a repeated-start condition (Figure 44) that causes all slaves on the bus to switch to HS mode. 2 The master then sends I C packets, as described above, using the HS-mode clock rate and timing. Slave Address MS Bit SCL The bus remains in HS mode until a stop bit (Figure 43) is sent by the master. While in HS mode, packets are separated by repeated-start conditions (Figure 44). Figure 42. Start Bit Slave Releases A transaction ends with a “STOP” condition, which is defined as SDA transitioning from 0 to 1 with SCL HIGH, as shown in Figure 43. Slave Releases Master Drives SDA tHD;STA SLADDR MS Bit SCL tHD;STO ACK(0) or NACK(1) SDA tSU;STA ACK(0) or NACK(1) Figure 44. Repeated-Start Timing Read and Write Transactions SCL The following figures outline the sequences for data read and write. Bus control is signified by the shading of the packet, Figure 43. Stop Bit S The protocols for High-Speed (HS), Low-Speed (LS), and Fast-Speed (FS) modes are identical, except the bus speed for HS mode is 3.4MHz. HS mode is entered when the bus master sends the HS master code 00001XXX after a start condition. The master code is sent in FS mode (less than 400KHz clock) and slaves do not ACK this transmission. A 7 bits 0 Slave Drives Bus . Symbol Definition A Slave Address and All addresses and data are MSB first. High-Speed (HS) Mode S Master Drives Bus defined as During a read from the FAN5355 (Figure 46), the master issues a “Repeated Start” after sending the register address and before resending the slave address. The “Repeated Start” is a 1 to 0 transition on SDA while SCL is HIGH, as shown in Figure 44. START, see Figure 42. ACK. The slave drives SDA to 0 to acknowledge the preceding packet. NACK. The slave sends a 1 to NACK the preceding packet. Repeated START, see Figure 44. STOP, see Figure 43. R P Table 9. 2 I C Bit Definitions for Figure 45 - Figure 46 0 8 bits 0 8 bits 0 A Reg Addr A Data A P Figure 45. Write Transaction 7 bits S Slave Address 0 0 8 bits 0 A Reg Addr A 7 bits R Slave Address 1 0 8 bits 1 A Data A P Figure 46. Read Transaction © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 21 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator THD;STA SDA Default Values Each option of the FAN5355 (see Ordering Information on page 2) has different default values for the some of the register bits. Table 10 defines both the default values and the bit’s type (as defined in Table 11) for each available option. VSEL0 VSEL1 Option 7 6 5 4 3 2 1 0 VOUT Option 7 6 5 4 3 2 1 0 VOUT 00 02 03 06 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1.05 1.05 1.00 1.80 00 02 03 06 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1.35 1.20 1.20 1.80 CONTROL1 CONTROL2 Option 7 6 5 4 3 2 1 0 Option 7 6 5 4 3 2 1 0 00, 02 03, 06 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 00, 02 03, 06 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 Table 10. Default Values and Bit Types for VSEL and CONTROL Registers # # # Active bit. Disabled. Read-only. Changing this bit changes the behavior of the converter, as described below. Converter logic ignores changes made to this bit. Bit can be written to and read-back. Writing to this bit through I2C does not change the read-back value, nor does it change converter behavior. Table 11. Bit-Type Definitions for Table 10 © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 22 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Register Descriptions The following table defines the operation of each register bit. Superscript characters define the default state for each option. 0,2,3,6 A Superscripts signify the default values for options 00, 02, 03, and 06, respectively. signifies the default for all options. Bit Name Value Description VSEL0 7 EN_DCDC 6 Reserved 5:0 DAC[5:0] 0 1A 1 Table 10 VSEL1 7 EN_DCDC 6 Reserved 5:0 DAC[5:0] 0 1A 1 Table 10 CONTROL1 7:6 Reserved 5 EN_SYNC 4 HW_nSW 10 A 0A 3:2 MODE_CTRL 1 MODE1 0 MODE0 1 0 1A 00A 01 10 11 0A 1 0A 1 CONTROL2 7 GO 6 OUTPUT_ DISCHARGE 5 PWROK (read only) 4:3 PLL_MULT 2:0 DEFSLEW 0A 1 0A 1 0 1 00A 01 10 11 000 001 010 011 100 101 110 111A Register Address: 00 Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write to bit 7 in either register establishes the EN_DCDC value. Device enabled when EN pin is HIGH, disabled when EN is LOW. 6-bit DAC value to set VOUT. Register Address: 01 Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL0. A write to bit 7 in either register establishes the EN_DCDC value. Device enabled when EN pin is HIGH, disabled when EN is LOW. 6-bit DAC value to set VOUT. Register Address: 02 Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be used to distinguish between vendors via I2C. Disables external signal on SYNC from affecting the regulator. When a valid frequency is detected on SYNC, the regulator synchronizes to it and PFM is disabled, except when MODE = 00, VSEL pin = LOW, and HW_nSW = 1. VOUT is controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting the GO bit. VOUT is programmed by the VSEL pin. VOUT = VSEL1 when VSEL is HIGH, and VSEL0 when VSEL is LOW. Operation follows MODE0, MODE1. PFM with automatic transitions to PWM, regardless of VSEL. PFM disabled (forced PWM), regardless of VSEL. Unused. PFM disabled (forced PWM) when regulator output is controlled by VSEL1. PFM with automatic transitions to PWM when regulator output is controlled by VSEL1. PFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on the operation of the regulator. Register Address: 03 This bit has no effect when HW_nSW = 1. Starts a VOUT transition if HW_nSW = 0. This bit must be written by the external master to 1 for the next VOUT transition to start, even if its value might have already been 1 from the last VOUT transition. When the regulator is disabled, VOUT is not discharged. When the regulator is disabled, VOUT discharges through an internal pull down. VOUT is not in regulation or is in current limit. VOUT is in regulation. fSW = fSYNC when synchronization is enabled. fSW = 2 X fSYNC when synchronization is enabled. fSW = 3 X fSYNC when synchronization is enabled. fSW = 4 X fSYNC when synchronization is enabled. VOUT slews at 0.15mV/μs during positive VOUT transitions. VOUT slews at 0.30mV/μs during positive VOUT transitions. VOUT slews at 0.60mV/μs during positive VOUT transitions. VOUT slews at 1.20mV/μs during positive VOUT transitions. VOUT slews at 2.40mV/μs during positive VOUT transitions. VOUT slews at 4.80mV/μs during positive VOUT transitions. VOUT slews at 9.60mV/μs during positive VOUT transitions. Positive VOUT transitions use single-step mode (see Figure 39). © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 23 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Bit Definitions BALL A1 INDEX AREA A E (Ø0.25) Cu PAD B 0.03 C 2X 0.50 1.00 A1 (Ø0.35) SOLDER MASK OPENING 0.50 D 0.03 C TOP VIEW RECOMMENDED LAND PATTERN (NSMD) 2X 0.06 C 0.05 C D 0.332±0.018 0.625 0.539 0.250±0.025 SEATING PLANE C SIDE VIEWS (X)+/-.018 0.005 0.50 C A B A. NO JEDEC REGISTRATION APPLIES B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D DATUM C, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. 12 X Ø0.315 +/- .025 D C 0.50 B A (Y)+/-.018 F FOR DIMENSIONS D, E, X, AND Y SEE 1 2 PRODUCT DATASHEET. F. BALL COMPOSITION: Sn95.5Ag3.9Cu0.6 SAC405 ALLOY G. DRAWING FILENAME: MKT-UC012AArev2 3 BOTTOM VIEW Figure 47. 12-Bump WLCSP, 0.5mm Pitch Product-Specific Dimensions Product D E X Y FAN5355UC 2.210 +/-0.040 1.440 +/-0.040 0.220 0.355 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 24 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Physical Dimensions 3.0 0.10 C 10 A 2X 6 1.55 2.00 3.10 2.33 0.78 0.55 B 2.25 2.40 2.00 3.0 0.10 C 2X TOP VIEW 0.8 MAX 1 0.50 0.25 5 RECOMMENDED LAND PATTERN (0.20) 0.05 0.00 0.02 D 0.10 C 0.08 C 0.23 C SIDE VIEW S E A TING P LA NE (3.00±0.10) 2.40 PIN #1 IDENT (0.38) 5 1 1.40 (3.00±0.10) E 0.55±0.10 10 0.30 0.20 0.5 6 2.0 0.10 0.05 C A B C BOTTOM VIEW A. CONFORMS TO JEDEC REGISTRATION MO-229, VARIATION WEED-5 EXCEPT WHERE NOTED B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LAND PATTERN DIMENSIONS ARE NOMINAL REFERENCE VALUES ONLY E. NOT COMPLIANT MLP10ArevB Figure 48. 10-pin, 3x3mm Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 25 www.fairchildsemi.com FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator Physical Dimensions FAN5355 — 1A / 0.8A, 3MHz Digitally Programmable Regulator © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.6 26 www.fairchildsemi.com