MC100EPT26 3.3V1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator Description The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8−lead package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board. The VBB output allows the EPT26 to be used in a single−ended input mode. In this mode the VBB output is tied to the D0 input for a non−inverting buffer or the D0 input for an inverting buffer. If used, the VBB pin should be bypassed to ground with > 0.01 mF capacitor. For a single−ended direct connection, use an external voltage reference source such as a resistor divider. Do not use VBB for a single−ended direct connection or port to another device. http://onsemi.com MARKING DIAGRAMS* 8 SO−8 D SUFFIX CASE 751 8 1 KPT26 ALYW G 1 8 TSSOP−8 DT SUFFIX CASE 948R 8 1 Features • • • • • • • • 1.4 ns Typical Propagation Delay Maximum Frequency > 275 MHz Typical DFN8 MN SUFFIX CASE 506AA The 100 Series Contains Temperature Compensation Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V 1 1 4 KA26 ALYWG G 3W MG G 24 mA TTL outputs A L Y W M G Q Outputs Will Default LOW with Inputs Open or at VEE VBB Output Pb−Free Packages are Available = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 14 1 Publication Order Number: MC100EPT26/D MC100EPT26 Table 1. PIN DESCRIPTION NC D 1 8 2 7 VCC Pin Q0 LVTTL D VBB 3 4 6 5 LVPECL Q1 Function Q0, Q1 LVTTL Outputs D0**, D1** Differential LVPECL Inputs Pair VCC Positive Supply VBB Output Reference Voltage GND Ground NC No Connect EP Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. GND ** Pins will default to VCC/2 when left open. (Top View) Figure 1. 8−Lead Pinout and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 50 kW Internal Input Pullup Resistor ESD Protection 50 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SO−8 TSSOP−8 DFN8 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 1.5 kV > 100 V > 2 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 UL 94 V−0 @ 0.125 in 117 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100EPT26 Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Rating Unit 3.8 V 0 to 3.8 V ± 0.5 mA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder 265 265 °C VCC Positive Power Supply GND = 0 V VIN Input Voltage GND = 0 V IBB VBB Sink/Source TA Condition 2 VI VCC Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 2) −40°C Symbol Min Characteristic Typ 25°C Max Min 85°C Typ Max Min Typ Max Unit VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Voltage Reference 1910 2160 1910 2160 1910 2160 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3) 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current 2035 1.2 2035 150 D D −150 −150 150 −150 −150 2035 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input parameters vary 1:1 with VCC. 3. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 5. TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V; TA = −40°C to 85°C Symbol Characteristic Condition Min VOH Output HIGH Voltage IOH = −3.0 mA VOL Output LOW Voltage IOL = 24 mA ICCH Power Supply Current 10 ICCL Power Supply Current 15 IOS Output Short Circuit Current −50 Typ Max 2.4 Unit V 0.5 V 20 18 mA 28 35 mA −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 3 MC100EPT26 Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; GND = 0.0 V (Note 4) −40°C 25°C Min Typ fmax Maximum Frequency (Figure 2) 275 350 tPLH, tPHL Propagation Delay to Output Differential (Note 5) 1.2 1.2 1.5 1.5 2.0 1.8 tSK+ + tSK−− tSKPP Within Device Skew++ Within Device Skew− − Device−to−Device Skew (Note 6) 15 20 100 tJITTER Random Clock Jitter (RMS) (Figure 2) @ v 200 MHz @ > 200 MHz VPP Input Voltage Swing (Differential Configuration) tr tf Output Rise/Fall Times (0.8V − 2.0V) Symbol Characteristic Q, Q Max 85°C Min Typ 275 350 Max Min Typ 275 350 1.2 1.2 1.5 1.5 2.0 1.8 60 85 500 15 20 100 6 20 30 275 150 800 1200 330 600 950 Max 1.3 1.2 1.7 1.5 2.2 1.8 ns 60 85 500 20 30 100 85 85 500 ps 6 40 30 275 6 170 30 275 150 800 1200 150 800 1200 330 600 950 330 650 950 Unit MHz ps mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 3. 5. Reference (VCC = 3.3 V ± 5%; GND = 0 V) 6. Skews are measured between outputs under identical transitions. VOL 0.5 V VOH 8 VOH (V) 2.0 JITTER 4 1.0 0.0 0 100 200 FREQUENCY (MHz) Figure 2. Typical VOH / Jitter versus Frequency (255C) http://onsemi.com 4 0 300 RANDOM CLOCK JITTER (ps RMS) 12 3.0 MC100EPT26 APPLICATION TTL RECEIVER CHARACTERISTIC TEST *CL includes fixture capacitance CL* RL AC TEST LOAD GND Figure 3. TTL Output Loading Used for Device Evaluation ORDERING INFORMATION Package Shipping † SOIC−8 98 Units / Rail MC100EPT26DG SOIC−8 (Pb−Free) 98 Units / Rail MC100EPT26DR2 SOIC−8 2500 / Tape & Reel MC100EPT26DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100EPT26DT TSSOP−8 100 Units / Rail MC100EPT26DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100EPT26DTR2 TSSOP−8 2500 / Tape & Reel MC100EPT26DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100EPT26MNR4 DFN8 1000 / Tape & Reel DFN8 (Pb−Free) 1000 / Tape & Reel Device MC100EPT26D MC100EPT26MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MC100EPT26 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 6 MC100EPT26 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− H 0.10 (0.004) D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100EPT26 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF S M T U V S 0.25 (0.010) B −U− 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S M A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 8 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100EPT26 PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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