N64S830HA 64Kb Low Power Serial SRAMs 8K × 8 bit Organization Overview Features The ON Semiconductor serial SRAM family includes several integrated memory devices including this 64K serially accessed Static Random Access Memory, internally organized as 8K words by 8 bits. The devices are designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high-speed performance and low power. The devices operate with a single chip select (CS) input and use a simple Serial Peripheral Interface (SPI) serial bus. A single data in and data out line is used along with a clock to access data within the devices. The N64S830HA devices include a HOLD pin that allows communication to the device to be paused. While paused, input transitions will be ignored. The devices can operate over a wide temperature range of -40oC to +85oC and can be available in several standard package offerings. • Power Supply Range 2.5 to 3.6V • Very low standby current As low as 1uA • Very low operating current As low as 3mA • Simple memory control Single chip select (CS) Serial input (SI) and serial output (SO) • Flexible operating modes Word read and write Page mode (32 word page) Burst mode (full array) • Organization 8K x 8 bit • Self timed write cycles • Built-in write protection (CS high) • HOLD pin for pausing communication • High reliability Unlimited write cycles • RoHS Compliant Packages Green SOIC and TSSOP Device Options Part Number N64S830HAS2 N64S830HAT2 Density Power Supply (V) Speed (MHz) 64Kb 3.0 20 ©2009 SCILLC. All rights reserved. June 2009 - Rev. K Package SOIC TSSOP Typical Standby Current Read/Write Operating Current 1uA 3 mA @ 1Mhz Publication Order Number: N64S830HA/D N64S830HA Package Configurations Pin Names Pin Function CS 1 8 CS SCK SI SO HOLD NC VCC Chip Select Input Serial Clock Input Serial Data Input Serial Data Output Hold Input No Connect SO 2 7 HOLD NC 3 6 SCK VSS 4 5 SI Power CS 1 8 VSS VSS Ground SO 2 3 VSS 4 Functional Block Diagram SCK HOLD CS Clock Circuitry Decode Logic SDI Data In Receiver SDO 64Kb SRAM Array Data Out Buffer Rev. K | Page 2 of 15 | www.onsemi.com TSSOP NC SOIC Pin Name VCC 7 HOLD 6 SCK 5 SI N64S830HA Absolute Maximum Ratings1 Item Symbol Rating Unit Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC+0.3 V Voltage on VCC Supply Relative to VSS VCC –0.3 to 4.5 V Power Dissipation PD 500 mW Storage Temperature TSTG –40 to 125 o Operating Temperature TA -40 to +85 o Soldering Temperature and Time TSOLDER 260oC, 10sec o C C C 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Item Symbol Test Conditions Min. Supply Voltage VCC 3V Device Input High Voltage VIH Typ1 Max Unit 2.5 3.6 V 0.7 x VCC VCC+0.3 V –0.3 0.8 V Input Low Voltage VIL Output High Voltage VOH IOH = -0.4mA Output Low Voltage VOL IOL = 1mA 0.2 V Input Leakage Current ILI CS = VCC, VIN = 0 to VCC 0.5 µA Output Leakage Current ILO CS = VCC, VOUT = 0 to VCC 0.5 µA ICC1 F = 1MHz, IOUT = 0 3 mA ICC2 F = 10MHz, IOUT = 0 6 mA ICC3 F = fCLK MAX, IOUT = 0 10 mA ISB CS = VCC, VIN = VSS or VCC 4 µA Read/Write Operating Current Standby Current VCC–0.5 V 1 1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and are not 100% tested. Capacitance1 Item Symbol Test Condition Input Capacitance CIN I/O Capacitance CI/O Max Unit VIN = 0V, f = 1 MHz, TA = 25oC 7 pF VIN = 0V, f = 1 MHz, TA = 25oC 7 pF 1. These parameters are verified in device characterization and are not 100% tested Rev. K | Page 3 of 15 | www.onsemi.com Min N64S830HA Timing Test Conditions Item Input Pulse Level 0.1VCC to 0.9 VCC Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 100pF Operating Temperature -40 to +85 oC Timing Item Symbol Clock Frequency Clock Rise Time Min. Max. Units fCLK 20 MHz tR 2 us Clock Fall Time tF 2 us Clock High Time tHI 25 ns Clock Low Time tLO 25 ns Clock Delay Time tCLD 25 ns CS Setup Time tCSS 25 ns CS Hold Time tCSH 50 ns CS Disable Time tCSD 25 ns SCK to CS tSCS 5 ns Data Setup Time tSU 10 ns Data Hold Time tHD 10 ns Output Valid From Clock Low tV 25 ns Output Hold Time tHO Output Disable Time tDIS HOLD Setup Time tHS 10 ns HOLD Hold Time tHH 10 ns HOLD Low to Output High-Z tHZ 10 ns HOLD High to Output Valid tHV 0 ns 20 Rev. K | Page 4 of 15 | www.onsemi.com 50 ns ns N64S830HA Serial Input Timing tCSD tCLD CS tR tF tCSH tSCS tCSS SCK tSU tHD MSB in SI LSB in SO High-Z Serial Output Timing CS tLO tHI tCSH SCK tV tDIS SO MSB out LSB out SI Don’t Care Hold Timing CS tHS tHS tHH SCK tHH SO n+2 n+1 n High-Z tHV n tHZ SI n+2 n+1 n-1 tSU n Don’t Care HOLD Rev. K | Page 5 of 15 | www.onsemi.com n n-1 N64S830HA Control Signal Descriptions Signal Name I/O Description CS Chip Select I A low level selects the device and a high level puts the device in standby mode. If CS is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence being started. SCK Serial Clock I Synchronizes all activities between the memory and controller. All incoming addresses, data and instructions are latched on the rising edge of SCK. Data out is updated on SO after the falling edge of SCK. SI Serial Data In I Receives instructions, addresses and data on the rising edge of SCK. SO Serial Data Out O Data is transferred out after the falling edge of SCK. I A high level is required for normal operation. Once the device is selected and a serial sequence is started, this input may be taken low to pause serial communication without resetting the serial sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the Hold function will not be invoked until the next SCK high to low transition. The device must remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low. Lowering the HOLD input at any time will take to SO output to High-Z. HOLD Hold Functional Operation Basic Operation The 64Kb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI) common on many standard micro-controllers. It may also interface with other non-SPI ports by programming discrete I/O lines to operate the device. The serial SRAM contains an 8-bit instruction register and is accessed via the SI pin. The CS pin must be low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it was held. The following table contains the possible instructions and formats. All instructions, addresses and data are transferred MSB first and LSB last. Instruction Set Instruction Instruction Format READ 0000 0011 Description Read data from memory starting at selected address WRITE 0000 0010 Write data to memory starting at selected address RDSR 0000 0101 Read status register WRSR 0000 0001 Write status register Rev. K | Page 6 of 15 | www.onsemi.com N64S830HA READ Operations The serial SRAM READ is selected by enabling CS low. First, the 8-bit READ instruction is transmitted to the device followed by the 16-bit address with the 3 MSBs being don’t care. After the READ instruction and addresses are sent, the data stored at that address in memory is shifted out on the SO pin after the output valid time from the clock edge. If operating in page mode, after the initial word of data is shifted out, the data stored at the next memory location on the page can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is read out. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. If operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory location can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (1FFFh), the address counter wraps to the address 0000h. This allows the burst read cycle to be continued indefinitely. All READ operations are terminated by pulling CS high. Word READ Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 15 14 Instruction SI 0 0 0 0 0 10 11 21 22 23 2 1 0 24 25 26 7 6 5 27 28 29 30 31 2 1 0 16-bit address 0 1 1 13 12 Data Out SO High-Z Rev. K | Page 7 of 15 | www.onsemi.com 4 3 N64S830HA Page and Burst READ Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 Instruction SI 0 0 0 0 10 11 21 22 23 2 1 0 24 25 26 27 28 29 30 31 1 0 16-bit address 0 0 1 15 1 14 13 12 Don’t Care ADDR 1 Data Out from ADDR 1 7 High-Z SO 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 6 5 4 3 2 47 Don’t Care Data Out from ADDR 3 Data Out from ADDR 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 Data Out from ADDR n 1 0 ... 7 6 5 4 3 2 1 0 Page READ Sequence SI 16-bit address Page address (X) Word address (Y) Data Words: sequential, at the end of the page the address wraps back to the beginning of the page SO Page X Page X Word Y Word Y+1 Word Y+2 Page X Page X Page X Page X Word 31 Word 0 Word 1 Burst READ Sequence SI Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. 16-bit address Page address (X) Word address (Y) ... SO ... Page X Page X Page X Page X Page X Page X Word Y Word Y+1 Word 31 Word 0 Word 1 Word Y-1 Word Y Rev. K | Page 8 of 15 | www.onsemi.com Page X+1 Page X+1 Word Y+1 N64S830HA WRITE Operations The serial SRAM WRITE is selected by enabling CS low. First, the 8-bit WRITE instruction is transmitted to the device followed by the 16-bit address with the 3 MSBs being don’t care. After the WRITE instruction and addresses are sent, the data to be stored in memory is shifted in on the SI pin. If operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. Simply write the data on SI pin and continue to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. The new data will replace data already stored in the memory locations. If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (1FFFh), the address counter wraps to the address 0000h. This allows the burst write cycle to be continued indefinitely. Again, the new data will replace data already stored in the memory locations. All WRITE operations are terminated by pulling CS high. Word WRITE Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 15 14 Instruction SI SO 0 0 0 0 0 10 11 21 22 23 24 25 26 2 1 0 7 6 5 16-bit address 0 1 0 13 12 ... 27 28 29 30 31 3 2 1 0 Data In High-Z Rev. K | Page 9 of 15 | www.onsemi.com 4 N64S830HA Page and Burst WRITE Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 15 14 Instruction SI 0 0 0 0 10 11 21 22 23 24 25 26 27 28 29 30 31 2 1 0 7 6 5 4 3 2 1 0 16-bit address 0 0 1 0 13 12 ADDR 1 SO Data In to ADDR 1 High-Z 32 33 34 35 36 37 38 39 40 6 5 4 3 42 43 44 45 46 47 Data In to ADDR 3 Data In to ADDR 2 7 41 2 1 0 7 6 5 4 3 Data In to ADDR n 2 1 0 ... 7 6 5 4 3 2 1 0 High-Z Page WRITE Sequence Data Words: sequential, at the end of the page the address wraps back to the beginning of the page SI 16-bit address Page address (X) Word address (Y) Page X Page X Word Y Word Y+1 Word Y+2 Page X Page X Page X Page X Word 31 Word 0 Word 1 High-Z SO Burst WRITE Sequence ... SI 16-bit address Page address (X) Word address (Y) ... Page X Page X Page X Page X Page X Page X Word Y Word Y+1 Word 31 Word 0 Word 1 Word Y-1 Word Y Page X+1 Page X+1 Word Y+1 Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. SO High-Z Rev. K | Page 10 of 15 | www.onsemi.com N64S830HA WRITE Status Register Instruction (WRSR) This instruction provides the ability to write the status register and select among several operating modes. Several of the register bits must be set to a low ‘0’. The timing sequence to write to the status register is shown below, followed by the organization of the status register. WRITE Status Register Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 Instruction 0 SI 0 0 0 10 11 12 13 14 15 1 0 Status Register Data In 0 0 0 7 1 6 5 4 3 2 High-Z SO Status Register - Data to Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode Reserved Hold Function 0 0 = Word Mode Must = 0 0 = Hold (Default) (Default) 1 = No Hold 1 0 = Page Mode 0 1 = Burst Mode 1 1 = Reserved Rev. K | Page 11 of 15 | www.onsemi.com N64S830HA READ Status Register Instruction (RDSR) This instruction provides the ability to read the programmable bits of the Status Register. These register bits may be read at any time by performing the following timing sequence. Bits 0, 6 and 7 contain the data for the functional operation and Bit 1 will read data type ‘1’ for the 64Kb device. READ Status Register Instruction (RDSR) CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 0 0 0 0 1 0 0 1 Status Register Data Out SO High-Z 7 6 5 4 3 2 1 0 Status Register Bit 7 Bit 6 Mode Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 1 = 64Kb Hold Function 0 0 = Word Mode 0 = Hold 1 0 = Page Mode 1 = No Hold 0 1 = Burst Mode 1 1 = Reserved Power-Up State The serial SRAM enters a know state at power-up time. The device is in low-power standby state with CS = 1. A low level on CS is required to enter a active state. Rev. K | Page 12 of 15 | www.onsemi.com N64S830HA 8-Lead Plastic Small Outline, 150mil SOIC E E1 p D α B A2 A1 h 45o c φ β L Parameter Sym Min Nom Max Pin Pitch p Overall height A 1.35 1.27 1.55 1.75 Molded Package Thickness A2 1.32 1.42 1.55 0.25 Standoff A1 0.10 0.18 Overall Width E 5.79 6.02 6.20 Molded Package Width E1 3.71 3.91 3.99 Overall Length D 4.80 4.90 5.00 Chamfer Distance h 0.25 0.38 0.51 Foot Length L 0.48 0.62 0.76 Foot Angle φ 0 4 8 Lead Thickness c 0.20 0.23 0.25 Lead Width B 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 Mold Draft Angle Bottom β 0 12 15 Note: 1. All dimensions in Millimeters 2. Package dimensions exclude mold flash and protusions. Rev. K | Page 13 of 15 | www.onsemi.com A N64S830HA 8-Lead Plastic Thin Shrink Small Outline, 4.4 mm TSSOP E E1 p D B α A2 A1 c φ β L Parameter Sym Min Nom Max Pin Pitch p Overall height A 0.65 Molded Package Thickness A2 0.85 0.90 0.95 0.15 1.10 Standoff A1 0.05 0.10 Overall Width E 6.25 6.38 6.50 Molded Package Width E1 4.30 4.40 4.50 Overall Length D 2.90 3.00 3.10 Foot Length L 0.50 0.60 0.70 Foot Angle φ 0 4 8 Lead Thickness c 0.09 0.15 0.20 Lead Width B 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 Mold Draft Angle Bottom β 0 5 10 Note: 1. All dimensions in Millimeters 2. Package dimensions exclude mold flash and protusions. Rev. K | Page 14 of 15 | www.onsemi.com A N64S830HA Ordering Information Part Number Package Shipping Method N64S830HAS22I 8-Pin SOIC (RoHS Compliant) Tray N64S830HAT22I 8-Pin TSSOP (RoHS Compliant) Tray N64S830HAS22IT 8-Pin SOIC (RoHS Compliant) Tape & Reel N64S830HAT22IT 8-Pin TSSOP (RoHS Compliant) Tape & Reel Revision History Revision # Date A October 2005 Change Description Initial advance release B January 2006 Separated density, removed write protection and added page and burst modes C January 2006 Changed packages to green type D January 2006 Changed TSSOP pinout to match SOIC E September 2006 Split x8 and x16 devices Converted to AMI Semiconductor F May 2007 G October 2007 Updated DC parameters Maximum frequency changed to 16MHz for 1.8V device H January 2008 Removed ADVANCE from datasheet Changed AMIS address Change to Status Register Bit #1 - must be set to ‘1’ I July 2008 J September 2008 K June 2009 Converted to ON Semiconductor and new part numbers Change to WRITE Status Register Bit #1 - must be set to ‘0’ Change to READ Status Register Updated Operating Characteristics - minimum operating voltge = 2.5V ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor PO Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East & Africa Technical Support: Phone 421-33-790-2910 Japan Customer Focus Center: Phone 81-3-5773-3850 Rev. K | Page 15 of 15 | www.onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative