FAIRCHILD NC7WZ00K8X_NL

Revised February 2005
NC7WZ00
TinyLogic£ UHS Dual 2-Input NAND Gate
General Description
Features
The NC7WZ00 is a dual 2-Input NAND Gate from
Fairchild's Ultra High Speed Series of TinyLogic£. The
device is fabricated with advanced CMOS technology to
achieve ultra high speed with high output drive while maintaining low static power dissipation over a broad VCC operating range. The device is specified to operate over the
1.65V to 5.5V VCC operating range. The inputs and output
are high impedance when VCC is 0V. Inputs tolerate voltages up to 7V independent of VCC operating voltage.
■ Space saving US8 surface mount package
■ MicroPak¥ Pb-Free leadless package
■ Ultra High Speed; tPD 2.4 ns typ into 50 pF at 5V VCC
■ High Output Drive; r24 mA at 3V VCC
■ Broad VCC Operating Range; 1.65V–5.5V
■ Matches the performance of LCX when operated at
3.3V VCC
■ Power down high impedance inputs/output
■ Overvoltage tolerant inputs facilitate 5V to 3V translation
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Product
Order
Package
Code
Number
Number
Top Mark
Package Description
NC7WZ00K8X
MAB08A
WZ00
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm
Wide
NC7WZ00K8X_NL
(Note 1)
MAB08A
WZ00
Pb-Free 8-Lead US8, JEDEC MO-187, Variation CA 3k Units on Tape and Reel
3.1mm Wide
NC7WZ00L8X
MAC08A
N6
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
Supplied As
3k Units on Tape and Reel
5k Units on Tape and Reel
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.
TinyLogic£ is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500267
www.fairchildsemi.com
NC7WZ00 TinyLogic£ UHS Dual 2-Input NAND Gate
April 2000
NC7WZ00
Logic Symbol
Connection Diagrams
IEEE/IEC
(Top View)
Pin Descriptions
Pin Names
Pin One Orientation Diagram
Description
An , Bn
Inputs
Yn
Output
Function Table
AAA represents Product Code Top Mark - see ordering code
Y
Inputs
A
H
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
AB
Output
B
L
L
H
L
H
H
H
L
H
H
H
HIGH Logic Level
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L
Pad Assignments for MicroPak
Y
L
LOW Logic Level
(Top Thru View)
2
Recommended Operating
Conditions (Note 3)
0.5V to 7V
0.5V to 7V
0.5V to 7V
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Supply Voltage Operating (VCC)
1.65V to 5.5V
Supply Voltage Data Retention (VCC)
DC Input Diode Current (IIK)
1.5V to 5.5V
Input Voltage (VIN)
@VIN 0.5V
50 mA
0V to 5.5V
Output Voltage (VOUT)
DC Output Diode Current (IOK)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
@VOUT 0.5V
50 mA
r 50 mA
DC Output Current (IOUT)
DC VCC/GND Current (ICC/IGND)
Storage Temperature (TSTG)
Junction Temperature under Bias (TJ)
Input Rise and Fall Time (tr, tf)
r 100 mA
65qC to 150qC
150qC
VCC @ 1.65V r 0.15V, 2.5V r 0.2V
0 ns/V to 20 ns/V
VCC @ 3.3V r 0.3V
0 ns/V to 10 ns/V
VCC @ 5.0V r 0.5V
0 ns/V to 5 ns/V
Thermal Resistance (TJA)
250qC/W
Junction Lead Temperature (TL);
260qC
(Soldering, 10 seconds)
Power Dissipation (PD) @ 85qC
250 mW
Note 2: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
IIN
Input Leakage Current
IOFF
Power Off Leakage Current
ICC
Quiescent Supply Current
TA
VCC
(V)
Min
25qC
Typ
TA
Max
40qC to 85qC
Min
1.65 - 1.95
0.75 VCC
0.75 VCC
2.3 - 5.5
0.70 VCC
0.70 VCC
Max
0.25 VCC
0.25 VCC
2.3 - 5.5
0.30 VCC
0.30 VCC
1.55
1.65
1.55
2.3
2.2
2.3
2.2
3.0
2.9
3.0
2.9
Conditions
V
1.65 - 1.95
1.65
Units
V
V
VIN
100 PA
VIL IOH
4.5
4.4
4.5
4.4
1.65
1.29
1.52
1.69
IOH
4 mA
2.3
1.9
2.15
1.9
IOH
8 mA
3.0
2.4
2.80
2.4
IOH
16 mA
3.0
2.3
2.68
2.3
IOH
24 mA
4.5
3.8
4.20
3.8
IOH
32 mA
V
1.65
0.0
0.1
0.1
2.3
0.0
0.1
0.1
3.0
0.0
0.1
0.1
V
VIN
VIH IOL
100 PA
4.5
0.0
0.1
0.1
1.65
0.08
0.24
0.24
IOL
2.3
0.10
0.3
0.3
IOL
8 mA
3.0
0.15
0.4
0.4
IOL
16 mA
3.0
0.22
0.55
0.55
IOL
24 mA
4.5
0.22
0.55
0.55
IOL
32 mA
r0.1
r1.0
PA
VIN
0 - 5.5
V
5.5V, GND
0.0
1
10
PA
VIN or VOUT
1.65 - 5.5
1
10
PA
VIN
3
4 mA
5.5V
5.5V, GND
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NC7WZ00
Absolute Maximum Ratings(Note 2)
NC7WZ00
AC Electrical Characteristics
Symbol
tPLH,
Parameter
Propagation Delay
tPHL
Propagation Delay
tPLH,
tPHL
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
VCC
TA
25qC
(V)
Min
Typ
1.8 r 0.15
2.0
2.5 r 0.2
1.2
3.3 r 0.3
TA
40qC to 85qC
Max
Min
Max
5.3
9.6
2.0
9.8
3.2
5.3
1.2
5.7
0.8
2.4
3.7
0.8
4.0
5.0 r 0.5
0.5
1.9
2.9
0.5
3.2
3.3 r 0.3
1.2
3.0
4.6
1.2
4.9
5.0 r 0.5
0.8
2.4
3.6
0.8
3.9
0
2.5
3.3
13
5.0
17
Units
ns
ns
Conditions
CL
15 pF,
RL
1 M:
CL
50 pF,
RL
500:
Figure
Number
Figures
1, 3
Figures
1, 3
pF
pF
(Note 4)
Figure 2
Note 4: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression:
ICCD (CPD)(VCC)(fIN) (ICCstatic).
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR
1.0 MHz; tw
500 ns
FIGURE 1. AC Test Circuit
FIGURE 3. AC Waveforms
Input
AC Waveform; tr
tf
PRR
10 MHz; Duty Cycle
1.8 ns;
50%
FIGURE 2. ICCD Test Circuit
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4
Tape Format
Package
Designator
Tape
Number
Cavity
Section
Cavities
Status
Status
125 (typ)
Empty
Sealed
Leader (Start End)
K8X
Carrier
Trailer (Hub End)
Cover Tape
3000
Filled
Sealed
75 (typ)
Empty
Sealed
Cover Tape
TAPE DIMENSIONS inches (millimeters)
TAPE FORMAT for MicroPak
Package
Designator
L8X
Tape
Number
Cavity
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
5
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NC7WZ00
Tape and Reel Specification
NC7WZ00
Tape and Reel Specification
(Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
8 mm
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165
0.331 0.059/0.000
0.567
W1 0.078/0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40 1.50/0.00)
(14.40)
(W1 2.00/1.00)
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NC7WZ00
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
7
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NC7WZ00 TinyLogic£ UHS Dual 2-Input NAND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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8