NLSF595 Serial (SPI) Tri−Color LED Driver The NLSF595 is advanced CMOS shift register with open drain outputs fabricated with 0.6 mm silicon gate CMOS technology. This device is used in conjunction with a microcontroller, with only one dedicated line. All pins have Overvoltage Protection that allows voltages above VCC up to 7.0 V to be present on the pins without damage or disruption of operation of the part, regardless of the operating voltage. This device may be used between 2.0 and 5.5 volts, the output driver level may be independent of supply voltage: 0−7.0 volts. Features • Parallel Outputs are Open Drain Capable of Sinking > 12 mA • • • • • • • • • • • • • • • • • Output Withstands up to +7.0 Regardless of VCC Standard Serial (SPI) Interface, Data, Clock, Enable (Low) All Inputs CMOS Level Compatible Frees up I/O around a Microcontroller Only One Pin Dedicated to this Device (Latch Enable) Output Enable may be Permanently Pulled Low High Speed Clocking, Fmax > 25 MHz (Shift Clock) Eight Bits Parallel Output Double Buffered Outputs, so Register may Fill without Affecting Output STD CMOS Serial Output, may be used to Cascade more than One Device Each Part Controls Two Tri−Color LEDs Two Devices can Control 5 Tri−Color LEDs Low Leakage: ICC = 2.0 mA (Max) at TA = 25°C Latchup Performance Exceeds 100 mA QFN−16/TSSOP−16 Packages ESD Performance: Human Body Model; > 2000 V, Machine Model; > 200 V Functionally Similar to the Popular 74VHC595 Pb−Free Packages are Available © Semiconductor Components Industries, LLC, 2005 July, 2005 − Rev. 8 1 http://onsemi.com MARKING DIAGRAMS 16 1 SF 595 ALYW QFN−16 MN SUFFIX CASE 485G (Top View) 9 16 16 NLSF 595 ALYW 1 TSSOP−16 DT SUFFIX CASE 948F A L Y W 1 8 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Publication Order Number: NLSF595/D NLSF595 EN3 OE RSK C2 SRG8 R SCLR SCK C/1 QB 1 16 VCC QC 2 15 QA QD 3 14 SI QE 4 13 OE QD QF 5 12 RCK QE QG 6 11 SCK QH 7 10 SCLR GND 8 9 SI 3 QA QB QC QF QG 2D 3 QH SQH SQH Figure 1. Pin Assignment (TSSOP−16) Figure 2. IEC Logic Symbol QC QB VCC QA QD 2D 1D 16 15 14 13 1 12 SI (Serial Data Input) QE 2 NLSF595 MN Package 11 OE QF 3 (Top View) 10 RCK (Register Clock) QG 4 9 5 6 8 7 SCLR (reset) SQH GND QH Figure 3. Pin Assignment (QFN−16) http://onsemi.com 2 SCK (Shift Clock) NLSF595 OE RCK OVT QA SI D Q D SRA Q STRA OVT R QB Q D D SRB Q STRB OVT R QC Q D D SRC Q STRC OVT R QD Q D D SRD STRD OVT R QE Q D D SRE Q STRE OVT R QF Q D D SRF Q STRF OVT R QG Q D D SRG Q STRG OVT R QH Q D SRH SCK PARALLEL DATA OUTPUTS Q D Q STRH R SCLR SQH Figure 4. Expanded Logic Diagram http://onsemi.com 3 NLSF595 MAXIMUM RATINGS Symbol Value Unit VCC Positive DC Supply Voltage −0.5 to +7.0 V VIN Digital Input Voltage −0.5 to +7.0 V VOUT DC Output Voltage −0.5 to VCC +7.0 V IIK Input Diode Current −20 mA IOK Output Diode Current $50 mA IOUT DC Output Current, per Pin +50 mA ICC DC Supply Current, VCC and GND Pins $75 mA PD Power Dissipation in Still Air 450 mW TSTG Storage Temperature Range −65 to +150 °C $300 mA 128 °C/W ILATCHUP qJA Parameter Latchup Performance Above VCC and Below GND at 125°C (Note 1) Thermal Resistance, Junction−to−Ambient Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit 2.0 5.5 V VCC DC Supply Voltage VIN DC Input Voltage 0 5.5 V DC Output Voltage 0 VCC V −55 125 °C 0 50 15 ns/V VOUT TA Operating Temperature Range, all Package Types tr, tf Input Rise or Fall Time VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V FUNCTION TABLE Inputs Operation Reset (SCLR) Resulting Function Serial Input (SI) Shift Clock (SCK) Reg Clock (RCK) Output Enable (OE) Shift Register Contents Storage Register Contents Serial Output (SQH) Parallel Outputs (QA − QH) Clear shift register L X X L, H, ↓ L L U L U Shift data into shift register H D ↑ L, H, ↓ L D→SRA; SRN→SRN+1 U SRG→SRH U Registers remains unchanged H X L, H, ↓ X L U ** U ** Transfer shift register contents to storage register H X L, H, ↓ ↑ L U SRN³STRN * SRN Storage register remains unchanged X X X L, H, ↓ L * U * U Enable parallel outputs X X X X L * ** * Enabled Force outputs into high impedance state X X X X H * ** * Z SR = shift register contents STR = storage register contents D = data (L, H) logic level U = remains unchanged ↓ = High−to−Low ↑ = Low−to−High http://onsemi.com 4 * = depends on Reset and Shift Clock inputs ** = depends on Register Clock input NLSF595 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min 1.5 2.1 3.15 3.85 VIH Minimum High−Level Input Voltage 2.0 3.0 4.5 5.5 VIL Maximum Low−Level Input Voltage 2.0 3.0 4.5 5.5 VOH Minimum High−Level Serial Output Only Output Voltage VIN = VIH or VIL 2.0 3.0 4.5 1.9 2.9 4.4 VIN = VIH or VIL IOH = −4 mA IOH = −8 mA 3.0 4.5 2.58 3.94 2.0 3.0 4.5 IOL = 4 mA IOL = 8 mA 3.0 4.5 Maximum Low−Level Output Voltage with Max. Load VIN = VIH or VIL IOL = 20 mA IOL = 25 mA 3.0 4.5 IIN Maximum Input Leakage Current VIN = 5.5 V or GND ICC Maximum Quiescent Supply Current IOZ Maximum Low−Level Output Voltage VIN = VIH or VIL Typ Max TA = ≤ 85°C TA = ≤ 125°C Min Min Max 1.5 2.1 3.15 3.85 0.59 0.9 1.35 1.65 VIN = VIH or VIL IOH = − 50 mA IOL = 50 mA VOL TA = 25°C VCC (V) 2.0 3.0 4.5 1.5 2.1 3.15 3.85 0.59 0.9 1.35 1.65 V 0.59 0.9 1.35 1.65 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.80 2.34 3.66 Unit V V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.36 0.36 0.44 0.44 0.52 0.52 1.0 0.6 1.1 0.7 1.25 0.8 V 0 to 5.5 $0.1 ±1.0 $1.0 mA VIN = VCC or GND 5.5 4.0 40.0 40.0 mA Three−State Output Off−State Current QA−QH VIN = VIH or VIL VOUT = VCC or GND 5.5 ±0.25 ±2.5 $2.5 mA ILKG Active (2) State Off Output Leakage Current QA−QH VIN = VIH or VIL VOUT = VCC or GND 5.5 ±0.25 ±2.5 $2.5 mA IOFF Power Off Output Leakage All Outputs VIN = 0 or 5.5 V VOUT = 5.5 V 0 ±0.25 ±2.5 $2.5 mA VOL2 http://onsemi.com 5 0.0 0.0 0.0 Max 0.8 0.5 NLSF595 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ Î ÎÎ Î ÎÎÎ Î ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25°C Symbol fmax tPLH, tPHL tPHL tPLZ tPZL tPZL tPLZ CIN COUT Parameter Test Conditions Min Typ Max TA = ≤ 85°C TA = ≤ 125°C Min Min Max Max Unit Maximum Clock Frequency (50% Duty Cycle) VCC = 3.3 $ 0.3 V 80 150 70 70 VCC = 5.0 ± 0.5 V 135 185 115 115 Propagation Delay, SCK to SQH VCC = 3.3 $ 0.3 V CL = 15 pF CL = 50 pF 8.8 11.3 13.0 16.5 1.0 1.0 15.0 18.5 1.0 1.0 15.0 18.5 VCC = 5.0 $ 0.5 V CL = 15 pF CL = 50 pF 6.2 7.7 8.2 10.2 1.0 1.0 9.4 11.4 1.0 1.0 9.4 11.4 VCC = 3.3 $ 0.3 V CL = 15 pF CL = 50 pF 8.4 10.9 12.8 16.3 1.0 1.0 13.7 17.2 1.0 1.0 13.7 17.2 VCC = 5.0 $ 0.5 V CL = 15 pF CL = 50 pF 5.9 7.4 8.0 10.0 1.0 1.0 9.1 11.1 1.0 1.0 9.1 11.1 Output Disable Time RCK to QA−QH Output Enable Time RCK to QA−QH VCC = 3.3 $ 0.3 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 7.7 10.2 5.4 6.9 11.9 15.4 7.4 9.4 1.0 1.0 1.0 1.0 13.5 17.0 8.5 10.5 1.0 1.0 1.0 1.0 13.5 17.0 8.5 10.5 ns Output Disable Time RCK to QA−QH Output Enable Time RCK to QA−QH VCC = 3.3 $ 0.3 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 7.7 10.2 5.4 6.9 11.9 15.4 7.4 9.4 1.0 1.0 1.0 1.0 13.5 17.0 8.5 10.5 1.0 1.0 1.0 1.0 13.5 17.0 8.5 10.5 ns Output Enable Time, OE to QA−QH VCC = 3.3 $ 0.3 V RL = 1 kW CL = 15 pF CL = 50 pF 7.5 9.0 11.5 15.0 1.0 1.0 13.5 17.0 1.0 1.0 13.5 17.0 ns VCC = 5.0 $ 0.5 V RL = 1 kW CL = 15 pF CL = 50 pF 4.8 8.3 8.6 10.6 1.0 1.0 10.0 12.0 1.0 1.0 10.0 12.0 VCC = 3.3 $ 0.3 V RL = 1 kW CL = 50 pF 12.1 15.7 1.0 16.2 1.0 16.2 VCC = 5.0 $ 0.5 V RL = 1 kW CL = 50 pF 7.6 10.3 1.0 11.0 1.0 11.0 Input Capacitance 4 10 Three−State Output Capacitance (Output in High−Impedance State), QA−QH 6 Propagation Delay, SCLR to SQH Output Disable Time, OE to QA−QH VCC = 5.0 $ 0.5 V VCC = 5.0 $ 0.5 V MHz ns ns ns 10 10 pF 10 10 pF Typical @ 25°C, VCC = 5.0 V CPD 87 Power Dissipation Capacitance (Note 2) pF 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25°C Symbol Characteristic Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.8 1.0 V VOLV Quiet Output Minimum Dynamic VOL −0.8 −1.0 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V http://onsemi.com 6 NLSF595 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (Input tr = tf = 3.0ns) Symbol tsu Parameter VCC V TA = 25°C Typ TA = − 40 to 85°C TA = − 55 to 125°C Limit Limit Limit Unit Setup Time, SI to SCK 3.3 5.0 3.5 3.0 3.5 3.0 3.5 3.0 ns tsu(H) Setup Time, SCK to RCK 3.3 5.0 8.0 5.0 8.5 5.0 8.5 5.0 ns tsu(L) Setup Time, SCLR to RCK 3.3 5.0 8.0 5.0 9.0 5.0 9.0 5.0 ns Hold Time, SI to SCK 3.3 5.0 1.5 2.0 1.5 2.0 1.5 2.0 ns th(L) Hold Time, SCLR to RCK 3.3 5.0 0 0 0 0 1.0 1.0 ns trec Recovery Time, SCLR to SCK 3.3 5.0 3.0 2.5 3.0 2.5 3.0 2.5 ns tw Pulse Width, SCK or RCK 3.3 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns Pulse Width, SCLR 3.3 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns th tw(L) http://onsemi.com 7 NLSF595 2.7 V +5.0 V 220 W SCLR Red OE 2.7 V Green NLSF595 Blue Data I/O or SPI (MISO) SI Clock SCK 5 Additional Outputs EN RCK SQH Serial Data Out MCU NLSF595 8 Additional Outputs Total of 5 3−Color Displays 16 VCC QC 2 15 QA QD 3 QE 4 QF 5 QG 6 NLSF595DTR2 QB 1 QH 7 14 SI 13 OE 12 RCK 11 SCK 10 SCLR GND 8 9 SQH Figure 5. NLSF595 Shown Driving 5 3−Color LEDs http://onsemi.com 8 NLSF595 SWITCHING WAVEFORMS tw VCC 50% SCK GND tw SQH GND tPHL 1/fmax tPLH 50% VCC SQH tPHL trec 50% VCC 50% QA−QH 50% OE tPZL tPZL 50% VCC QA−QH VOL +0.3 V VOL +0.3V VCC GND VALID tsu VCC 50% SCK VCC 50% GND tsu(H) GND th 50% RCK VCC 50% SCK or RCK HIGH IMPEDANCE Figure 9. 50% SI GND tPLZ 50% VCC Figure 8. SCLR VCC 50% GND VOL +0.3 V GND Figure 7. VCC tPLZ VCC 50% SCK Figure 6. RCK VCC 50% SCLR GND tw GND Figure 10. VCC Figure 11. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 12. Figure 13. http://onsemi.com 9 NLSF595 SCK SI SCLR RCK OE QA QB QC QD QE QF QG QH SQH NOTE: output is in a high−impedance state. Figure 14. Timing Diagram INPUT Figure 15. Input Equivalent Circuit http://onsemi.com 10 NLSF595 LED DATA QA ON 0 QB OFF 1 QC OFF 1 QD OFF 1 QE ON 0 QF ON 0 QG OFF 1 QH ON 0 Data must be valid at the time of the positive edge. Data Duty Cycle Not Important Clock 250 ns See Data Sheet for Pinout +2.5 V QA QB For Cascading Devices Data Clock EN QC SQH QD QE SI SCK RCK QF QG OE QH Figure 16. NLSF595 Example http://onsemi.com 11 +5.0 V NLSF595 ORDERING INFORMATION Device Nomenclature Circuit Indicator Technology Device Function Package Suffix Tape & Reel Suffix Package Shipping† NLSF595MNR2 NL SF 595 MN R2 QFN 13−inch/2500 Unit NLSF595MNR2G NL SF 595 MN R2 QFN (Pb−Free) 13−inch/2500 Unit NLSF595DTR2 NL SF 595 DT R2 TSSOP* (Pb−Free) 13−inch/2500 Unit Device Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 12 NLSF595 PACKAGE DIMENSIONS QFN−16 MN SUFFIX CASE 485G−01 ISSUE B D PIN 1 LOCATION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B ÇÇ ÇÇ E DIM A A1 A3 b D D2 E E2 e K L 0.15 C TOP VIEW 0.15 C D2 16X e L 5 NOTE 5 EXPOSED PAD 8 4 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 −−− 0.30 0.50 9 E2 16X K 12 1 0.05 C 13 A b 0.10 C A B (A3) 0.10 C 16 16X e 16 X BOTTOM VIEW 0.08 C SIDE VIEW NOTE 3 SOLDERING FOOTPRINT* 0.575 0.022 3.25 0.128 0.30 0.012 EXPOSED PAD 1.50 0.059 3.25 0.128 0.50 0.02 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 A1 SEATING PLANE C NLSF595 PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E G ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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