MC74VHCT541A Octal Bus Buffer The MC74VHCT541A is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHCT541A is a noninverting, 3−state, buffer/line driver/line receiver. When either OE1 or OE2 is high, the terminal outputs are in the high impedance state. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The VHCT541A input and output (when disabled) structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage−input/output voltage mismatch, battery backup, hot insertion, etc. http://onsemi.com MARKING DIAGRAMS 20 SOIC−20WB SUFFIX DW CASE 751D 1 VHCT541A AWLYYWWG 1 Features • • • • • • • • • • • • High Speed: tPD = 5.4 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 V to 5.5 V Operating Range Low Noise: VOLP = 1.6 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 134 FETs or 33.5 Equivalent Gates Pb−Free Packages are Available* 20 1 VHCT 541A ALYWG G TSSOP−20 SUFFIX DT CASE 948E 1 20 74VHCT541 AWLYWWG SOEIAJ−20 SUFFIX M CASE 967 1 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs Output Y *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 4 1 OE1 OE2 A L L H X L L X H L H X X L H Z Z ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Publication Order Number: MC74VHCT541A/D MC74VHCT541A A1 A2 A3 DATA INPUTS A4 A5 A6 A7 A8 OUTPUT ENABLES OE1 OE2 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Y1 Y2 Y3 Y4 NONINVERTING OUTPUTS Y5 Y6 Y7 Y8 OE1 1 20 VCC A1 2 19 OE2 A2 3 18 Y1 A3 4 17 Y2 A4 5 16 Y3 A5 6 15 Y4 A6 7 14 Y5 A7 8 13 Y6 A8 9 12 Y7 10 11 Y8 GND 1 Figure 2. Pin Assignment 19 Figure 1. Logic Diagram ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage Parameter – 0.5 to + 7.0 V Vin DC Input Voltage – 0.5 to + 7.0 V Vout DC Output Voltage – 0.5 to + 7.0 – 0.5 to VCC + 0.5 V IIK Input Diode Current − 20 mA IOK Output Diode Current (VOUT < GND; VOUT > VCC) ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 _C Outputs in 3−State High or Low State SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating − SOIC Packages: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage Vin DC Input Voltage Vout DC Output Voltage TA Operating Temperature tr, tf Input Rise and Fall Time Outputs in 3−State High or Low State VCC =5.0V ±0.5V http://onsemi.com 2 Min Max Unit 4.5 5.5 V 0 5.5 V 0 0 5.5 VCC V − 40 + 85 _C 0 20 ns/V MC74VHCT541A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ DC ELECTRICAL CHARACTERISTICS Test Conditions TA = 25°C VCC V Min 2.0 Symbol Parameter VIH Minimum High−Level Input Voltage 4.5 to 5.5 VIL Maximum Low−Level Input Voltage 4.5 to 5.5 VOH Minimum High−Level Output Voltage Vin = VIH or VIL IOH = − 50mA 4.5 4.4 IOH = − 8mA 4.5 3.94 VOL Maximum Low−Level Output Voltage Vin = VIH or VIL IOL = 50mA 4.5 IOL = 8mA Iin Maximum Input Leakage Current IOZ Typ TA = − 40 to 85°C Max Min Max 2.0 V 0.8 0.8 4.5 Unit 4.4 V V 3.80 0.0 0.1 0.1 V 4.5 0.36 0.44 Vin = 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0 mA Maximum 3−State Leakage Current Vin = VIL or VIH Vout = VCC or GND 5.5 ± 0.25 ± 2.5 mA ICC Maximum Quiescent Supply Current Vin = VCC or GND 5.5 4.0 40.0 mA ICCT Quiescent Supply Current Per Input: VIN = 3.4V Other Input: VCC or GND 5.5 1.35 1.50 mA IOPD Output Leakage Current VOUT = 5.5V 0 0.5 5.0 mA AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Symbol Parameter Test Conditions Min TA = − 40 to 85°C Typ Max Min Max Unit tPLH, tPHL Maximum Propagation Delay, A to Y VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 5.0 5.5 6.9 7.9 1.0 1.0 8.0 9.0 ns tPZL, tPZH Output Enable TIme, OE to Y VCC = 5.0 ± 0.5V RL = 1kW CL = 15pF CL = 50pF 8.3 8.8 11.3 12.3 1.0 1.0 13.0 14.0 ns tPLZ, tPHZ Output Disable Time, OE to Y VCC = 5.0 ± 0.5V RL = 1kW CL = 50pF 9.4 11.9 1.0 13.5 ns Output to Output Skew VCC = 5.0 ± 0.5V (Note 1) CL = 50pF 1.0 1.0 ns 10 10 pF tOSLH, tOSHL Cin Maximum Input Capacitance 4 Cout Maximum 3−State Output Capacitance (Output in High Impedance State) 9 pF Typical @ 25°C, VCC = 5.0V CPD 19 Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25°C Symbol Parameter Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 1.2 1.6 V VOLV Quiet Output Minimum Dynamic VOL −1.2 −1.6 V VIHD Minimum High Level Dynamic Input Voltage 2.0 V VILD Maximum Low Level Dynamic Input Voltage 0.8 V http://onsemi.com 3 MC74VHCT541A ORDERING INFORMATION Package Shipping † MC74VHCT541ADW SOIC−20WB 38 Units / Rail MC74VHCT541ADWG SOIC−20WB (Pb−Free) 38 Units / Rail MC74VHCT541ADWR2 SOIC−20WB 1000 / Tape & Reel MC74VHCT541ADWRG SOIC−20WB (Pb−Free) 1000 / Tape & Reel MC74VHCT541ADT TSSOP−20* 75 Units / Rail MC74VHCT541ADTG TSSOP−20* 75 Units / Rail MC74VHCT541ADTR2 TSSOP−20* 2500 / Tape & Reel MC74VHCT541ADTRG TSSOP−20* 2500 / Tape & Reel MC74VHCT541AMEL SOEIAJ−20 2000 / Tape & Reel MC74VHCT541AMELG SOEIAJ−20 (Pb−Free) 2000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. 3V A 3V 1.5V tPLH tPHL Y OE1 or OE2 GND Y Y Figure 3. Switching Waveform HIGH IMPEDANCE 1.5V tPZH VOL GND tPLZ tPZL VOH 1.5V VOL +0.3V tPHZ VOH −0.3V 1.5V HIGH IMPEDANCE Figure 4. Switching Waveform TEST POINT TEST POINT OUTPUT OUTPUT DEVICE UNDER TEST 1.5V DEVICE UNDER TEST C L* *Includes all probe and jig capacitance 1 kW C L* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 5. Test Circuit Figure 6. Test Circuit http://onsemi.com 4 MC74VHCT541A PACKAGE DIMENSIONS SOIC−20 WB DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h 1 10 20X DIM A A1 B C D E e H h L q B B 0.25 M T A B S S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D e 18X MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SEATING PLANE A1 C T TSSOP−20 D5 SUFFIX CASE 948E−02 ISSUE B 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 J J1 B L −U− PIN 1 IDENT SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING PLANE http://onsemi.com 5 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74VHCT541A PACKAGE DIMENSIONS SOEIAJ−20 M SUFFIX CASE 967−01 ISSUE A 20 LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D VIEW P e A c 0.13 (0.005) DIM A A1 b c D E e HE L LE M Q1 Z A1 b M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.81 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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