PicoGuard XS® ESD Clamp Array For High Speed Data Line Protection CM1233 Features • • • • • • • • ESD protection for 4 pairs of differential channels ESD protection to IEC61000-4-2 Level 4 at ±8kV contact discharge Pass-through impedance matched clamp architecture Flow-through routing for high-speed signal integrity Minimal line capacitance change with temperature and voltage 100Ω matched impedance for each paired differential channel Each I/O pin can withstand over 1000 ESD strikes* RoHS compliant (lead-free) TDFN-16 package Applications • • DVI ports, HDMI ports in notebooks, set top boxes, digital TVs, LCD displays General purpose high-speed data line ESD protection ©2010 SCILLC. All rights reserved. April 2010 – Rev. 2 Product Description The PicoGuard XS (eXtreme Speed) protection family is specifically designed for next generation deep sub-micron high speed data line protection. The CM1233 is ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading and tightly controlled signal skews (with channel-to-channel matching at 2% max deviation). The device is particularly well-suited for protecting systems using high-speed ports such as DVI or HDMI, along with corresponding ports in removable storage, digital camcorders, DVD-RW drives and other applications where extremely low loading capacitance with ESD protection are required. The CM1233 also features easily routed "passthrough" pinouts in a RoHS compliant (lead-free),16lead TDFN, small footprint package. Publication Order Number: CM1233/D CM1233 *Standard test condition is IEC61000-4-2 level 4 test circuit with each pin subjected to ±8kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. PicoGuard XS ESD Protection Architecture Conceptually, an ESD protection device performs the following actions upon an ESD strike discharge into a protected ASIC (see Figure 1): 1. When an ESD potential is applied to the system under test (contact or air-discharge), Kirchoff’s Current Law (KCL) dictates that the Electrical Overstress (EOS) currents will immediately divide throughout the circuit, based on the dynamic impedance of each path. 2. Ideally, the classic shunt ESD clamp will switch within 1ns to a low-impedance path and return the majority of the EOS current to the chassis shield/reference ground. In actuality, if the ESD component's response time (tCLAMP) is slower than the ASIC it is protecting, or if the Dynamic Clamping Resistance (RDYN) is not significantly lower than the ASIC's I/O cell circuitry, then the ASIC will have to absorb a large amount of the EOS energy, and be more likely to fail. 3. Subsequent to the ESD/EOS event, both devices must immediately return to their original specifications, and be ready for an additional strike. Any deterioration in parasitics or clamping capability should be considered a failure, since it can then affect signal integrity or subsequent protection capability. (This is known as "multistrike" capability.) Rev. 2 | Page 2 of 13 | www.onsemi.com CM1233 In the CM1233 PicoGuard XS architecture, the signal line leading the connector to the ASIC routes through the CM1233 chip which provides 100Ω matched differential channel characteristic impedance that helps optimize 100Ω load impedance applications such as the HDMI high speed data lines. Note:When each of the channels are used individually for single-ended signal lines protection, the individual channel provides 50Ω characteristic impedance matching. The load impedance matching feature of the CM1233 helps to simplify system designer’s PCB layout considerations in impedance matching and also eliminates associated passive components. The route through the PicoGuard XS architecture enables the CM1233 to provide matched impedance for the signal path between the connector and the ASIC. Besides this function, this circuit arrangement also changes the way the parasitic inductance interacts with the ESD protection circuit and helps reduce the IRESIDUAL current to the ASIC. Figure 1. Standard ESD Protection Device Block Diagram Rev. 2 | Page 3 of 13 | www.onsemi.com CM1233 The PicoGuard XS Architecture Advantages Figure 2 illustrates a standard ESD protection device. The inductor element represents the parasitic inductance arising from the bond wire and the PCB trace leading to the ESD protection diodes. Figure 2. Standard ESD Protection Model Figure 3 illustrates one of the channels. Similarly, the inductor elements represent the parasitic inductance arising from the bond wire and PCB traces leading to the ESD protection diodes as well. Figure 3. CM1233 PicoGuard XS ESD Protection Model Rev. 2 | Page 4 of 13 | www.onsemi.com CM1233 CM1233 Inductor Elements In the CM1233 PicoGuard XS architecture, the inductor elements and ESD protection diodes interact differently compared to the standard ESD model. In the standard ESD protection device model, the inductive element presents high impedance against high slew rate strike voltage, i.e. during an ESD strike. The impedance increases the resistance of the conduction path leading to the ESD protection element. This limits the speed that the ESD pulse can discharge through the ESD protection element. In the PicoGuard XS architecture, the inductive elements are in series to the conduction path leading to the protected device. The elements actually help to limit the current and voltage striking the protected device. First the reactance of the inductive element, L1, on the connector side when an ESD strike occurs, acts in the opposite direction of the ESD striking current. This helps limit the peak striking voltage. Then the reactance of the inductive element, L2, on the ASIC side forces this limited ESD strike current to be shunted through the ESD protection diodes. At the same time, the voltage drop across both series element acts to lower the clamping voltage at the protected device terminal. Through this arrangement, the inductive elements also tune the impedance of the ESD protection element by cancelling the capacitive load presented by the ESD diodes to the signal line. This improves the signal integrity and makes the overall ESD protection device more transparent to the high bandwidth data signals passing through the channel. The innovative PicoGuard XS architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the ESD current strike to the protected device and also improves the signal integrity of the system by balancing the capacitive loading effects of the ESD diodes. At the same time, this architecture provides an impedance matched signal path for 50Ω loading applications. Board designs can take advantage of precision internal component matching for improved signal integrity, which is not otherwise possible with discrete components at the system level. This helps to simplify the PCB layout considerations by the system designer and eliminates the associated passive components for load matching that is normally required with standard ESD protection circuits. Each ESD channel consists of a pair of diodes in series which steer the positive or negative ESD current pulse to either the Zener diode or to ground. This embedded Zener diode also serves to eliminate the need for a separate bypass capacitor to absorb positive ESD strikes to ground. The CM1233 protects against ESD pulses up to ±8kV contact per the IEC 61000-4-2 standard. Rev. 2 | Page 5 of 13 | www.onsemi.com CM1233 PIN DESCRIPTIONS Pin Name Description 1 2 In_1+ In_1- Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) 3 4 In_2+ In_2- Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) 5 6 In_3+ In_3- Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) 7 8 In_4+ In_4- Bidrectional Clamp to ASIC (inside system) Bidrectional Clamp to ASIC (inside system) 9 10 Out_4Out_4+ Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) 11 12 Out_3Out_3+ Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) 13 14 Out_2Out_2+ Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) 15 16 Out_1Out_1+ Bidrectional Clamp to Connector (outside system) Bidrectional Clamp to Connector (outside system) PAD GND Ground return to shield Rev. 2 | Page 6 of 13 | www.onsemi.com CM1233 Ordering Information PART NUMBERING INFORMATION PIN PACKAGE ORDERING PART NUMBER (LEAD-FREE FINISH) PART MARKING 16 TDFN-16 CM1233-08DE CM1233-08 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS* PARAMETER Operating Temperature Range RATING -40 to +85 UNITS °C Storage Temperature Range Breakdown Voltage (Positive) -65 to +150 6 °C V *Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 2 | Page 7 of 13 | www.onsemi.com CM1233 ELECTRICAL OPERATING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VIN I/O Voltage Relative to GND IIN Continuous Current through signal pins (IN to OUT) 1000 Hr IF Channel Leakage Current TA = 25°C; VIN = 5V ESD Protection - Peak Discharge Voltage at any channel input, in system: Contact discharge per IEC 61000-4-2 Standard TA = 25°C VESD IRES Channel Clamp Voltage (Channel clamp voltage per IEC 61000-45 Standard) Positive Transients Negative Transients IPP = 1A, TA = 25°C, tP = 8/20µS Dynamic Resistance Positive Transients Negative Transients Zo ∆Zo Z CHANNEL ∆ZCHANNEL TYP MAX UNITS 5.5 V 100 IEC 61000-4-2 8kV; RDUP = 5Ω TA = 25°C; See Figure 6 RDYN MIN -0.5 Residual ESD Peak Current on RDUP (Resistance of Device Under Protection) VCL (SEE NOTE 1) ±0.1 mA ±1.0 µA kV ±8 3.2 A +10 –1.8 V V IPP = 1A, TA = 25ºC , tP = 8/20µS 0.9 0.55 Ω Ω Differential Channels pair characteristic impedance TR = 200ps 100 Ω Channel-to-Channel Impedance Match (Differential) TR = 200ps 2 % Individual Channel Characteristic Impedance in Single-ended Connection TR = 200ps 50 Ω Channel-to-Channel Impedance Match (Individual) TR = 200ps 2 % Note 1: All parameters specified at TA = –40°C to +85°C unless otherwise noted. Rev. 2 | Page 8 of 13 | www.onsemi.com CM1233 Performance Information Graphical Comparison and Test Setup Figure 4 shows that the CM1233 (PicoGuard XS ESD protector) lowers the peak voltage and clamping voltage by 45% across a wide range of loading conditions in comparison to a standard ESD protection device. Figure 5 also indicates that the DUP/ASIC protected by the CM1233 dissipates less energy than a standard ESD protection device. This data was derived using the test setups shown in Figure 6. Figure 4. VPeak (8KV IEC-61000 4-2 ESD Contact Strike) and VClamp vs. Loading (RDUP)* Figure 5. Energy Dissipated in DUP vs RDUP* * RDUP is the emulated Dynamic Resistance (load) of the Device Under Protection (DUP). See Figure 6. Rev. 2 | Page 9 of 13 | www.onsemi.com CM1233 Figure 6. Test Setups: Standard Device (Left) and CM1233 (Right) Figure 7. Typical Channel TDR Measured Across Out_x and In_x Per Each Differential Channels Pair (Typical 200ps Incident Rise Time) Rev. 2 | Page 10 of 13 | www.onsemi.com CM1233 Application Information CM1233 Application and Guidelines As a general rule, the CM1233 ESD protection array should be located as close as possible to the point of entry of expected electrostatic discharges with minimum PCB trace lengths to the ground planes and between the signal input and the ESD device to minimize stray series inductance. Figure 8. Application of Positive ESD Pulse Between Input Channel and Ground Figure 9. Typical PCB Layout Additional Information See also California Micro Devices Application Note AP209, “Design Considerations for ESD Protection,” in the Applications section at www.calmicro.com. Rev. 2 | Page 11 of 13 | www.onsemi.com CM1233 Mechanical Details TDFN-16 Mechanical Specifications, 0.75mm The 16-lead, 6.0x4.0mm, 0.75mm pitch TDFN package dimensions are presented below. PACKAGE DIMENSIONS Package TDFN JEDEC No. MO-229C Leads 16 * Millimeters Dim. Inches Min Nom Max Min Nom Max A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 A3 0.175 0.200 0.225 0.007 0.008 0.009 b 0.20 0.25 0.30 0.008 0.010 0.012 D 5.90 6.00 6.10 0.232 0.236 0.240 D2 5.05 5.10 5.15 0.199 0.201 0.203 E 3.90 4.00 4.10 0.153 0.157 0.161 E2 1.75 1.80 1.85 0.012 0.016 0.020 e 0.75 BSC 0.029 BSC K 0.70 REF 0.028 REF L # per tape and reel 0.35 0.40 0.45 0.014 0.016 0.018 3000 pieces Controlling dimension: millimeters * This package is compliant with JEDEC standard MO-229C with the exception of the D, D2, E, E2, K and L dimensions as called out in the table above. Dimensions for 16-Lead, 0.75mm pitch TDFN package Rev. 2 | Page 12 of 13 | www.onsemi.com CM1233 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Literature Distribution Center for ON Semiconductor Toll Free USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: [email protected] Phone: 81-3-5773-3850 Sales Representative Rev. 2 | Page 13 of 13 | www.onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit