TPD4S012 www.ti.com SLVS928A – MARCH 2009 – REVISED NOVEMBER 2009 4-CHANNEL ESD SOLUTION FOR USB-HS/USB OTG/USB CHARGER INTERFACE Check for Samples: TPD4S012 FEATURES 1 • • • • • • • • • Integrated ESD Clamps for D+, D–, VBUS, and ID Pins to Provide Single-Chip ESD Protection for USB High Speed, USB-OTG, and USB Charger Interface Special Snap Back Technology Allows High-voltage Tolerance During Normal Operation while Reducing the Clamp Voltage during System Level ESD Stress USB Signal Pins (D+, D–, ID) – 0.8-pF Line Capacitance – Tolerates 6 V Signal VBUS Line (VBUS) – 11-pF Line Capacitance – Tolerates 20 V Signal Flow-Through Pin Mapping for the High-Speed Lines Ensures Zero Additional Skew Due to Board Layout While Placing the ESD Protection Chip Near the Connector Supports Data Rates in Excess of 480 Mbps IEC 61000-4-2 (Level 4) System Level ESD Compliance Measured at the D+, D–, and ID Pins – ±10-kV IEC 61000-4-2 Contact Discharge – ±10-kV IEC 61000-4-2 Air-Gap Discharge 3 Amps Peak Pulse Current (8/20 μs Pulse) for VBUS and D+, D–, and ID Lines Industrial Temperature Range: –40°C to 85°C APPLICATIONS • • • • • Cellular Phones Digital Cameras Global Positioning Systems (GPS) Portable Digital Assistants (PDA) Portable Computers DRY PACKAGE (TOP VIEW) D+ 1 6 VBUS D– 2 5 N.C. ID 3 4 GND YFP PACKAGE (TOP VIEW) D+ D– VBUS A1 C1 WGND E VI E PR B1 A2 B2 ID C2 VBUS N.C. – Not internally connected D+, D–, and ID pins are exact equivalent ESD clamp circuits. Any of these pins can be connected to any other D+, D–, or ID pin if it becomes easier to route the traces from the USB connector. DESCRIPTION The TPD4S012 is a four-channel electrostatic discharge (ESD) solution for USB charger or USB on-the-go (OTG) interface. In many cell phone applications, the USB connector is the de facto communication port for external communications like high-speed data transfer, audio signal, charging, car-kit, etc. In order to support different interfaces, the USB port needs to handle different voltage levels. For example, some chargers require the VBUS port of the USB connector to handle in excess of the normal VBUS voltage per USB specifications. The TPD4S012 offers combinations of two different clamp voltages to match the voltage tolerances of the different signal interfaces using the common USB connector. Refer to Figure 5-6 & Figure 9-12, special snap back technology allows high-voltage tolerance during normal operation while reducing the clamp voltage during system level ESD stress. The TPD4S012 conforms to IEC61000-4-2 (Level 4) ESD. The device is offered in space-saving packages with flow-through pin mapping. The TPD4S012 is characterized for operation over ambient air temperature of –40°C to 85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPD4S012 SLVS928A – MARCH 2009 – REVISED NOVEMBER 2009 www.ti.com ORDERING INFORMATION TA PACKAGE –40°C to 85°C (1) (2) (1) (2) ORDERABLE PART NUMBER NOMINAL DIMENSIONS (mm) TOP-SIDE MARKING SON – DRY Reel of 3000 W = 1.0, L = 1.45, H = 0.55, Pitch = 0.5 TPD4S012DRYR 3B WCSP – XXX Reel of 3000 W = 0.8, L = 1.2, H = 0.5, Pitch = 0.4 TPD4S012XXXR TBD Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. APPLICATION SCHEMATIC VBUS VBUS D+ D+ PMU/USB Controller D– - D– ID ID GND GND If the ID pin is not used, it can be left floating. Board Layout Recommendations GND ID Core PMU Chip/ USB Controller D– D+ VBUS Figure 1. Using DRY Package VBUS Core PMU Chip/ USB Controller ID C2 C1 B2 B1 A2 A2 A1 VBUS D– GND D+ Figure 2. Using YFP Package The TPD4S012 can provide system-level ESD protection to the high-speed differential ports. The flow-through package offers flexibility for board routing. Figure 1 and Figure 2 show the board layout scheme for the D+ and D– lines of a single differential pair. It allows the differential signal pairs couple together right after they touch the ESD ports of the TPD4S012. 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD4S012 TPD4S012 www.ti.com SLVS928A – MARCH 2009 – REVISED NOVEMBER 2009 CIRCUIT DIAGRAM VBUS D+ D– ID GND TERMINAL FUNCTIONS TERMINAL TYPE DESCRIPTION DRY PIN NO. XXX BALL NO. NAME 1 A1 D+ ESD clamp Provides ESD protection to the high-speed differential data lines 2 B1 D– ESD clamp Provides ESD protection to the high-speed differential data lines 3 B2 ID ESD clamp Provides ESD protection to the high-speed differential data lines 4 A2 GND Pwr 5 – N.C. – 6 C1, C2 VBUS ESD clamp Ground Not internally connected ESD clamp for high-voltage tolerant VBUS line(s) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) MIN MAX VBUS voltage tolerance VBUS pin –0.3 20 IO voltage tolerance D+, D–, ID pins –0.3 6 V –65 125 °C Tstg Storage temperature range TA Operating free-air temperature range –40 UNIT V 85 °C IEC 61000-4-2 Contact Discharge D+, D–, ID ±10 kV IEC 61000-4-2 Air-Gap Discharge D+, D–, ID ±10 kV IEC 61000-4-2 Contact Discharge VBUS pin ±10 kV IEC 61000-4-2 Air-Gap Discharge VBUS pin ±9 kV Peak pulse power (tp = 8/20 μs) D+, D–, ID, VBUS pins 60 W Peak pulse current (tp = 8/20 μs) D+, D–, ID, VBUS pins 3 A Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD4S012 3 TPD4S012 SLVS928A – MARCH 2009 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VBUS = 5 V IVBUS VBUS operating current IIO IO port current VIO = 2.5 V, VBUS = D+, D–, ID pins 5V VD Diode forward voltage IIO = 8 mA CVBUS VBUS pin capacitance VBUS = 5 V CIO RDYN D+, D–, ID pins (lower clamp diode) Breakdown voltage 0.6 MAX UNIT μA 0.1 0.5 0.1 0.5 μA 0.8 0.95 V 11 15 pF VIO = 2.5 V D+, D–, ID pins (DRY package) 0.8 1 pF IIO = 1.5 A D+, D–, ID, and VBUS pins, including central clamp dioded during positive ESD pulse 1.2 IIO = 1 A D+, D–, ID, and VBUS pins, including central clamp diode during negative ESD pulse Dynamic resistance VBR TYP D+, D–, ID pins open VBUS = 19 V IO capacitance MIN Ω 1 D+, D–, ID pins IIO = 1 mA VBUS pin(s) 6 9 20 24 V TYPICAL CHARACTERISTICS 6.0 3.5 5.5 Power 3.0 5.0 Current 4.5 2.5 3.5 IPP (A) IPP (A) 4.0 3.0 2.5 2.0 1.5 Power 2.0 Current 1.0 1.5 1.0 0.5 0.5 0 0 0 5 10 15 20 25 30 35 40 45 50 0 5 Time (ms) 15 20 25 30 35 40 45 50 Time (ms) Figure 3. Peak Pulse Power Waveform at the D+, D–, or ID Pin 4 10 Figure 4. Peak Pulse Power Waveform at the VBUS Pin Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD4S012 TPD4S012 www.ti.com SLVS928A – MARCH 2009 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS (continued) 2.0 1.8 1.8 1.6 1.6 1.4 1.2 1.2 Current (A) Current (A) 1.4 1.0 0.8 1.0 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 2 4 6 8 10 Voltage (V) 10 12 5 0 14 Figure 5. D+, D–, or ID Clamp Voltage Under ESD Event 10 15 20 Voltage (V) 25 30 Figure 6. VBUS Clamp Voltage Under ESD Event 1.70E-12 1.80E-11 1.60E-12 1.70E-11 1.50E-12 1.60E-11 1.40E-12 1.50E-11 1.40E-11 VBUS to GND 1.20E-12 Farads Farads 1.30E-12 1.10E-12 1.00E-12 1.30E-11 1.20E-11 D+ to GND 9.00E-13 1.10E-11 8.00E-13 1.00E-11 7.00E-13 0.0 1.0 2.0 3.0 4.0 9.00E-12 0.0 5.0 1.0 2.0 Figure 7. D+, D–, or ID Capacitance, TA = 27°C 4.0 5.0 Figure 8. VBUS Capacitance, TA = 27°C 140 40 120 20 100 0 80 Amplitude (V) Amplitude (V) 3.0 Volts Volts 60 40 20 –20 –40 –60 –80 0 –100 –20 –40 –120 0 25 50 75 100 125 150 Time (ns) 175 200 225 250 Figure 9. IEC Clamping Waveform, 8 kV Contact, D+, 25 ns/div 0 25 50 75 100 125 150 Time (ns) 175 200 225 250 Figure 10. IEC Clamping Waveform, –8 kV Contact, D+, 25 ns/div Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD4S012 5 TPD4S012 SLVS928A – MARCH 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) 140 40 120 20 0 80 Amplitude (V) Amplitude (V) 100 60 40 20 –40 –60 –80 0 –100 –20 –40 –120 0 25 50 75 100 125 150 Time (ns) 175 200 225 250 Figure 11. VBUS IEC Clamping Waveform, 8 kV Contact, D+, 25 ns/div 6 –20 0 25 50 75 100 125 150 Time (ns) 175 200 225 250 Figure 12. VBUS IEC Clamping Waveform, –8 kV Contact, D+, 25 ns/div Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPD4S012 PACKAGE OPTION ADDENDUM www.ti.com 31-Jul-2010 PACKAGING INFORMATION Orderable Device TPD4S012DRYR Status (1) ACTIVE Package Type Package Drawing SON DRY Pins Package Qty 6 5000 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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